processor-2000/registers.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity registers is
    Port ( addr_A : in STD_LOGIC_VECTOR (3 downto 0);
           addr_B : in STD_LOGIC_VECTOR (3 downto 0);
           addr_W : in STD_LOGIC_VECTOR (3 downto 0);
           W : in STD_LOGIC;
           DATA : in STD_LOGIC_VECTOR (7 downto 0);
           RST : in STD_LOGIC;
           CLK : in STD_LOGIC;
           QA : out STD_LOGIC_VECTOR (7 downto 0);
           QB : out STD_LOGIC_VECTOR (7 downto 0));
end registers;

architecture Behavioral of registers is
	type REGISTER_BANK is array (15 downto 0) of std_logic_vector(7 downto 0);
	SIGNAL RB : REGISTER_BANK;
begin
	process
	begin
		wait until CLK'event and CLK='1';
			if (RST = '0') then
				RB <= (others => (others => '0'));
			elsif (W = '1') then
				RB(to_integer(unsigned(addr_W))) <= DATA;
			end if;
	end process;
	
	QA <= RB(to_integer(unsigned(addr_A))) when W = '0' or addr_W /= addr_A else DATA;
	QB <= RB(to_integer(unsigned(addr_B))) when W = '0' or addr_W /= addr_B else DATA;

end Behavioral;