processor-2000/data_memory_test.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY data_memory_test IS
END data_memory_test;
 
ARCHITECTURE behavior OF data_memory_test IS 
  
    COMPONENT data_memory
    PORT(
         addr : IN  std_logic_vector(7 downto 0);
         data : IN  std_logic_vector(7 downto 0);
         rw : IN  std_logic;
         rst : IN  std_logic;
         clk : IN  std_logic;
         q : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal addr : std_logic_vector(7 downto 0) := (others => '0');
   signal data : std_logic_vector(7 downto 0) := (others => '0');
   signal rw : std_logic := '0';
   signal rst : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal q : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: data_memory PORT MAP (
          addr => addr,
          data => data,
          rw => rw,
          rst => rst,
          clk => clk,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin				
		addr <=
		"00000000",
		"00000010" after 1*CLK_period,
		"00000110" after 2*CLK_period,
		"00001000" after 3*CLK_period,
		"00001100" after 4*CLK_period,
		"00000000" after 5*CLK_period,
		"00000001" after 6*CLK_period,
		"00000010" after 8*CLK_period,
		"00000000" after 9*CLK_period,
		"00001111" after 11*CLK_period;


		DATA <= 
		"01010101",
		"10101010" after 6*CLK_period,
		"00000000" after 7*CLK_period,
		"11111111" after 8*CLK_period,
		"00001111" after 10*CLK_period;
		
		rw <=
		'1',
		'0' after 5*CLK_period,
		'1' after 9*CLK_period,
		'0' after 10*CLK_period;
		
		RST <= '1' after clk_period, '0' after 12*CLK_period;
		
      wait;
   end process;

END;