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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.NUMERIC_STD.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
- entity CPU is
- Port (
- clk : in STD_LOGIC;
- rst : in STD_LOGIC
- );
- end CPU;
-
- architecture Behavioral of CPU is
- constant NOP : std_logic_vector(7 downto 0) := "00000000";
- constant ADD : std_logic_vector(7 downto 0) := "00000001";
- constant MUL : std_logic_vector(7 downto 0) := "00000010";
- constant SOU : std_logic_vector(7 downto 0) := "00000011";
- constant DIV : std_logic_vector(7 downto 0) := "00000100";
- constant COP : std_logic_vector(7 downto 0) := "00000101";
- constant AFC : std_logic_vector(7 downto 0) := "00000110";
- constant LOAD : std_logic_vector(7 downto 0) := "00000111";
- constant STORE: std_logic_vector(7 downto 0) := "00001000";
- -- constant HALT : std_logic_vector(7 downto 0) := "00001001";
-
- constant MX1: std_logic_vector(8 downto 0) := "100111110";
- constant MX2: std_logic_vector(8 downto 0) := "000011110";
-
- COMPONENT ALU
- PORT(
- A : IN std_logic_vector(7 downto 0);
- B : IN std_logic_vector(7 downto 0);
- S : OUT std_logic_vector(7 downto 0);
- O : OUT std_logic;
- Z : OUT std_logic;
- C : OUT std_logic;
- Ctrl : IN std_logic_vector(1 downto 0)
- );
- END COMPONENT;
-
- COMPONENT registers
- PORT(
- addr_A : IN std_logic_vector(0 to 3);
- addr_B : IN std_logic_vector(0 to 3);
- addr_W : IN std_logic_vector(0 to 3);
- W : IN std_logic;
- DATA : IN std_logic_vector(0 to 7);
- RST : IN std_logic;
- CLK : IN std_logic;
- QA : OUT std_logic_vector(0 to 7);
- QB : OUT std_logic_vector(0 to 7)
- );
- END COMPONENT;
-
- COMPONENT instruction_memory
- PORT(
- addr : IN std_logic_vector(7 downto 0);
- q : OUT std_logic_vector(31 downto 0);
- clk : IN std_logic
- );
- END COMPONENT;
-
-
- COMPONENT data_memory
- PORT(
- addr : IN std_logic_vector(7 downto 0);
- data : IN std_logic_vector(7 downto 0);
- rw : IN std_logic;
- rst : IN std_logic;
- clk : IN std_logic;
- q : OUT std_logic_vector(7 downto 0)
- );
- END COMPONENT;
-
- signal halted : std_logic := '0';
-
- -- Interfaces composants
- signal ALU_A : std_logic_vector(7 downto 0);
- signal ALU_B : std_logic_vector(7 downto 0);
- signal ALU_S : std_logic_vector(7 downto 0);
- signal ALU_O : std_logic;
- signal ALU_Z : std_logic;
- signal ALU_C : std_logic;
- signal ALU_Ctrl : std_logic_vector(1 downto 0);
-
- signal registers_addr_A : std_logic_vector(3 downto 0) := (others => '0');
- signal registers_addr_B : std_logic_vector(3 downto 0) := (others => '0');
- signal registers_addr_W : std_logic_vector(3 downto 0) := (others => '0');
- signal registers_W : std_logic := '0';
- signal registers_DATA : std_logic_vector(7 downto 0) := (others => '0');
- signal registers_QA : std_logic_vector(7 downto 0);
- signal registers_QB : std_logic_vector(7 downto 0);
-
- signal data_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
- signal data_memory_data : std_logic_vector(7 downto 0) := (others => '0');
- signal data_memory_rw : std_logic := '1';
- signal data_memory_q : std_logic_vector(7 downto 0);
-
- signal instr_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
- signal instr_memory_q : std_logic_vector(31 downto 0);
-
- -- Etage 1
- signal OP1_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal C1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-
- -- Etage 2
- signal OP2_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal C2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-
- -- Etage 3
- signal OP3_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-
- -- Etage 4
- signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal OP4_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
- signal A4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
- signal B4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-
- -- Aleas
- signal alea_write_P3: std_logic := '0';
- signal alea_write_P3_reg: std_logic_vector(3 downto 0) := "0000";
- signal alea_write_P2: std_logic := '0';
- signal alea_write_P2_reg: std_logic_vector(3 downto 0) := "0000";
- signal alea_read_B_P1: std_logic := '0';
- signal alea_read_B_P1_reg: std_logic_vector(3 downto 0) := "0000";
- signal alea_read_C_P1: std_logic := '0';
- signal alea_read_C_P1_reg: std_logic_vector(3 downto 0) := "0000";
- signal alea: std_logic := '0';
-
- begin
- myalu: ALU PORT MAP (
- A => alu_a,
- B => alu_b,
- S => alu_s,
- O => alu_o,
- Z => alu_z,
- C => alu_c,
- Ctrl => alu_ctrl
- );
-
- reg: registers PORT MAP (
- addr_A => registers_addr_A,
- addr_B => registers_addr_B,
- addr_W => registers_addr_W,
- W => registers_W,
- DATA => registers_data,
- RST => rst,
- CLK => clk,
- QA => registers_qa,
- QB => registers_qb
- );
-
- data_mem: data_memory PORT MAP (
- addr => data_memory_addr,
- data => data_memory_data,
- rw => data_memory_rw,
- rst => rst,
- clk => clk,
- q => data_memory_q
- );
-
- instr_mem: instruction_memory PORT MAP (
- addr => instr_memory_addr,
- q => instr_memory_q,
- clk => clk
- );
-
- instr_memory_addr <= IP;
-
- registers_addr_W <= A4(3 downto 0);
- registers_W <= '0' when (OP4 = NOP or OP4 = STORE) else '1';
- registers_data <= B4;
- registers_addr_A <= B1(3 downto 0);
- registers_addr_B <= C1(3 downto 0);
-
- ALU_A <= B2;
- ALU_B <= C2;
- ALU_Ctrl <= OP2(1 downto 0);
-
- data_memory_RW <= '0' when (OP3 = STORE) else '1';
- data_memory_addr <= A3 when (OP3 = STORE) else B3;
- data_memory_data <= B3;
-
- -- Etage 1
- OP1_in <= instr_memory_q(31 downto 24);
- A1_in <= instr_memory_q(23 downto 16);
- B1_in <= instr_memory_q(15 downto 8);
- C1_in <= instr_memory_q(7 downto 0);
-
- OP1 <= OP1_in;
- A1 <= A1_in;
- B1 <= B1_in;
- C1 <= C1_in;
-
- -- Etage 2
- OP2_in <= OP1;
- A2_in <= A1;
- B2_in <= registers_QA when (MX1(to_integer(unsigned(OP1))) = '1') else B1;
- C2_in <= registers_QB;
-
- -- Etage 3
- OP3_in <= OP2;
- A3_in <= A2;
- B3_in <= ALU_S when (MX2(to_integer(unsigned(OP2))) = '1') else B2;
-
- -- Etage 4
- OP4_in <= OP3;
- A4_in <= A3;
- B4_in <= data_memory_Q when (OP3 = LOAD) else B3;
-
- -- Aleas
- alea_write_P3 <= '0' when (OP4_in = NOP or OP4_in = STORE) else '1';
- alea_write_P3_reg <= A4_in(3 downto 0);
- alea_write_P2 <= '0' when (OP3_in = NOP or OP3_in = STORE) else '1';
- alea_write_P2_reg <= A3_in(3 downto 0);
- alea_read_B_P1 <= '0' when (OP1_in = NOP or OP1_in = AFC or OP1_in = LOAD) else '1';
- alea_read_B_P1_reg <= B1_in(3 downto 0);
- alea_read_C_P1 <= '1' when (OP1_in = ADD or OP1_in = MUL or OP1_in = DIV or OP1_in = SOU) else '0';
- alea_read_C_P1_reg <= C1_in(3 downto 0);
-
- alea <= '1'
- when (
- (alea_write_P3 = '1' and alea_read_B_P1 = '1' and alea_write_P3_reg = alea_read_B_P1_reg) or
- (alea_write_P3 = '1' and alea_read_C_P1 = '1' and alea_write_P3_reg = alea_read_C_P1_reg) or
- (alea_write_P2 = '1' and alea_read_B_P1 = '1' and alea_write_P2_reg = alea_read_B_P1_reg) or
- (alea_write_P2 = '1' and alea_read_C_P1 = '1' and alea_write_P2_reg = alea_read_C_P1_reg))
- else '0';
-
- process
- begin
- wait until CLK'event and CLK='1';
- if (halted = '0') then
- -- Etage 3 -> 4
- OP4 <= OP4_in;
- A4 <= A4_in;
- B4 <= B4_in;
-
- -- Etage 2 -> 3
- OP3 <= OP3_in;
- A3 <= A3_in;
- B3 <= B3_in;
-
- -- Etage 1 -> 2
- if (alea = '0') then
- OP2 <= OP2_in;
- A2 <= A2_in;
- B2 <= B2_in;
- C2 <= C2_in;
-
- IP <= IP + 1;
- else
- OP2 <= NOP;
- A2 <= "00000000";
- B2 <= "00000000";
- C2 <= "00000000";
- end if;
- end if;
-
- end process;
-
- end Behavioral;
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