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CPU.vhd 8.5KB

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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5. entity CPU is
  6. Port (
  7. clk : in STD_LOGIC;
  8. rst : in STD_LOGIC
  9. );
  10. end CPU;
  11. architecture Behavioral of CPU is
  12. constant NOP : std_logic_vector(7 downto 0) := "00000000";
  13. constant ADD : std_logic_vector(7 downto 0) := "00000001";
  14. constant MUL : std_logic_vector(7 downto 0) := "00000010";
  15. constant SOU : std_logic_vector(7 downto 0) := "00000011";
  16. constant DIV : std_logic_vector(7 downto 0) := "00000100";
  17. constant COP : std_logic_vector(7 downto 0) := "00000101";
  18. constant AFC : std_logic_vector(7 downto 0) := "00000110";
  19. constant LOAD : std_logic_vector(7 downto 0) := "00000111";
  20. constant STORE: std_logic_vector(7 downto 0) := "00001000";
  21. -- constant HALT : std_logic_vector(7 downto 0) := "00001001";
  22. constant MX1: std_logic_vector(8 downto 0) := "100111110";
  23. constant MX2: std_logic_vector(8 downto 0) := "000011110";
  24. COMPONENT ALU
  25. PORT(
  26. A : IN std_logic_vector(7 downto 0);
  27. B : IN std_logic_vector(7 downto 0);
  28. S : OUT std_logic_vector(7 downto 0);
  29. O : OUT std_logic;
  30. Z : OUT std_logic;
  31. C : OUT std_logic;
  32. Ctrl : IN std_logic_vector(1 downto 0)
  33. );
  34. END COMPONENT;
  35. COMPONENT registers
  36. PORT(
  37. addr_A : IN std_logic_vector(0 to 3);
  38. addr_B : IN std_logic_vector(0 to 3);
  39. addr_W : IN std_logic_vector(0 to 3);
  40. W : IN std_logic;
  41. DATA : IN std_logic_vector(0 to 7);
  42. RST : IN std_logic;
  43. CLK : IN std_logic;
  44. QA : OUT std_logic_vector(0 to 7);
  45. QB : OUT std_logic_vector(0 to 7)
  46. );
  47. END COMPONENT;
  48. COMPONENT instruction_memory
  49. PORT(
  50. addr : IN std_logic_vector(7 downto 0);
  51. q : OUT std_logic_vector(31 downto 0);
  52. clk : IN std_logic
  53. );
  54. END COMPONENT;
  55. COMPONENT data_memory
  56. PORT(
  57. addr : IN std_logic_vector(7 downto 0);
  58. data : IN std_logic_vector(7 downto 0);
  59. rw : IN std_logic;
  60. rst : IN std_logic;
  61. clk : IN std_logic;
  62. q : OUT std_logic_vector(7 downto 0)
  63. );
  64. END COMPONENT;
  65. signal halted : std_logic := '0';
  66. -- Interfaces composants
  67. signal ALU_A : std_logic_vector(7 downto 0);
  68. signal ALU_B : std_logic_vector(7 downto 0);
  69. signal ALU_S : std_logic_vector(7 downto 0);
  70. signal ALU_O : std_logic;
  71. signal ALU_Z : std_logic;
  72. signal ALU_C : std_logic;
  73. signal ALU_Ctrl : std_logic_vector(1 downto 0);
  74. signal registers_addr_A : std_logic_vector(3 downto 0) := (others => '0');
  75. signal registers_addr_B : std_logic_vector(3 downto 0) := (others => '0');
  76. signal registers_addr_W : std_logic_vector(3 downto 0) := (others => '0');
  77. signal registers_W : std_logic := '0';
  78. signal registers_DATA : std_logic_vector(7 downto 0) := (others => '0');
  79. signal registers_QA : std_logic_vector(7 downto 0);
  80. signal registers_QB : std_logic_vector(7 downto 0);
  81. signal data_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
  82. signal data_memory_data : std_logic_vector(7 downto 0) := (others => '0');
  83. signal data_memory_rw : std_logic := '1';
  84. signal data_memory_q : std_logic_vector(7 downto 0);
  85. signal instr_memory_addr : std_logic_vector(7 downto 0) := (others => '0');
  86. signal instr_memory_q : std_logic_vector(31 downto 0);
  87. -- Etage 1
  88. signal OP1_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  89. signal A1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  90. signal B1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  91. signal C1_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  92. signal IP : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  93. signal OP1 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  94. signal A1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  95. signal B1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  96. signal C1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  97. -- Etage 2
  98. signal OP2_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  99. signal A2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  100. signal B2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  101. signal C2_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  102. signal OP2 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  103. signal A2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  104. signal B2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  105. signal C2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  106. -- Etage 3
  107. signal OP3_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  108. signal A3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  109. signal B3_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  110. signal OP3 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  111. signal A3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  112. signal B3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  113. -- Etage 4
  114. signal OP4 : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  115. signal A4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  116. signal B4 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  117. signal OP4_in : STD_LOGIC_VECTOR(7 downto 0) := NOP;
  118. signal A4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  119. signal B4_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
  120. -- Aleas
  121. signal alea_write_P3: std_logic := '0';
  122. signal alea_write_P3_reg: std_logic_vector(3 downto 0) := "0000";
  123. signal alea_write_P2: std_logic := '0';
  124. signal alea_write_P2_reg: std_logic_vector(3 downto 0) := "0000";
  125. signal alea_read_B_P1: std_logic := '0';
  126. signal alea_read_B_P1_reg: std_logic_vector(3 downto 0) := "0000";
  127. signal alea_read_C_P1: std_logic := '0';
  128. signal alea_read_C_P1_reg: std_logic_vector(3 downto 0) := "0000";
  129. signal alea: std_logic := '0';
  130. begin
  131. myalu: ALU PORT MAP (
  132. A => alu_a,
  133. B => alu_b,
  134. S => alu_s,
  135. O => alu_o,
  136. Z => alu_z,
  137. C => alu_c,
  138. Ctrl => alu_ctrl
  139. );
  140. reg: registers PORT MAP (
  141. addr_A => registers_addr_A,
  142. addr_B => registers_addr_B,
  143. addr_W => registers_addr_W,
  144. W => registers_W,
  145. DATA => registers_data,
  146. RST => rst,
  147. CLK => clk,
  148. QA => registers_qa,
  149. QB => registers_qb
  150. );
  151. data_mem: data_memory PORT MAP (
  152. addr => data_memory_addr,
  153. data => data_memory_data,
  154. rw => data_memory_rw,
  155. rst => rst,
  156. clk => clk,
  157. q => data_memory_q
  158. );
  159. instr_mem: instruction_memory PORT MAP (
  160. addr => instr_memory_addr,
  161. q => instr_memory_q,
  162. clk => clk
  163. );
  164. instr_memory_addr <= IP;
  165. registers_addr_W <= A4(3 downto 0);
  166. registers_W <= '0' when (OP4 = NOP or OP4 = STORE) else '1';
  167. registers_data <= B4;
  168. registers_addr_A <= B1(3 downto 0);
  169. registers_addr_B <= C1(3 downto 0);
  170. ALU_A <= B2;
  171. ALU_B <= C2;
  172. ALU_Ctrl <= OP2(1 downto 0);
  173. data_memory_RW <= '0' when (OP3 = STORE) else '1';
  174. data_memory_addr <= A3 when (OP3 = STORE) else B3;
  175. data_memory_data <= B3;
  176. -- Etage 1
  177. OP1_in <= instr_memory_q(31 downto 24);
  178. A1_in <= instr_memory_q(23 downto 16);
  179. B1_in <= instr_memory_q(15 downto 8);
  180. C1_in <= instr_memory_q(7 downto 0);
  181. OP1 <= OP1_in;
  182. A1 <= A1_in;
  183. B1 <= B1_in;
  184. C1 <= C1_in;
  185. -- Etage 2
  186. OP2_in <= OP1;
  187. A2_in <= A1;
  188. B2_in <= registers_QA when (MX1(to_integer(unsigned(OP1))) = '1') else B1;
  189. C2_in <= registers_QB;
  190. -- Etage 3
  191. OP3_in <= OP2;
  192. A3_in <= A2;
  193. B3_in <= ALU_S when (MX2(to_integer(unsigned(OP2))) = '1') else B2;
  194. -- Etage 4
  195. OP4_in <= OP3;
  196. A4_in <= A3;
  197. B4_in <= data_memory_Q when (OP3 = LOAD) else B3;
  198. -- Aleas
  199. alea_write_P3 <= '0' when (OP4_in = NOP or OP4_in = STORE) else '1';
  200. alea_write_P3_reg <= A4_in(3 downto 0);
  201. alea_write_P2 <= '0' when (OP3_in = NOP or OP3_in = STORE) else '1';
  202. alea_write_P2_reg <= A3_in(3 downto 0);
  203. alea_read_B_P1 <= '0' when (OP1_in = NOP or OP1_in = AFC or OP1_in = LOAD) else '1';
  204. alea_read_B_P1_reg <= B1_in(3 downto 0);
  205. alea_read_C_P1 <= '1' when (OP1_in = ADD or OP1_in = MUL or OP1_in = DIV or OP1_in = SOU) else '0';
  206. alea_read_C_P1_reg <= C1_in(3 downto 0);
  207. alea <= '1'
  208. when (
  209. (alea_write_P3 = '1' and alea_read_B_P1 = '1' and alea_write_P3_reg = alea_read_B_P1_reg) or
  210. (alea_write_P3 = '1' and alea_read_C_P1 = '1' and alea_write_P3_reg = alea_read_C_P1_reg) or
  211. (alea_write_P2 = '1' and alea_read_B_P1 = '1' and alea_write_P2_reg = alea_read_B_P1_reg) or
  212. (alea_write_P2 = '1' and alea_read_C_P1 = '1' and alea_write_P2_reg = alea_read_C_P1_reg))
  213. else '0';
  214. process
  215. begin
  216. wait until CLK'event and CLK='1';
  217. if (halted = '0') then
  218. -- Etage 3 -> 4
  219. OP4 <= OP4_in;
  220. A4 <= A4_in;
  221. B4 <= B4_in;
  222. -- Etage 2 -> 3
  223. OP3 <= OP3_in;
  224. A3 <= A3_in;
  225. B3 <= B3_in;
  226. -- Etage 1 -> 2
  227. if (alea = '0') then
  228. OP2 <= OP2_in;
  229. A2 <= A2_in;
  230. B2 <= B2_in;
  231. C2 <= C2_in;
  232. IP <= IP + 1;
  233. else
  234. OP2 <= NOP;
  235. A2 <= "00000000";
  236. B2 <= "00000000";
  237. C2 <= "00000000";
  238. end if;
  239. end if;
  240. end process;
  241. end Behavioral;