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- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.numeric_std.ALL;
-
- ENTITY ALU_test IS
- END ALU_test;
-
- ARCHITECTURE behavior OF ALU_test IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT ALU
- PORT(
- A : IN std_logic_vector(7 downto 0);
- B : IN std_logic_vector(7 downto 0);
- S : OUT std_logic_vector(7 downto 0);
- O : OUT std_logic;
- Z : OUT std_logic;
- C : OUT std_logic;
- Ctrl : IN std_logic_vector(1 downto 0)
- );
- END COMPONENT;
-
-
- --Inputs
- signal A : std_logic_vector(7 downto 0) := (others => '0');
- signal B : std_logic_vector(7 downto 0) := (others => '0');
- signal Ctrl : std_logic_vector(1 downto 0) := (others => '0');
-
- --Outputs
- signal S : std_logic_vector(7 downto 0);
- signal O : std_logic;
- signal Z : std_logic;
- signal C : std_logic;
-
- BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: ALU PORT MAP (
- A => A,
- B => B,
- S => S,
- O => O,
- Z => Z,
- C => C,
- Ctrl => Ctrl
- );
-
- -- Stimulus process
- stim_proc: process
- begin
- A <=
- "00000001",
- "11111000" after 1 ms,
- "00000010" after 2 ms,
- "11001100" after 3 ms,
- "00000011" after 4 ms,
- "00000001" after 5 ms;
-
- B <=
- "00000011",
- "10000000" after 1 ms,
- "00000011" after 2 ms,
- "01100101" after 3 ms,
- "00000001" after 4 ms,
- "00000011" after 5 ms;
-
- Ctrl <=
- "01",
- "11" after 2 ms,
- "10" after 4 ms,
- "00" after 6 ms,
- "00" after 7 ms;
-
- wait;
- end process;
-
- END;
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