LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY instruction_memory_test IS
END instruction_memory_test;
 
ARCHITECTURE behavior OF instruction_memory_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT instruction_memory
    PORT(
         addr : IN  std_logic_vector(7 downto 0);
         q : OUT  std_logic_vector(31 downto 0);
         clk : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal addr : std_logic_vector(7 downto 0) := (others => '0');
   signal clk : std_logic := '0';

 	--Outputs
   signal q : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: instruction_memory PORT MAP (
          addr => addr,
          q => q,
          clk => clk
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin
		addr <=
		"00000000",
		"00000010" after 1*CLK_period,
		"00000110" after 2*CLK_period,
		"00001000" after 3*CLK_period,
		"00001100" after 4*CLK_period,
		"00000000" after 5*CLK_period,
		"00000001" after 6*CLK_period,
		"00000010" after 8*CLK_period,
		"00000000" after 9*CLK_period,
		"00001111" after 11*CLK_period;
      wait;
   end process;

END;