Dumber-Robot-Firmware.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00003f44 08000110 08000110 00010110 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000001ec 08004054 08004054 00014054 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 08004240 08004240 00014240 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 08004244 08004244 00014244 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 000001ec 20000000 08004248 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 000001a8 200001ec 08004434 000201ec 2**2 ALLOC 7 ._user_heap_stack 00000100 20000394 08004434 00020394 2**0 ALLOC 8 .ARM.attributes 00000029 00000000 00000000 000201ec 2**0 CONTENTS, READONLY 9 .debug_info 0000e654 00000000 00000000 00020215 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_abbrev 000025ac 00000000 00000000 0002e869 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_loc 00004ed6 00000000 00000000 00030e15 2**0 CONTENTS, READONLY, DEBUGGING 12 .debug_aranges 00000bf8 00000000 00000000 00035cf0 2**3 CONTENTS, READONLY, DEBUGGING 13 .debug_ranges 00000b20 00000000 00000000 000368e8 2**3 CONTENTS, READONLY, DEBUGGING 14 .debug_macro 00011ffb 00000000 00000000 00037408 2**0 CONTENTS, READONLY, DEBUGGING 15 .debug_line 00007e72 00000000 00000000 00049403 2**0 CONTENTS, READONLY, DEBUGGING 16 .debug_str 00056f77 00000000 00000000 00051275 2**0 CONTENTS, READONLY, DEBUGGING 17 .comment 0000007c 00000000 00000000 000a81ec 2**0 CONTENTS, READONLY 18 .debug_frame 000024c8 00000000 00000000 000a8268 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 08000110 <__do_global_dtors_aux>: 8000110: b510 push {r4, lr} 8000112: 4c05 ldr r4, [pc, #20] ; (8000128 <__do_global_dtors_aux+0x18>) 8000114: 7823 ldrb r3, [r4, #0] 8000116: b933 cbnz r3, 8000126 <__do_global_dtors_aux+0x16> 8000118: 4b04 ldr r3, [pc, #16] ; (800012c <__do_global_dtors_aux+0x1c>) 800011a: b113 cbz r3, 8000122 <__do_global_dtors_aux+0x12> 800011c: 4804 ldr r0, [pc, #16] ; (8000130 <__do_global_dtors_aux+0x20>) 800011e: f3af 8000 nop.w 8000122: 2301 movs r3, #1 8000124: 7023 strb r3, [r4, #0] 8000126: bd10 pop {r4, pc} 8000128: 200001ec .word 0x200001ec 800012c: 00000000 .word 0x00000000 8000130: 0800403c .word 0x0800403c 08000134 : 8000134: b508 push {r3, lr} 8000136: 4b03 ldr r3, [pc, #12] ; (8000144 ) 8000138: b11b cbz r3, 8000142 800013a: 4903 ldr r1, [pc, #12] ; (8000148 ) 800013c: 4803 ldr r0, [pc, #12] ; (800014c ) 800013e: f3af 8000 nop.w 8000142: bd08 pop {r3, pc} 8000144: 00000000 .word 0x00000000 8000148: 200001f0 .word 0x200001f0 800014c: 0800403c .word 0x0800403c 08000150 : 8000150: 4603 mov r3, r0 8000152: f813 2b01 ldrb.w r2, [r3], #1 8000156: 2a00 cmp r2, #0 8000158: d1fb bne.n 8000152 800015a: 1a18 subs r0, r3, r0 800015c: 3801 subs r0, #1 800015e: 4770 bx lr 08000160 <__aeabi_drsub>: 8000160: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000164: e002 b.n 800016c <__adddf3> 8000166: bf00 nop 08000168 <__aeabi_dsub>: 8000168: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800016c <__adddf3>: 800016c: b530 push {r4, r5, lr} 800016e: ea4f 0441 mov.w r4, r1, lsl #1 8000172: ea4f 0543 mov.w r5, r3, lsl #1 8000176: ea94 0f05 teq r4, r5 800017a: bf08 it eq 800017c: ea90 0f02 teqeq r0, r2 8000180: bf1f itttt ne 8000182: ea54 0c00 orrsne.w ip, r4, r0 8000186: ea55 0c02 orrsne.w ip, r5, r2 800018a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800018e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000192: f000 80e2 beq.w 800035a <__adddf3+0x1ee> 8000196: ea4f 5454 mov.w r4, r4, lsr #21 800019a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800019e: bfb8 it lt 80001a0: 426d neglt r5, r5 80001a2: dd0c ble.n 80001be <__adddf3+0x52> 80001a4: 442c add r4, r5 80001a6: ea80 0202 eor.w r2, r0, r2 80001aa: ea81 0303 eor.w r3, r1, r3 80001ae: ea82 0000 eor.w r0, r2, r0 80001b2: ea83 0101 eor.w r1, r3, r1 80001b6: ea80 0202 eor.w r2, r0, r2 80001ba: ea81 0303 eor.w r3, r1, r3 80001be: 2d36 cmp r5, #54 ; 0x36 80001c0: bf88 it hi 80001c2: bd30 pophi {r4, r5, pc} 80001c4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80001c8: ea4f 3101 mov.w r1, r1, lsl #12 80001cc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 80001d0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80001d4: d002 beq.n 80001dc <__adddf3+0x70> 80001d6: 4240 negs r0, r0 80001d8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80001dc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80001e0: ea4f 3303 mov.w r3, r3, lsl #12 80001e4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80001e8: d002 beq.n 80001f0 <__adddf3+0x84> 80001ea: 4252 negs r2, r2 80001ec: eb63 0343 sbc.w r3, r3, r3, lsl #1 80001f0: ea94 0f05 teq r4, r5 80001f4: f000 80a7 beq.w 8000346 <__adddf3+0x1da> 80001f8: f1a4 0401 sub.w r4, r4, #1 80001fc: f1d5 0e20 rsbs lr, r5, #32 8000200: db0d blt.n 800021e <__adddf3+0xb2> 8000202: fa02 fc0e lsl.w ip, r2, lr 8000206: fa22 f205 lsr.w r2, r2, r5 800020a: 1880 adds r0, r0, r2 800020c: f141 0100 adc.w r1, r1, #0 8000210: fa03 f20e lsl.w r2, r3, lr 8000214: 1880 adds r0, r0, r2 8000216: fa43 f305 asr.w r3, r3, r5 800021a: 4159 adcs r1, r3 800021c: e00e b.n 800023c <__adddf3+0xd0> 800021e: f1a5 0520 sub.w r5, r5, #32 8000222: f10e 0e20 add.w lr, lr, #32 8000226: 2a01 cmp r2, #1 8000228: fa03 fc0e lsl.w ip, r3, lr 800022c: bf28 it cs 800022e: f04c 0c02 orrcs.w ip, ip, #2 8000232: fa43 f305 asr.w r3, r3, r5 8000236: 18c0 adds r0, r0, r3 8000238: eb51 71e3 adcs.w r1, r1, r3, asr #31 800023c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000240: d507 bpl.n 8000252 <__adddf3+0xe6> 8000242: f04f 0e00 mov.w lr, #0 8000246: f1dc 0c00 rsbs ip, ip, #0 800024a: eb7e 0000 sbcs.w r0, lr, r0 800024e: eb6e 0101 sbc.w r1, lr, r1 8000252: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000256: d31b bcc.n 8000290 <__adddf3+0x124> 8000258: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800025c: d30c bcc.n 8000278 <__adddf3+0x10c> 800025e: 0849 lsrs r1, r1, #1 8000260: ea5f 0030 movs.w r0, r0, rrx 8000264: ea4f 0c3c mov.w ip, ip, rrx 8000268: f104 0401 add.w r4, r4, #1 800026c: ea4f 5244 mov.w r2, r4, lsl #21 8000270: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000274: f080 809a bcs.w 80003ac <__adddf3+0x240> 8000278: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800027c: bf08 it eq 800027e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000282: f150 0000 adcs.w r0, r0, #0 8000286: eb41 5104 adc.w r1, r1, r4, lsl #20 800028a: ea41 0105 orr.w r1, r1, r5 800028e: bd30 pop {r4, r5, pc} 8000290: ea5f 0c4c movs.w ip, ip, lsl #1 8000294: 4140 adcs r0, r0 8000296: eb41 0101 adc.w r1, r1, r1 800029a: f411 1f80 tst.w r1, #1048576 ; 0x100000 800029e: f1a4 0401 sub.w r4, r4, #1 80002a2: d1e9 bne.n 8000278 <__adddf3+0x10c> 80002a4: f091 0f00 teq r1, #0 80002a8: bf04 itt eq 80002aa: 4601 moveq r1, r0 80002ac: 2000 moveq r0, #0 80002ae: fab1 f381 clz r3, r1 80002b2: bf08 it eq 80002b4: 3320 addeq r3, #32 80002b6: f1a3 030b sub.w r3, r3, #11 80002ba: f1b3 0220 subs.w r2, r3, #32 80002be: da0c bge.n 80002da <__adddf3+0x16e> 80002c0: 320c adds r2, #12 80002c2: dd08 ble.n 80002d6 <__adddf3+0x16a> 80002c4: f102 0c14 add.w ip, r2, #20 80002c8: f1c2 020c rsb r2, r2, #12 80002cc: fa01 f00c lsl.w r0, r1, ip 80002d0: fa21 f102 lsr.w r1, r1, r2 80002d4: e00c b.n 80002f0 <__adddf3+0x184> 80002d6: f102 0214 add.w r2, r2, #20 80002da: bfd8 it le 80002dc: f1c2 0c20 rsble ip, r2, #32 80002e0: fa01 f102 lsl.w r1, r1, r2 80002e4: fa20 fc0c lsr.w ip, r0, ip 80002e8: bfdc itt le 80002ea: ea41 010c orrle.w r1, r1, ip 80002ee: 4090 lslle r0, r2 80002f0: 1ae4 subs r4, r4, r3 80002f2: bfa2 ittt ge 80002f4: eb01 5104 addge.w r1, r1, r4, lsl #20 80002f8: 4329 orrge r1, r5 80002fa: bd30 popge {r4, r5, pc} 80002fc: ea6f 0404 mvn.w r4, r4 8000300: 3c1f subs r4, #31 8000302: da1c bge.n 800033e <__adddf3+0x1d2> 8000304: 340c adds r4, #12 8000306: dc0e bgt.n 8000326 <__adddf3+0x1ba> 8000308: f104 0414 add.w r4, r4, #20 800030c: f1c4 0220 rsb r2, r4, #32 8000310: fa20 f004 lsr.w r0, r0, r4 8000314: fa01 f302 lsl.w r3, r1, r2 8000318: ea40 0003 orr.w r0, r0, r3 800031c: fa21 f304 lsr.w r3, r1, r4 8000320: ea45 0103 orr.w r1, r5, r3 8000324: bd30 pop {r4, r5, pc} 8000326: f1c4 040c rsb r4, r4, #12 800032a: f1c4 0220 rsb r2, r4, #32 800032e: fa20 f002 lsr.w r0, r0, r2 8000332: fa01 f304 lsl.w r3, r1, r4 8000336: ea40 0003 orr.w r0, r0, r3 800033a: 4629 mov r1, r5 800033c: bd30 pop {r4, r5, pc} 800033e: fa21 f004 lsr.w r0, r1, r4 8000342: 4629 mov r1, r5 8000344: bd30 pop {r4, r5, pc} 8000346: f094 0f00 teq r4, #0 800034a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800034e: bf06 itte eq 8000350: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000354: 3401 addeq r4, #1 8000356: 3d01 subne r5, #1 8000358: e74e b.n 80001f8 <__adddf3+0x8c> 800035a: ea7f 5c64 mvns.w ip, r4, asr #21 800035e: bf18 it ne 8000360: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000364: d029 beq.n 80003ba <__adddf3+0x24e> 8000366: ea94 0f05 teq r4, r5 800036a: bf08 it eq 800036c: ea90 0f02 teqeq r0, r2 8000370: d005 beq.n 800037e <__adddf3+0x212> 8000372: ea54 0c00 orrs.w ip, r4, r0 8000376: bf04 itt eq 8000378: 4619 moveq r1, r3 800037a: 4610 moveq r0, r2 800037c: bd30 pop {r4, r5, pc} 800037e: ea91 0f03 teq r1, r3 8000382: bf1e ittt ne 8000384: 2100 movne r1, #0 8000386: 2000 movne r0, #0 8000388: bd30 popne {r4, r5, pc} 800038a: ea5f 5c54 movs.w ip, r4, lsr #21 800038e: d105 bne.n 800039c <__adddf3+0x230> 8000390: 0040 lsls r0, r0, #1 8000392: 4149 adcs r1, r1 8000394: bf28 it cs 8000396: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800039a: bd30 pop {r4, r5, pc} 800039c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 80003a0: bf3c itt cc 80003a2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 80003a6: bd30 popcc {r4, r5, pc} 80003a8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80003ac: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 80003b0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80003b4: f04f 0000 mov.w r0, #0 80003b8: bd30 pop {r4, r5, pc} 80003ba: ea7f 5c64 mvns.w ip, r4, asr #21 80003be: bf1a itte ne 80003c0: 4619 movne r1, r3 80003c2: 4610 movne r0, r2 80003c4: ea7f 5c65 mvnseq.w ip, r5, asr #21 80003c8: bf1c itt ne 80003ca: 460b movne r3, r1 80003cc: 4602 movne r2, r0 80003ce: ea50 3401 orrs.w r4, r0, r1, lsl #12 80003d2: bf06 itte eq 80003d4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80003d8: ea91 0f03 teqeq r1, r3 80003dc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80003e0: bd30 pop {r4, r5, pc} 80003e2: bf00 nop 080003e4 <__aeabi_ui2d>: 80003e4: f090 0f00 teq r0, #0 80003e8: bf04 itt eq 80003ea: 2100 moveq r1, #0 80003ec: 4770 bxeq lr 80003ee: b530 push {r4, r5, lr} 80003f0: f44f 6480 mov.w r4, #1024 ; 0x400 80003f4: f104 0432 add.w r4, r4, #50 ; 0x32 80003f8: f04f 0500 mov.w r5, #0 80003fc: f04f 0100 mov.w r1, #0 8000400: e750 b.n 80002a4 <__adddf3+0x138> 8000402: bf00 nop 08000404 <__aeabi_i2d>: 8000404: f090 0f00 teq r0, #0 8000408: bf04 itt eq 800040a: 2100 moveq r1, #0 800040c: 4770 bxeq lr 800040e: b530 push {r4, r5, lr} 8000410: f44f 6480 mov.w r4, #1024 ; 0x400 8000414: f104 0432 add.w r4, r4, #50 ; 0x32 8000418: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 800041c: bf48 it mi 800041e: 4240 negmi r0, r0 8000420: f04f 0100 mov.w r1, #0 8000424: e73e b.n 80002a4 <__adddf3+0x138> 8000426: bf00 nop 08000428 <__aeabi_f2d>: 8000428: 0042 lsls r2, r0, #1 800042a: ea4f 01e2 mov.w r1, r2, asr #3 800042e: ea4f 0131 mov.w r1, r1, rrx 8000432: ea4f 7002 mov.w r0, r2, lsl #28 8000436: bf1f itttt ne 8000438: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 800043c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000440: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000444: 4770 bxne lr 8000446: f092 0f00 teq r2, #0 800044a: bf14 ite ne 800044c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000450: 4770 bxeq lr 8000452: b530 push {r4, r5, lr} 8000454: f44f 7460 mov.w r4, #896 ; 0x380 8000458: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800045c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000460: e720 b.n 80002a4 <__adddf3+0x138> 8000462: bf00 nop 08000464 <__aeabi_ul2d>: 8000464: ea50 0201 orrs.w r2, r0, r1 8000468: bf08 it eq 800046a: 4770 bxeq lr 800046c: b530 push {r4, r5, lr} 800046e: f04f 0500 mov.w r5, #0 8000472: e00a b.n 800048a <__aeabi_l2d+0x16> 08000474 <__aeabi_l2d>: 8000474: ea50 0201 orrs.w r2, r0, r1 8000478: bf08 it eq 800047a: 4770 bxeq lr 800047c: b530 push {r4, r5, lr} 800047e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 8000482: d502 bpl.n 800048a <__aeabi_l2d+0x16> 8000484: 4240 negs r0, r0 8000486: eb61 0141 sbc.w r1, r1, r1, lsl #1 800048a: f44f 6480 mov.w r4, #1024 ; 0x400 800048e: f104 0432 add.w r4, r4, #50 ; 0x32 8000492: ea5f 5c91 movs.w ip, r1, lsr #22 8000496: f43f aedc beq.w 8000252 <__adddf3+0xe6> 800049a: f04f 0203 mov.w r2, #3 800049e: ea5f 0cdc movs.w ip, ip, lsr #3 80004a2: bf18 it ne 80004a4: 3203 addne r2, #3 80004a6: ea5f 0cdc movs.w ip, ip, lsr #3 80004aa: bf18 it ne 80004ac: 3203 addne r2, #3 80004ae: eb02 02dc add.w r2, r2, ip, lsr #3 80004b2: f1c2 0320 rsb r3, r2, #32 80004b6: fa00 fc03 lsl.w ip, r0, r3 80004ba: fa20 f002 lsr.w r0, r0, r2 80004be: fa01 fe03 lsl.w lr, r1, r3 80004c2: ea40 000e orr.w r0, r0, lr 80004c6: fa21 f102 lsr.w r1, r1, r2 80004ca: 4414 add r4, r2 80004cc: e6c1 b.n 8000252 <__adddf3+0xe6> 80004ce: bf00 nop 080004d0 <__aeabi_dmul>: 80004d0: b570 push {r4, r5, r6, lr} 80004d2: f04f 0cff mov.w ip, #255 ; 0xff 80004d6: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80004da: ea1c 5411 ands.w r4, ip, r1, lsr #20 80004de: bf1d ittte ne 80004e0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80004e4: ea94 0f0c teqne r4, ip 80004e8: ea95 0f0c teqne r5, ip 80004ec: f000 f8de bleq 80006ac <__aeabi_dmul+0x1dc> 80004f0: 442c add r4, r5 80004f2: ea81 0603 eor.w r6, r1, r3 80004f6: ea21 514c bic.w r1, r1, ip, lsl #21 80004fa: ea23 534c bic.w r3, r3, ip, lsl #21 80004fe: ea50 3501 orrs.w r5, r0, r1, lsl #12 8000502: bf18 it ne 8000504: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000508: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800050c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8000510: d038 beq.n 8000584 <__aeabi_dmul+0xb4> 8000512: fba0 ce02 umull ip, lr, r0, r2 8000516: f04f 0500 mov.w r5, #0 800051a: fbe1 e502 umlal lr, r5, r1, r2 800051e: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 8000522: fbe0 e503 umlal lr, r5, r0, r3 8000526: f04f 0600 mov.w r6, #0 800052a: fbe1 5603 umlal r5, r6, r1, r3 800052e: f09c 0f00 teq ip, #0 8000532: bf18 it ne 8000534: f04e 0e01 orrne.w lr, lr, #1 8000538: f1a4 04ff sub.w r4, r4, #255 ; 0xff 800053c: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000540: f564 7440 sbc.w r4, r4, #768 ; 0x300 8000544: d204 bcs.n 8000550 <__aeabi_dmul+0x80> 8000546: ea5f 0e4e movs.w lr, lr, lsl #1 800054a: 416d adcs r5, r5 800054c: eb46 0606 adc.w r6, r6, r6 8000550: ea42 21c6 orr.w r1, r2, r6, lsl #11 8000554: ea41 5155 orr.w r1, r1, r5, lsr #21 8000558: ea4f 20c5 mov.w r0, r5, lsl #11 800055c: ea40 505e orr.w r0, r0, lr, lsr #21 8000560: ea4f 2ece mov.w lr, lr, lsl #11 8000564: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000568: bf88 it hi 800056a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 800056e: d81e bhi.n 80005ae <__aeabi_dmul+0xde> 8000570: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 8000574: bf08 it eq 8000576: ea5f 0e50 movseq.w lr, r0, lsr #1 800057a: f150 0000 adcs.w r0, r0, #0 800057e: eb41 5104 adc.w r1, r1, r4, lsl #20 8000582: bd70 pop {r4, r5, r6, pc} 8000584: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000588: ea46 0101 orr.w r1, r6, r1 800058c: ea40 0002 orr.w r0, r0, r2 8000590: ea81 0103 eor.w r1, r1, r3 8000594: ebb4 045c subs.w r4, r4, ip, lsr #1 8000598: bfc2 ittt gt 800059a: ebd4 050c rsbsgt r5, r4, ip 800059e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 80005a2: bd70 popgt {r4, r5, r6, pc} 80005a4: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005a8: f04f 0e00 mov.w lr, #0 80005ac: 3c01 subs r4, #1 80005ae: f300 80ab bgt.w 8000708 <__aeabi_dmul+0x238> 80005b2: f114 0f36 cmn.w r4, #54 ; 0x36 80005b6: bfde ittt le 80005b8: 2000 movle r0, #0 80005ba: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 80005be: bd70 pople {r4, r5, r6, pc} 80005c0: f1c4 0400 rsb r4, r4, #0 80005c4: 3c20 subs r4, #32 80005c6: da35 bge.n 8000634 <__aeabi_dmul+0x164> 80005c8: 340c adds r4, #12 80005ca: dc1b bgt.n 8000604 <__aeabi_dmul+0x134> 80005cc: f104 0414 add.w r4, r4, #20 80005d0: f1c4 0520 rsb r5, r4, #32 80005d4: fa00 f305 lsl.w r3, r0, r5 80005d8: fa20 f004 lsr.w r0, r0, r4 80005dc: fa01 f205 lsl.w r2, r1, r5 80005e0: ea40 0002 orr.w r0, r0, r2 80005e4: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80005e8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80005ec: eb10 70d3 adds.w r0, r0, r3, lsr #31 80005f0: fa21 f604 lsr.w r6, r1, r4 80005f4: eb42 0106 adc.w r1, r2, r6 80005f8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80005fc: bf08 it eq 80005fe: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000602: bd70 pop {r4, r5, r6, pc} 8000604: f1c4 040c rsb r4, r4, #12 8000608: f1c4 0520 rsb r5, r4, #32 800060c: fa00 f304 lsl.w r3, r0, r4 8000610: fa20 f005 lsr.w r0, r0, r5 8000614: fa01 f204 lsl.w r2, r1, r4 8000618: ea40 0002 orr.w r0, r0, r2 800061c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000620: eb10 70d3 adds.w r0, r0, r3, lsr #31 8000624: f141 0100 adc.w r1, r1, #0 8000628: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800062c: bf08 it eq 800062e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000632: bd70 pop {r4, r5, r6, pc} 8000634: f1c4 0520 rsb r5, r4, #32 8000638: fa00 f205 lsl.w r2, r0, r5 800063c: ea4e 0e02 orr.w lr, lr, r2 8000640: fa20 f304 lsr.w r3, r0, r4 8000644: fa01 f205 lsl.w r2, r1, r5 8000648: ea43 0302 orr.w r3, r3, r2 800064c: fa21 f004 lsr.w r0, r1, r4 8000650: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000654: fa21 f204 lsr.w r2, r1, r4 8000658: ea20 0002 bic.w r0, r0, r2 800065c: eb00 70d3 add.w r0, r0, r3, lsr #31 8000660: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000664: bf08 it eq 8000666: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800066a: bd70 pop {r4, r5, r6, pc} 800066c: f094 0f00 teq r4, #0 8000670: d10f bne.n 8000692 <__aeabi_dmul+0x1c2> 8000672: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 8000676: 0040 lsls r0, r0, #1 8000678: eb41 0101 adc.w r1, r1, r1 800067c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000680: bf08 it eq 8000682: 3c01 subeq r4, #1 8000684: d0f7 beq.n 8000676 <__aeabi_dmul+0x1a6> 8000686: ea41 0106 orr.w r1, r1, r6 800068a: f095 0f00 teq r5, #0 800068e: bf18 it ne 8000690: 4770 bxne lr 8000692: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 8000696: 0052 lsls r2, r2, #1 8000698: eb43 0303 adc.w r3, r3, r3 800069c: f413 1f80 tst.w r3, #1048576 ; 0x100000 80006a0: bf08 it eq 80006a2: 3d01 subeq r5, #1 80006a4: d0f7 beq.n 8000696 <__aeabi_dmul+0x1c6> 80006a6: ea43 0306 orr.w r3, r3, r6 80006aa: 4770 bx lr 80006ac: ea94 0f0c teq r4, ip 80006b0: ea0c 5513 and.w r5, ip, r3, lsr #20 80006b4: bf18 it ne 80006b6: ea95 0f0c teqne r5, ip 80006ba: d00c beq.n 80006d6 <__aeabi_dmul+0x206> 80006bc: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006c0: bf18 it ne 80006c2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006c6: d1d1 bne.n 800066c <__aeabi_dmul+0x19c> 80006c8: ea81 0103 eor.w r1, r1, r3 80006cc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006d0: f04f 0000 mov.w r0, #0 80006d4: bd70 pop {r4, r5, r6, pc} 80006d6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006da: bf06 itte eq 80006dc: 4610 moveq r0, r2 80006de: 4619 moveq r1, r3 80006e0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006e4: d019 beq.n 800071a <__aeabi_dmul+0x24a> 80006e6: ea94 0f0c teq r4, ip 80006ea: d102 bne.n 80006f2 <__aeabi_dmul+0x222> 80006ec: ea50 3601 orrs.w r6, r0, r1, lsl #12 80006f0: d113 bne.n 800071a <__aeabi_dmul+0x24a> 80006f2: ea95 0f0c teq r5, ip 80006f6: d105 bne.n 8000704 <__aeabi_dmul+0x234> 80006f8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80006fc: bf1c itt ne 80006fe: 4610 movne r0, r2 8000700: 4619 movne r1, r3 8000702: d10a bne.n 800071a <__aeabi_dmul+0x24a> 8000704: ea81 0103 eor.w r1, r1, r3 8000708: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800070c: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000710: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000714: f04f 0000 mov.w r0, #0 8000718: bd70 pop {r4, r5, r6, pc} 800071a: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 800071e: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 8000722: bd70 pop {r4, r5, r6, pc} 08000724 <__aeabi_ddiv>: 8000724: b570 push {r4, r5, r6, lr} 8000726: f04f 0cff mov.w ip, #255 ; 0xff 800072a: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 800072e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8000732: bf1d ittte ne 8000734: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000738: ea94 0f0c teqne r4, ip 800073c: ea95 0f0c teqne r5, ip 8000740: f000 f8a7 bleq 8000892 <__aeabi_ddiv+0x16e> 8000744: eba4 0405 sub.w r4, r4, r5 8000748: ea81 0e03 eor.w lr, r1, r3 800074c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000750: ea4f 3101 mov.w r1, r1, lsl #12 8000754: f000 8088 beq.w 8000868 <__aeabi_ddiv+0x144> 8000758: ea4f 3303 mov.w r3, r3, lsl #12 800075c: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000760: ea45 1313 orr.w r3, r5, r3, lsr #4 8000764: ea43 6312 orr.w r3, r3, r2, lsr #24 8000768: ea4f 2202 mov.w r2, r2, lsl #8 800076c: ea45 1511 orr.w r5, r5, r1, lsr #4 8000770: ea45 6510 orr.w r5, r5, r0, lsr #24 8000774: ea4f 2600 mov.w r6, r0, lsl #8 8000778: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 800077c: 429d cmp r5, r3 800077e: bf08 it eq 8000780: 4296 cmpeq r6, r2 8000782: f144 04fd adc.w r4, r4, #253 ; 0xfd 8000786: f504 7440 add.w r4, r4, #768 ; 0x300 800078a: d202 bcs.n 8000792 <__aeabi_ddiv+0x6e> 800078c: 085b lsrs r3, r3, #1 800078e: ea4f 0232 mov.w r2, r2, rrx 8000792: 1ab6 subs r6, r6, r2 8000794: eb65 0503 sbc.w r5, r5, r3 8000798: 085b lsrs r3, r3, #1 800079a: ea4f 0232 mov.w r2, r2, rrx 800079e: f44f 1080 mov.w r0, #1048576 ; 0x100000 80007a2: f44f 2c00 mov.w ip, #524288 ; 0x80000 80007a6: ebb6 0e02 subs.w lr, r6, r2 80007aa: eb75 0e03 sbcs.w lr, r5, r3 80007ae: bf22 ittt cs 80007b0: 1ab6 subcs r6, r6, r2 80007b2: 4675 movcs r5, lr 80007b4: ea40 000c orrcs.w r0, r0, ip 80007b8: 085b lsrs r3, r3, #1 80007ba: ea4f 0232 mov.w r2, r2, rrx 80007be: ebb6 0e02 subs.w lr, r6, r2 80007c2: eb75 0e03 sbcs.w lr, r5, r3 80007c6: bf22 ittt cs 80007c8: 1ab6 subcs r6, r6, r2 80007ca: 4675 movcs r5, lr 80007cc: ea40 005c orrcs.w r0, r0, ip, lsr #1 80007d0: 085b lsrs r3, r3, #1 80007d2: ea4f 0232 mov.w r2, r2, rrx 80007d6: ebb6 0e02 subs.w lr, r6, r2 80007da: eb75 0e03 sbcs.w lr, r5, r3 80007de: bf22 ittt cs 80007e0: 1ab6 subcs r6, r6, r2 80007e2: 4675 movcs r5, lr 80007e4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80007e8: 085b lsrs r3, r3, #1 80007ea: ea4f 0232 mov.w r2, r2, rrx 80007ee: ebb6 0e02 subs.w lr, r6, r2 80007f2: eb75 0e03 sbcs.w lr, r5, r3 80007f6: bf22 ittt cs 80007f8: 1ab6 subcs r6, r6, r2 80007fa: 4675 movcs r5, lr 80007fc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000800: ea55 0e06 orrs.w lr, r5, r6 8000804: d018 beq.n 8000838 <__aeabi_ddiv+0x114> 8000806: ea4f 1505 mov.w r5, r5, lsl #4 800080a: ea45 7516 orr.w r5, r5, r6, lsr #28 800080e: ea4f 1606 mov.w r6, r6, lsl #4 8000812: ea4f 03c3 mov.w r3, r3, lsl #3 8000816: ea43 7352 orr.w r3, r3, r2, lsr #29 800081a: ea4f 02c2 mov.w r2, r2, lsl #3 800081e: ea5f 1c1c movs.w ip, ip, lsr #4 8000822: d1c0 bne.n 80007a6 <__aeabi_ddiv+0x82> 8000824: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000828: d10b bne.n 8000842 <__aeabi_ddiv+0x11e> 800082a: ea41 0100 orr.w r1, r1, r0 800082e: f04f 0000 mov.w r0, #0 8000832: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 8000836: e7b6 b.n 80007a6 <__aeabi_ddiv+0x82> 8000838: f411 1f80 tst.w r1, #1048576 ; 0x100000 800083c: bf04 itt eq 800083e: 4301 orreq r1, r0 8000840: 2000 moveq r0, #0 8000842: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000846: bf88 it hi 8000848: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 800084c: f63f aeaf bhi.w 80005ae <__aeabi_dmul+0xde> 8000850: ebb5 0c03 subs.w ip, r5, r3 8000854: bf04 itt eq 8000856: ebb6 0c02 subseq.w ip, r6, r2 800085a: ea5f 0c50 movseq.w ip, r0, lsr #1 800085e: f150 0000 adcs.w r0, r0, #0 8000862: eb41 5104 adc.w r1, r1, r4, lsl #20 8000866: bd70 pop {r4, r5, r6, pc} 8000868: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 800086c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000870: eb14 045c adds.w r4, r4, ip, lsr #1 8000874: bfc2 ittt gt 8000876: ebd4 050c rsbsgt r5, r4, ip 800087a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800087e: bd70 popgt {r4, r5, r6, pc} 8000880: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000884: f04f 0e00 mov.w lr, #0 8000888: 3c01 subs r4, #1 800088a: e690 b.n 80005ae <__aeabi_dmul+0xde> 800088c: ea45 0e06 orr.w lr, r5, r6 8000890: e68d b.n 80005ae <__aeabi_dmul+0xde> 8000892: ea0c 5513 and.w r5, ip, r3, lsr #20 8000896: ea94 0f0c teq r4, ip 800089a: bf08 it eq 800089c: ea95 0f0c teqeq r5, ip 80008a0: f43f af3b beq.w 800071a <__aeabi_dmul+0x24a> 80008a4: ea94 0f0c teq r4, ip 80008a8: d10a bne.n 80008c0 <__aeabi_ddiv+0x19c> 80008aa: ea50 3401 orrs.w r4, r0, r1, lsl #12 80008ae: f47f af34 bne.w 800071a <__aeabi_dmul+0x24a> 80008b2: ea95 0f0c teq r5, ip 80008b6: f47f af25 bne.w 8000704 <__aeabi_dmul+0x234> 80008ba: 4610 mov r0, r2 80008bc: 4619 mov r1, r3 80008be: e72c b.n 800071a <__aeabi_dmul+0x24a> 80008c0: ea95 0f0c teq r5, ip 80008c4: d106 bne.n 80008d4 <__aeabi_ddiv+0x1b0> 80008c6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80008ca: f43f aefd beq.w 80006c8 <__aeabi_dmul+0x1f8> 80008ce: 4610 mov r0, r2 80008d0: 4619 mov r1, r3 80008d2: e722 b.n 800071a <__aeabi_dmul+0x24a> 80008d4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80008d8: bf18 it ne 80008da: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80008de: f47f aec5 bne.w 800066c <__aeabi_dmul+0x19c> 80008e2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80008e6: f47f af0d bne.w 8000704 <__aeabi_dmul+0x234> 80008ea: ea52 0543 orrs.w r5, r2, r3, lsl #1 80008ee: f47f aeeb bne.w 80006c8 <__aeabi_dmul+0x1f8> 80008f2: e712 b.n 800071a <__aeabi_dmul+0x24a> 080008f4 <__aeabi_d2iz>: 80008f4: ea4f 0241 mov.w r2, r1, lsl #1 80008f8: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 80008fc: d215 bcs.n 800092a <__aeabi_d2iz+0x36> 80008fe: d511 bpl.n 8000924 <__aeabi_d2iz+0x30> 8000900: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000904: ebb3 5262 subs.w r2, r3, r2, asr #21 8000908: d912 bls.n 8000930 <__aeabi_d2iz+0x3c> 800090a: ea4f 23c1 mov.w r3, r1, lsl #11 800090e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000912: ea43 5350 orr.w r3, r3, r0, lsr #21 8000916: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 800091a: fa23 f002 lsr.w r0, r3, r2 800091e: bf18 it ne 8000920: 4240 negne r0, r0 8000922: 4770 bx lr 8000924: f04f 0000 mov.w r0, #0 8000928: 4770 bx lr 800092a: ea50 3001 orrs.w r0, r0, r1, lsl #12 800092e: d105 bne.n 800093c <__aeabi_d2iz+0x48> 8000930: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000934: bf08 it eq 8000936: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 800093a: 4770 bx lr 800093c: f04f 0000 mov.w r0, #0 8000940: 4770 bx lr 8000942: bf00 nop 08000944 <__aeabi_frsub>: 8000944: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 8000948: e002 b.n 8000950 <__addsf3> 800094a: bf00 nop 0800094c <__aeabi_fsub>: 800094c: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 08000950 <__addsf3>: 8000950: 0042 lsls r2, r0, #1 8000952: bf1f itttt ne 8000954: ea5f 0341 movsne.w r3, r1, lsl #1 8000958: ea92 0f03 teqne r2, r3 800095c: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000960: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000964: d06a beq.n 8000a3c <__addsf3+0xec> 8000966: ea4f 6212 mov.w r2, r2, lsr #24 800096a: ebd2 6313 rsbs r3, r2, r3, lsr #24 800096e: bfc1 itttt gt 8000970: 18d2 addgt r2, r2, r3 8000972: 4041 eorgt r1, r0 8000974: 4048 eorgt r0, r1 8000976: 4041 eorgt r1, r0 8000978: bfb8 it lt 800097a: 425b neglt r3, r3 800097c: 2b19 cmp r3, #25 800097e: bf88 it hi 8000980: 4770 bxhi lr 8000982: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 8000986: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 800098a: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 800098e: bf18 it ne 8000990: 4240 negne r0, r0 8000992: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000996: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 800099a: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 800099e: bf18 it ne 80009a0: 4249 negne r1, r1 80009a2: ea92 0f03 teq r2, r3 80009a6: d03f beq.n 8000a28 <__addsf3+0xd8> 80009a8: f1a2 0201 sub.w r2, r2, #1 80009ac: fa41 fc03 asr.w ip, r1, r3 80009b0: eb10 000c adds.w r0, r0, ip 80009b4: f1c3 0320 rsb r3, r3, #32 80009b8: fa01 f103 lsl.w r1, r1, r3 80009bc: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 80009c0: d502 bpl.n 80009c8 <__addsf3+0x78> 80009c2: 4249 negs r1, r1 80009c4: eb60 0040 sbc.w r0, r0, r0, lsl #1 80009c8: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 80009cc: d313 bcc.n 80009f6 <__addsf3+0xa6> 80009ce: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 80009d2: d306 bcc.n 80009e2 <__addsf3+0x92> 80009d4: 0840 lsrs r0, r0, #1 80009d6: ea4f 0131 mov.w r1, r1, rrx 80009da: f102 0201 add.w r2, r2, #1 80009de: 2afe cmp r2, #254 ; 0xfe 80009e0: d251 bcs.n 8000a86 <__addsf3+0x136> 80009e2: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 80009e6: eb40 50c2 adc.w r0, r0, r2, lsl #23 80009ea: bf08 it eq 80009ec: f020 0001 biceq.w r0, r0, #1 80009f0: ea40 0003 orr.w r0, r0, r3 80009f4: 4770 bx lr 80009f6: 0049 lsls r1, r1, #1 80009f8: eb40 0000 adc.w r0, r0, r0 80009fc: f410 0f00 tst.w r0, #8388608 ; 0x800000 8000a00: f1a2 0201 sub.w r2, r2, #1 8000a04: d1ed bne.n 80009e2 <__addsf3+0x92> 8000a06: fab0 fc80 clz ip, r0 8000a0a: f1ac 0c08 sub.w ip, ip, #8 8000a0e: ebb2 020c subs.w r2, r2, ip 8000a12: fa00 f00c lsl.w r0, r0, ip 8000a16: bfaa itet ge 8000a18: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000a1c: 4252 neglt r2, r2 8000a1e: 4318 orrge r0, r3 8000a20: bfbc itt lt 8000a22: 40d0 lsrlt r0, r2 8000a24: 4318 orrlt r0, r3 8000a26: 4770 bx lr 8000a28: f092 0f00 teq r2, #0 8000a2c: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 8000a30: bf06 itte eq 8000a32: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 8000a36: 3201 addeq r2, #1 8000a38: 3b01 subne r3, #1 8000a3a: e7b5 b.n 80009a8 <__addsf3+0x58> 8000a3c: ea4f 0341 mov.w r3, r1, lsl #1 8000a40: ea7f 6c22 mvns.w ip, r2, asr #24 8000a44: bf18 it ne 8000a46: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000a4a: d021 beq.n 8000a90 <__addsf3+0x140> 8000a4c: ea92 0f03 teq r2, r3 8000a50: d004 beq.n 8000a5c <__addsf3+0x10c> 8000a52: f092 0f00 teq r2, #0 8000a56: bf08 it eq 8000a58: 4608 moveq r0, r1 8000a5a: 4770 bx lr 8000a5c: ea90 0f01 teq r0, r1 8000a60: bf1c itt ne 8000a62: 2000 movne r0, #0 8000a64: 4770 bxne lr 8000a66: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 8000a6a: d104 bne.n 8000a76 <__addsf3+0x126> 8000a6c: 0040 lsls r0, r0, #1 8000a6e: bf28 it cs 8000a70: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 8000a74: 4770 bx lr 8000a76: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 8000a7a: bf3c itt cc 8000a7c: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 8000a80: 4770 bxcc lr 8000a82: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000a86: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 8000a8a: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000a8e: 4770 bx lr 8000a90: ea7f 6222 mvns.w r2, r2, asr #24 8000a94: bf16 itet ne 8000a96: 4608 movne r0, r1 8000a98: ea7f 6323 mvnseq.w r3, r3, asr #24 8000a9c: 4601 movne r1, r0 8000a9e: 0242 lsls r2, r0, #9 8000aa0: bf06 itte eq 8000aa2: ea5f 2341 movseq.w r3, r1, lsl #9 8000aa6: ea90 0f01 teqeq r0, r1 8000aaa: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 8000aae: 4770 bx lr 08000ab0 <__aeabi_ui2f>: 8000ab0: f04f 0300 mov.w r3, #0 8000ab4: e004 b.n 8000ac0 <__aeabi_i2f+0x8> 8000ab6: bf00 nop 08000ab8 <__aeabi_i2f>: 8000ab8: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 8000abc: bf48 it mi 8000abe: 4240 negmi r0, r0 8000ac0: ea5f 0c00 movs.w ip, r0 8000ac4: bf08 it eq 8000ac6: 4770 bxeq lr 8000ac8: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 8000acc: 4601 mov r1, r0 8000ace: f04f 0000 mov.w r0, #0 8000ad2: e01c b.n 8000b0e <__aeabi_l2f+0x2a> 08000ad4 <__aeabi_ul2f>: 8000ad4: ea50 0201 orrs.w r2, r0, r1 8000ad8: bf08 it eq 8000ada: 4770 bxeq lr 8000adc: f04f 0300 mov.w r3, #0 8000ae0: e00a b.n 8000af8 <__aeabi_l2f+0x14> 8000ae2: bf00 nop 08000ae4 <__aeabi_l2f>: 8000ae4: ea50 0201 orrs.w r2, r0, r1 8000ae8: bf08 it eq 8000aea: 4770 bxeq lr 8000aec: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 8000af0: d502 bpl.n 8000af8 <__aeabi_l2f+0x14> 8000af2: 4240 negs r0, r0 8000af4: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000af8: ea5f 0c01 movs.w ip, r1 8000afc: bf02 ittt eq 8000afe: 4684 moveq ip, r0 8000b00: 4601 moveq r1, r0 8000b02: 2000 moveq r0, #0 8000b04: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 8000b08: bf08 it eq 8000b0a: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 8000b0e: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 8000b12: fabc f28c clz r2, ip 8000b16: 3a08 subs r2, #8 8000b18: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000b1c: db10 blt.n 8000b40 <__aeabi_l2f+0x5c> 8000b1e: fa01 fc02 lsl.w ip, r1, r2 8000b22: 4463 add r3, ip 8000b24: fa00 fc02 lsl.w ip, r0, r2 8000b28: f1c2 0220 rsb r2, r2, #32 8000b2c: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000b30: fa20 f202 lsr.w r2, r0, r2 8000b34: eb43 0002 adc.w r0, r3, r2 8000b38: bf08 it eq 8000b3a: f020 0001 biceq.w r0, r0, #1 8000b3e: 4770 bx lr 8000b40: f102 0220 add.w r2, r2, #32 8000b44: fa01 fc02 lsl.w ip, r1, r2 8000b48: f1c2 0220 rsb r2, r2, #32 8000b4c: ea50 004c orrs.w r0, r0, ip, lsl #1 8000b50: fa21 f202 lsr.w r2, r1, r2 8000b54: eb43 0002 adc.w r0, r3, r2 8000b58: bf08 it eq 8000b5a: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000b5e: 4770 bx lr 08000b60 <__aeabi_fmul>: 8000b60: f04f 0cff mov.w ip, #255 ; 0xff 8000b64: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000b68: bf1e ittt ne 8000b6a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000b6e: ea92 0f0c teqne r2, ip 8000b72: ea93 0f0c teqne r3, ip 8000b76: d06f beq.n 8000c58 <__aeabi_fmul+0xf8> 8000b78: 441a add r2, r3 8000b7a: ea80 0c01 eor.w ip, r0, r1 8000b7e: 0240 lsls r0, r0, #9 8000b80: bf18 it ne 8000b82: ea5f 2141 movsne.w r1, r1, lsl #9 8000b86: d01e beq.n 8000bc6 <__aeabi_fmul+0x66> 8000b88: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8000b8c: ea43 1050 orr.w r0, r3, r0, lsr #5 8000b90: ea43 1151 orr.w r1, r3, r1, lsr #5 8000b94: fba0 3101 umull r3, r1, r0, r1 8000b98: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000b9c: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 8000ba0: bf3e ittt cc 8000ba2: 0049 lslcc r1, r1, #1 8000ba4: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8000ba8: 005b lslcc r3, r3, #1 8000baa: ea40 0001 orr.w r0, r0, r1 8000bae: f162 027f sbc.w r2, r2, #127 ; 0x7f 8000bb2: 2afd cmp r2, #253 ; 0xfd 8000bb4: d81d bhi.n 8000bf2 <__aeabi_fmul+0x92> 8000bb6: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8000bba: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000bbe: bf08 it eq 8000bc0: f020 0001 biceq.w r0, r0, #1 8000bc4: 4770 bx lr 8000bc6: f090 0f00 teq r0, #0 8000bca: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000bce: bf08 it eq 8000bd0: 0249 lsleq r1, r1, #9 8000bd2: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000bd6: ea40 2051 orr.w r0, r0, r1, lsr #9 8000bda: 3a7f subs r2, #127 ; 0x7f 8000bdc: bfc2 ittt gt 8000bde: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000be2: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000be6: 4770 bxgt lr 8000be8: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000bec: f04f 0300 mov.w r3, #0 8000bf0: 3a01 subs r2, #1 8000bf2: dc5d bgt.n 8000cb0 <__aeabi_fmul+0x150> 8000bf4: f112 0f19 cmn.w r2, #25 8000bf8: bfdc itt le 8000bfa: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 8000bfe: 4770 bxle lr 8000c00: f1c2 0200 rsb r2, r2, #0 8000c04: 0041 lsls r1, r0, #1 8000c06: fa21 f102 lsr.w r1, r1, r2 8000c0a: f1c2 0220 rsb r2, r2, #32 8000c0e: fa00 fc02 lsl.w ip, r0, r2 8000c12: ea5f 0031 movs.w r0, r1, rrx 8000c16: f140 0000 adc.w r0, r0, #0 8000c1a: ea53 034c orrs.w r3, r3, ip, lsl #1 8000c1e: bf08 it eq 8000c20: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000c24: 4770 bx lr 8000c26: f092 0f00 teq r2, #0 8000c2a: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000c2e: bf02 ittt eq 8000c30: 0040 lsleq r0, r0, #1 8000c32: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000c36: 3a01 subeq r2, #1 8000c38: d0f9 beq.n 8000c2e <__aeabi_fmul+0xce> 8000c3a: ea40 000c orr.w r0, r0, ip 8000c3e: f093 0f00 teq r3, #0 8000c42: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000c46: bf02 ittt eq 8000c48: 0049 lsleq r1, r1, #1 8000c4a: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000c4e: 3b01 subeq r3, #1 8000c50: d0f9 beq.n 8000c46 <__aeabi_fmul+0xe6> 8000c52: ea41 010c orr.w r1, r1, ip 8000c56: e78f b.n 8000b78 <__aeabi_fmul+0x18> 8000c58: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000c5c: ea92 0f0c teq r2, ip 8000c60: bf18 it ne 8000c62: ea93 0f0c teqne r3, ip 8000c66: d00a beq.n 8000c7e <__aeabi_fmul+0x11e> 8000c68: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000c6c: bf18 it ne 8000c6e: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000c72: d1d8 bne.n 8000c26 <__aeabi_fmul+0xc6> 8000c74: ea80 0001 eor.w r0, r0, r1 8000c78: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000c7c: 4770 bx lr 8000c7e: f090 0f00 teq r0, #0 8000c82: bf17 itett ne 8000c84: f090 4f00 teqne r0, #2147483648 ; 0x80000000 8000c88: 4608 moveq r0, r1 8000c8a: f091 0f00 teqne r1, #0 8000c8e: f091 4f00 teqne r1, #2147483648 ; 0x80000000 8000c92: d014 beq.n 8000cbe <__aeabi_fmul+0x15e> 8000c94: ea92 0f0c teq r2, ip 8000c98: d101 bne.n 8000c9e <__aeabi_fmul+0x13e> 8000c9a: 0242 lsls r2, r0, #9 8000c9c: d10f bne.n 8000cbe <__aeabi_fmul+0x15e> 8000c9e: ea93 0f0c teq r3, ip 8000ca2: d103 bne.n 8000cac <__aeabi_fmul+0x14c> 8000ca4: 024b lsls r3, r1, #9 8000ca6: bf18 it ne 8000ca8: 4608 movne r0, r1 8000caa: d108 bne.n 8000cbe <__aeabi_fmul+0x15e> 8000cac: ea80 0001 eor.w r0, r0, r1 8000cb0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000cb4: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000cb8: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000cbc: 4770 bx lr 8000cbe: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000cc2: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 8000cc6: 4770 bx lr 08000cc8 <__aeabi_fdiv>: 8000cc8: f04f 0cff mov.w ip, #255 ; 0xff 8000ccc: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000cd0: bf1e ittt ne 8000cd2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000cd6: ea92 0f0c teqne r2, ip 8000cda: ea93 0f0c teqne r3, ip 8000cde: d069 beq.n 8000db4 <__aeabi_fdiv+0xec> 8000ce0: eba2 0203 sub.w r2, r2, r3 8000ce4: ea80 0c01 eor.w ip, r0, r1 8000ce8: 0249 lsls r1, r1, #9 8000cea: ea4f 2040 mov.w r0, r0, lsl #9 8000cee: d037 beq.n 8000d60 <__aeabi_fdiv+0x98> 8000cf0: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8000cf4: ea43 1111 orr.w r1, r3, r1, lsr #4 8000cf8: ea43 1310 orr.w r3, r3, r0, lsr #4 8000cfc: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000d00: 428b cmp r3, r1 8000d02: bf38 it cc 8000d04: 005b lslcc r3, r3, #1 8000d06: f142 027d adc.w r2, r2, #125 ; 0x7d 8000d0a: f44f 0c00 mov.w ip, #8388608 ; 0x800000 8000d0e: 428b cmp r3, r1 8000d10: bf24 itt cs 8000d12: 1a5b subcs r3, r3, r1 8000d14: ea40 000c orrcs.w r0, r0, ip 8000d18: ebb3 0f51 cmp.w r3, r1, lsr #1 8000d1c: bf24 itt cs 8000d1e: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000d22: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000d26: ebb3 0f91 cmp.w r3, r1, lsr #2 8000d2a: bf24 itt cs 8000d2c: eba3 0391 subcs.w r3, r3, r1, lsr #2 8000d30: ea40 009c orrcs.w r0, r0, ip, lsr #2 8000d34: ebb3 0fd1 cmp.w r3, r1, lsr #3 8000d38: bf24 itt cs 8000d3a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8000d3e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000d42: 011b lsls r3, r3, #4 8000d44: bf18 it ne 8000d46: ea5f 1c1c movsne.w ip, ip, lsr #4 8000d4a: d1e0 bne.n 8000d0e <__aeabi_fdiv+0x46> 8000d4c: 2afd cmp r2, #253 ; 0xfd 8000d4e: f63f af50 bhi.w 8000bf2 <__aeabi_fmul+0x92> 8000d52: 428b cmp r3, r1 8000d54: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000d58: bf08 it eq 8000d5a: f020 0001 biceq.w r0, r0, #1 8000d5e: 4770 bx lr 8000d60: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000d64: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000d68: 327f adds r2, #127 ; 0x7f 8000d6a: bfc2 ittt gt 8000d6c: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000d70: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000d74: 4770 bxgt lr 8000d76: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000d7a: f04f 0300 mov.w r3, #0 8000d7e: 3a01 subs r2, #1 8000d80: e737 b.n 8000bf2 <__aeabi_fmul+0x92> 8000d82: f092 0f00 teq r2, #0 8000d86: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000d8a: bf02 ittt eq 8000d8c: 0040 lsleq r0, r0, #1 8000d8e: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000d92: 3a01 subeq r2, #1 8000d94: d0f9 beq.n 8000d8a <__aeabi_fdiv+0xc2> 8000d96: ea40 000c orr.w r0, r0, ip 8000d9a: f093 0f00 teq r3, #0 8000d9e: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000da2: bf02 ittt eq 8000da4: 0049 lsleq r1, r1, #1 8000da6: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000daa: 3b01 subeq r3, #1 8000dac: d0f9 beq.n 8000da2 <__aeabi_fdiv+0xda> 8000dae: ea41 010c orr.w r1, r1, ip 8000db2: e795 b.n 8000ce0 <__aeabi_fdiv+0x18> 8000db4: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000db8: ea92 0f0c teq r2, ip 8000dbc: d108 bne.n 8000dd0 <__aeabi_fdiv+0x108> 8000dbe: 0242 lsls r2, r0, #9 8000dc0: f47f af7d bne.w 8000cbe <__aeabi_fmul+0x15e> 8000dc4: ea93 0f0c teq r3, ip 8000dc8: f47f af70 bne.w 8000cac <__aeabi_fmul+0x14c> 8000dcc: 4608 mov r0, r1 8000dce: e776 b.n 8000cbe <__aeabi_fmul+0x15e> 8000dd0: ea93 0f0c teq r3, ip 8000dd4: d104 bne.n 8000de0 <__aeabi_fdiv+0x118> 8000dd6: 024b lsls r3, r1, #9 8000dd8: f43f af4c beq.w 8000c74 <__aeabi_fmul+0x114> 8000ddc: 4608 mov r0, r1 8000dde: e76e b.n 8000cbe <__aeabi_fmul+0x15e> 8000de0: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000de4: bf18 it ne 8000de6: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000dea: d1ca bne.n 8000d82 <__aeabi_fdiv+0xba> 8000dec: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 8000df0: f47f af5c bne.w 8000cac <__aeabi_fmul+0x14c> 8000df4: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 8000df8: f47f af3c bne.w 8000c74 <__aeabi_fmul+0x114> 8000dfc: e75f b.n 8000cbe <__aeabi_fmul+0x15e> 8000dfe: bf00 nop 08000e00 <__gesf2>: 8000e00: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 8000e04: e006 b.n 8000e14 <__cmpsf2+0x4> 8000e06: bf00 nop 08000e08 <__lesf2>: 8000e08: f04f 0c01 mov.w ip, #1 8000e0c: e002 b.n 8000e14 <__cmpsf2+0x4> 8000e0e: bf00 nop 08000e10 <__cmpsf2>: 8000e10: f04f 0c01 mov.w ip, #1 8000e14: f84d cd04 str.w ip, [sp, #-4]! 8000e18: ea4f 0240 mov.w r2, r0, lsl #1 8000e1c: ea4f 0341 mov.w r3, r1, lsl #1 8000e20: ea7f 6c22 mvns.w ip, r2, asr #24 8000e24: bf18 it ne 8000e26: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000e2a: d011 beq.n 8000e50 <__cmpsf2+0x40> 8000e2c: b001 add sp, #4 8000e2e: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8000e32: bf18 it ne 8000e34: ea90 0f01 teqne r0, r1 8000e38: bf58 it pl 8000e3a: ebb2 0003 subspl.w r0, r2, r3 8000e3e: bf88 it hi 8000e40: 17c8 asrhi r0, r1, #31 8000e42: bf38 it cc 8000e44: ea6f 70e1 mvncc.w r0, r1, asr #31 8000e48: bf18 it ne 8000e4a: f040 0001 orrne.w r0, r0, #1 8000e4e: 4770 bx lr 8000e50: ea7f 6c22 mvns.w ip, r2, asr #24 8000e54: d102 bne.n 8000e5c <__cmpsf2+0x4c> 8000e56: ea5f 2c40 movs.w ip, r0, lsl #9 8000e5a: d105 bne.n 8000e68 <__cmpsf2+0x58> 8000e5c: ea7f 6c23 mvns.w ip, r3, asr #24 8000e60: d1e4 bne.n 8000e2c <__cmpsf2+0x1c> 8000e62: ea5f 2c41 movs.w ip, r1, lsl #9 8000e66: d0e1 beq.n 8000e2c <__cmpsf2+0x1c> 8000e68: f85d 0b04 ldr.w r0, [sp], #4 8000e6c: 4770 bx lr 8000e6e: bf00 nop 08000e70 <__aeabi_cfrcmple>: 8000e70: 4684 mov ip, r0 8000e72: 4608 mov r0, r1 8000e74: 4661 mov r1, ip 8000e76: e7ff b.n 8000e78 <__aeabi_cfcmpeq> 08000e78 <__aeabi_cfcmpeq>: 8000e78: b50f push {r0, r1, r2, r3, lr} 8000e7a: f7ff ffc9 bl 8000e10 <__cmpsf2> 8000e7e: 2800 cmp r0, #0 8000e80: bf48 it mi 8000e82: f110 0f00 cmnmi.w r0, #0 8000e86: bd0f pop {r0, r1, r2, r3, pc} 08000e88 <__aeabi_fcmpeq>: 8000e88: f84d ed08 str.w lr, [sp, #-8]! 8000e8c: f7ff fff4 bl 8000e78 <__aeabi_cfcmpeq> 8000e90: bf0c ite eq 8000e92: 2001 moveq r0, #1 8000e94: 2000 movne r0, #0 8000e96: f85d fb08 ldr.w pc, [sp], #8 8000e9a: bf00 nop 08000e9c <__aeabi_fcmplt>: 8000e9c: f84d ed08 str.w lr, [sp, #-8]! 8000ea0: f7ff ffea bl 8000e78 <__aeabi_cfcmpeq> 8000ea4: bf34 ite cc 8000ea6: 2001 movcc r0, #1 8000ea8: 2000 movcs r0, #0 8000eaa: f85d fb08 ldr.w pc, [sp], #8 8000eae: bf00 nop 08000eb0 <__aeabi_fcmple>: 8000eb0: f84d ed08 str.w lr, [sp, #-8]! 8000eb4: f7ff ffe0 bl 8000e78 <__aeabi_cfcmpeq> 8000eb8: bf94 ite ls 8000eba: 2001 movls r0, #1 8000ebc: 2000 movhi r0, #0 8000ebe: f85d fb08 ldr.w pc, [sp], #8 8000ec2: bf00 nop 08000ec4 <__aeabi_fcmpge>: 8000ec4: f84d ed08 str.w lr, [sp, #-8]! 8000ec8: f7ff ffd2 bl 8000e70 <__aeabi_cfrcmple> 8000ecc: bf94 ite ls 8000ece: 2001 movls r0, #1 8000ed0: 2000 movhi r0, #0 8000ed2: f85d fb08 ldr.w pc, [sp], #8 8000ed6: bf00 nop 08000ed8 <__aeabi_fcmpgt>: 8000ed8: f84d ed08 str.w lr, [sp, #-8]! 8000edc: f7ff ffc8 bl 8000e70 <__aeabi_cfrcmple> 8000ee0: bf34 ite cc 8000ee2: 2001 movcc r0, #1 8000ee4: 2000 movcs r0, #0 8000ee6: f85d fb08 ldr.w pc, [sp], #8 8000eea: bf00 nop 08000eec <__aeabi_f2uiz>: 8000eec: 0042 lsls r2, r0, #1 8000eee: d20e bcs.n 8000f0e <__aeabi_f2uiz+0x22> 8000ef0: f1b2 4ffe cmp.w r2, #2130706432 ; 0x7f000000 8000ef4: d30b bcc.n 8000f0e <__aeabi_f2uiz+0x22> 8000ef6: f04f 039e mov.w r3, #158 ; 0x9e 8000efa: ebb3 6212 subs.w r2, r3, r2, lsr #24 8000efe: d409 bmi.n 8000f14 <__aeabi_f2uiz+0x28> 8000f00: ea4f 2300 mov.w r3, r0, lsl #8 8000f04: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000f08: fa23 f002 lsr.w r0, r3, r2 8000f0c: 4770 bx lr 8000f0e: f04f 0000 mov.w r0, #0 8000f12: 4770 bx lr 8000f14: f112 0f61 cmn.w r2, #97 ; 0x61 8000f18: d101 bne.n 8000f1e <__aeabi_f2uiz+0x32> 8000f1a: 0242 lsls r2, r0, #9 8000f1c: d102 bne.n 8000f24 <__aeabi_f2uiz+0x38> 8000f1e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8000f22: 4770 bx lr 8000f24: f04f 0000 mov.w r0, #0 8000f28: 4770 bx lr 8000f2a: bf00 nop 08000f2c : /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 8000f2c: 78c3 ldrb r3, [r0, #3] 8000f2e: b95b cbnz r3, 8000f48 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8000f30: 7803 ldrb r3, [r0, #0] 8000f32: 095a lsrs r2, r3, #5 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 8000f34: f003 031f and.w r3, r3, #31 8000f38: 2101 movs r1, #1 8000f3a: fa01 f303 lsl.w r3, r1, r3 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8000f3e: 3220 adds r2, #32 8000f40: 4912 ldr r1, [pc, #72] ; (8000f8c ) 8000f42: f841 3022 str.w r3, [r1, r2, lsl #2] } } 8000f46: 4770 bx lr { 8000f48: b410 push {r4} tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 8000f4a: 4b11 ldr r3, [pc, #68] ; (8000f90 ) 8000f4c: 68da ldr r2, [r3, #12] 8000f4e: 43d2 mvns r2, r2 8000f50: f3c2 2202 ubfx r2, r2, #8, #3 tmppre = (0x4 - tmppriority); 8000f54: f1c2 0404 rsb r4, r2, #4 tmpsub = tmpsub >> tmppriority; 8000f58: 210f movs r1, #15 8000f5a: fa21 f202 lsr.w r2, r1, r2 tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 8000f5e: 7843 ldrb r3, [r0, #1] 8000f60: 40a3 lsls r3, r4 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 8000f62: 7881 ldrb r1, [r0, #2] 8000f64: 400a ands r2, r1 8000f66: 4313 orrs r3, r2 tmppriority = tmppriority << 0x04; 8000f68: 011b lsls r3, r3, #4 NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 8000f6a: 7802 ldrb r2, [r0, #0] 8000f6c: b2db uxtb r3, r3 8000f6e: 4907 ldr r1, [pc, #28] ; (8000f8c ) 8000f70: 440a add r2, r1 8000f72: f882 3300 strb.w r3, [r2, #768] ; 0x300 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8000f76: 7803 ldrb r3, [r0, #0] 8000f78: 0958 lsrs r0, r3, #5 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 8000f7a: f003 031f and.w r3, r3, #31 8000f7e: 2201 movs r2, #1 8000f80: fa02 f303 lsl.w r3, r2, r3 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8000f84: f841 3020 str.w r3, [r1, r0, lsl #2] } 8000f88: bc10 pop {r4} 8000f8a: 4770 bx lr 8000f8c: e000e100 .word 0xe000e100 8000f90: e000ed00 .word 0xe000ed00 08000f94 : * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { 8000f94: b410 push {r4} assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; 8000f96: 6843 ldr r3, [r0, #4] /* Clear DUALMOD and SCAN bits */ tmpreg1 &= CR1_CLEAR_Mask; 8000f98: f423 2370 bic.w r3, r3, #983040 ; 0xf0000 8000f9c: f423 7380 bic.w r3, r3, #256 ; 0x100 /* Configure ADCx: Dual mode and scan conversion mode */ /* Set DUALMOD bits according to ADC_Mode value */ /* Set SCAN bit according to ADC_ScanConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); 8000fa0: 680a ldr r2, [r1, #0] 8000fa2: 790c ldrb r4, [r1, #4] 8000fa4: ea42 2204 orr.w r2, r2, r4, lsl #8 8000fa8: 4313 orrs r3, r2 /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; 8000faa: 6043 str r3, [r0, #4] /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; 8000fac: 6882 ldr r2, [r0, #8] /* Clear CONT, ALIGN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_Mask; 8000fae: 4b0a ldr r3, [pc, #40] ; (8000fd8 ) 8000fb0: 4013 ands r3, r2 /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 8000fb2: 68ca ldr r2, [r1, #12] 8000fb4: 688c ldr r4, [r1, #8] 8000fb6: 4322 orrs r2, r4 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); 8000fb8: 794c ldrb r4, [r1, #5] tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 8000fba: ea42 0244 orr.w r2, r2, r4, lsl #1 8000fbe: 4313 orrs r3, r2 /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; 8000fc0: 6083 str r3, [r0, #8] /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; 8000fc2: 6ac3 ldr r3, [r0, #44] ; 0x2c /* Clear L bits */ tmpreg1 &= SQR1_CLEAR_Mask; 8000fc4: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfChannel value */ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); 8000fc8: 7c0a ldrb r2, [r1, #16] 8000fca: 3a01 subs r2, #1 8000fcc: b2d2 uxtb r2, r2 tmpreg1 |= (uint32_t)tmpreg2 << 20; 8000fce: ea43 5302 orr.w r3, r3, r2, lsl #20 /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; 8000fd2: 62c3 str r3, [r0, #44] ; 0x2c } 8000fd4: bc10 pop {r4} 8000fd6: 4770 bx lr 8000fd8: fff1f7fd .word 0xfff1f7fd 08000fdc : void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8000fdc: b921 cbnz r1, 8000fe8 ADCx->CR2 |= CR2_ADON_Set; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; 8000fde: 6883 ldr r3, [r0, #8] 8000fe0: f023 0301 bic.w r3, r3, #1 8000fe4: 6083 str r3, [r0, #8] 8000fe6: 4770 bx lr ADCx->CR2 |= CR2_ADON_Set; 8000fe8: 6883 ldr r3, [r0, #8] 8000fea: f043 0301 orr.w r3, r3, #1 8000fee: 6083 str r3, [r0, #8] 8000ff0: 4770 bx lr 08000ff2 : void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_DMA_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8000ff2: b921 cbnz r1, 8000ffe ADCx->CR2 |= CR2_DMA_Set; } else { /* Disable the selected ADC DMA request */ ADCx->CR2 &= CR2_DMA_Reset; 8000ff4: 6883 ldr r3, [r0, #8] 8000ff6: f423 7380 bic.w r3, r3, #256 ; 0x100 8000ffa: 6083 str r3, [r0, #8] 8000ffc: 4770 bx lr ADCx->CR2 |= CR2_DMA_Set; 8000ffe: 6883 ldr r3, [r0, #8] 8001000: f443 7380 orr.w r3, r3, #256 ; 0x100 8001004: 6083 str r3, [r0, #8] 8001006: 4770 bx lr 08001008 : void ADC_StartCalibration(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC calibration process */ ADCx->CR2 |= CR2_CAL_Set; 8001008: 6883 ldr r3, [r0, #8] 800100a: f043 0304 orr.w r3, r3, #4 800100e: 6083 str r3, [r0, #8] 8001010: 4770 bx lr 08001012 : { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of CAL bit */ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) 8001012: 6883 ldr r3, [r0, #8] 8001014: f013 0f04 tst.w r3, #4 8001018: d101 bne.n 800101e bitstatus = SET; } else { /* CAL bit is reset: end of calibration */ bitstatus = RESET; 800101a: 2000 movs r0, #0 } /* Return the CAL bit status */ return bitstatus; } 800101c: 4770 bx lr bitstatus = SET; 800101e: 2001 movs r0, #1 8001020: 4770 bx lr 08001022 : void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8001022: b921 cbnz r1, 800102e } else { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; 8001024: 6883 ldr r3, [r0, #8] 8001026: f423 03a0 bic.w r3, r3, #5242880 ; 0x500000 800102a: 6083 str r3, [r0, #8] 800102c: 4770 bx lr ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; 800102e: 6883 ldr r3, [r0, #8] 8001030: f443 03a0 orr.w r3, r3, #5242880 ; 0x500000 8001034: 6083 str r3, [r0, #8] 8001036: 4770 bx lr 08001038 : * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles * @retval None */ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { 8001038: b470 push {r4, r5, r6} assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_REGULAR_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ if (ADC_Channel > ADC_Channel_9) 800103a: 2909 cmp r1, #9 800103c: d91d bls.n 800107a { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; 800103e: 68c5 ldr r5, [r0, #12] /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); 8001040: f1a1 040a sub.w r4, r1, #10 8001044: eb04 0444 add.w r4, r4, r4, lsl #1 8001048: 2607 movs r6, #7 800104a: 40a6 lsls r6, r4 /* Clear the old channel sample time */ tmpreg1 &= ~tmpreg2; 800104c: ea25 0506 bic.w r5, r5, r6 /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); 8001050: fa03 f404 lsl.w r4, r3, r4 /* Set the new channel sample time */ tmpreg1 |= tmpreg2; 8001054: 432c orrs r4, r5 /* Store the new register value */ ADCx->SMPR1 = tmpreg1; 8001056: 60c4 str r4, [r0, #12] tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } /* For Rank 1 to 6 */ if (Rank < 7) 8001058: 2a06 cmp r2, #6 800105a: d91a bls.n 8001092 tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR3 = tmpreg1; } /* For Rank 7 to 12 */ else if (Rank < 13) 800105c: 2a0c cmp r2, #12 800105e: d926 bls.n 80010ae } /* For Rank 13 to 16 */ else { /* Get the old register value */ tmpreg1 = ADCx->SQR1; 8001060: 6ac3 ldr r3, [r0, #44] ; 0x2c /* Calculate the mask to clear */ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); 8001062: 3a0d subs r2, #13 8001064: eb02 0282 add.w r2, r2, r2, lsl #2 8001068: 241f movs r4, #31 800106a: 4094 lsls r4, r2 /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; 800106c: ea23 0304 bic.w r3, r3, r4 /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); 8001070: fa01 f202 lsl.w r2, r1, r2 /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; 8001074: 431a orrs r2, r3 /* Store the new register value */ ADCx->SQR1 = tmpreg1; 8001076: 62c2 str r2, [r0, #44] ; 0x2c } } 8001078: e017 b.n 80010aa tmpreg1 = ADCx->SMPR2; 800107a: 6905 ldr r5, [r0, #16] tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); 800107c: eb01 0641 add.w r6, r1, r1, lsl #1 8001080: 2407 movs r4, #7 8001082: 40b4 lsls r4, r6 tmpreg1 &= ~tmpreg2; 8001084: ea25 0504 bic.w r5, r5, r4 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); 8001088: fa03 f406 lsl.w r4, r3, r6 tmpreg1 |= tmpreg2; 800108c: 432c orrs r4, r5 ADCx->SMPR2 = tmpreg1; 800108e: 6104 str r4, [r0, #16] 8001090: e7e2 b.n 8001058 tmpreg1 = ADCx->SQR3; 8001092: 6b43 ldr r3, [r0, #52] ; 0x34 tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); 8001094: 3a01 subs r2, #1 8001096: eb02 0282 add.w r2, r2, r2, lsl #2 800109a: 241f movs r4, #31 800109c: 4094 lsls r4, r2 tmpreg1 &= ~tmpreg2; 800109e: ea23 0304 bic.w r3, r3, r4 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); 80010a2: fa01 f202 lsl.w r2, r1, r2 tmpreg1 |= tmpreg2; 80010a6: 431a orrs r2, r3 ADCx->SQR3 = tmpreg1; 80010a8: 6342 str r2, [r0, #52] ; 0x34 } 80010aa: bc70 pop {r4, r5, r6} 80010ac: 4770 bx lr tmpreg1 = ADCx->SQR2; 80010ae: 6b03 ldr r3, [r0, #48] ; 0x30 tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); 80010b0: 3a07 subs r2, #7 80010b2: eb02 0282 add.w r2, r2, r2, lsl #2 80010b6: 241f movs r4, #31 80010b8: 4094 lsls r4, r2 tmpreg1 &= ~tmpreg2; 80010ba: ea23 0304 bic.w r3, r3, r4 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); 80010be: fa01 f202 lsl.w r2, r1, r2 tmpreg1 |= tmpreg2; 80010c2: 431a orrs r2, r3 ADCx->SQR2 = tmpreg1; 80010c4: 6302 str r2, [r0, #48] ; 0x30 80010c6: e7f0 b.n 80010aa 080010c8 : { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); /* Disable the selected DMAy Channelx */ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); 80010c8: 6803 ldr r3, [r0, #0] 80010ca: f023 0301 bic.w r3, r3, #1 80010ce: 041b lsls r3, r3, #16 80010d0: 0c1b lsrs r3, r3, #16 80010d2: 6003 str r3, [r0, #0] /* Reset DMAy Channelx control register */ DMAy_Channelx->CCR = 0; 80010d4: 2300 movs r3, #0 80010d6: 6003 str r3, [r0, #0] /* Reset DMAy Channelx remaining bytes register */ DMAy_Channelx->CNDTR = 0; 80010d8: 6043 str r3, [r0, #4] /* Reset DMAy Channelx peripheral address register */ DMAy_Channelx->CPAR = 0; 80010da: 6083 str r3, [r0, #8] /* Reset DMAy Channelx memory address register */ DMAy_Channelx->CMAR = 0; 80010dc: 60c3 str r3, [r0, #12] if (DMAy_Channelx == DMA1_Channel1) 80010de: 4b36 ldr r3, [pc, #216] ; (80011b8 ) 80010e0: 4298 cmp r0, r3 80010e2: d021 beq.n 8001128 { /* Reset interrupt pending bits for DMA1 Channel1 */ DMA1->IFCR |= DMA1_Channel1_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel2) 80010e4: 4b35 ldr r3, [pc, #212] ; (80011bc ) 80010e6: 4298 cmp r0, r3 80010e8: d024 beq.n 8001134 { /* Reset interrupt pending bits for DMA1 Channel2 */ DMA1->IFCR |= DMA1_Channel2_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel3) 80010ea: 4b35 ldr r3, [pc, #212] ; (80011c0 ) 80010ec: 4298 cmp r0, r3 80010ee: d027 beq.n 8001140 { /* Reset interrupt pending bits for DMA1 Channel3 */ DMA1->IFCR |= DMA1_Channel3_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel4) 80010f0: 4b34 ldr r3, [pc, #208] ; (80011c4 ) 80010f2: 4298 cmp r0, r3 80010f4: d02a beq.n 800114c { /* Reset interrupt pending bits for DMA1 Channel4 */ DMA1->IFCR |= DMA1_Channel4_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel5) 80010f6: 4b34 ldr r3, [pc, #208] ; (80011c8 ) 80010f8: 4298 cmp r0, r3 80010fa: d02d beq.n 8001158 { /* Reset interrupt pending bits for DMA1 Channel5 */ DMA1->IFCR |= DMA1_Channel5_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel6) 80010fc: 4b33 ldr r3, [pc, #204] ; (80011cc ) 80010fe: 4298 cmp r0, r3 8001100: d030 beq.n 8001164 { /* Reset interrupt pending bits for DMA1 Channel6 */ DMA1->IFCR |= DMA1_Channel6_IT_Mask; } else if (DMAy_Channelx == DMA1_Channel7) 8001102: 4b33 ldr r3, [pc, #204] ; (80011d0 ) 8001104: 4298 cmp r0, r3 8001106: d033 beq.n 8001170 { /* Reset interrupt pending bits for DMA1 Channel7 */ DMA1->IFCR |= DMA1_Channel7_IT_Mask; } else if (DMAy_Channelx == DMA2_Channel1) 8001108: 4b32 ldr r3, [pc, #200] ; (80011d4 ) 800110a: 4298 cmp r0, r3 800110c: d036 beq.n 800117c { /* Reset interrupt pending bits for DMA2 Channel1 */ DMA2->IFCR |= DMA2_Channel1_IT_Mask; } else if (DMAy_Channelx == DMA2_Channel2) 800110e: 4b32 ldr r3, [pc, #200] ; (80011d8 ) 8001110: 4298 cmp r0, r3 8001112: d039 beq.n 8001188 { /* Reset interrupt pending bits for DMA2 Channel2 */ DMA2->IFCR |= DMA2_Channel2_IT_Mask; } else if (DMAy_Channelx == DMA2_Channel3) 8001114: 4b31 ldr r3, [pc, #196] ; (80011dc ) 8001116: 4298 cmp r0, r3 8001118: d03c beq.n 8001194 { /* Reset interrupt pending bits for DMA2 Channel3 */ DMA2->IFCR |= DMA2_Channel3_IT_Mask; } else if (DMAy_Channelx == DMA2_Channel4) 800111a: 4b31 ldr r3, [pc, #196] ; (80011e0 ) 800111c: 4298 cmp r0, r3 800111e: d03f beq.n 80011a0 /* Reset interrupt pending bits for DMA2 Channel4 */ DMA2->IFCR |= DMA2_Channel4_IT_Mask; } else { if (DMAy_Channelx == DMA2_Channel5) 8001120: 4b30 ldr r3, [pc, #192] ; (80011e4 ) 8001122: 4298 cmp r0, r3 8001124: d042 beq.n 80011ac 8001126: 4770 bx lr DMA1->IFCR |= DMA1_Channel1_IT_Mask; 8001128: 4a2f ldr r2, [pc, #188] ; (80011e8 ) 800112a: 6853 ldr r3, [r2, #4] 800112c: f043 030f orr.w r3, r3, #15 8001130: 6053 str r3, [r2, #4] 8001132: 4770 bx lr DMA1->IFCR |= DMA1_Channel2_IT_Mask; 8001134: 4a2c ldr r2, [pc, #176] ; (80011e8 ) 8001136: 6853 ldr r3, [r2, #4] 8001138: f043 03f0 orr.w r3, r3, #240 ; 0xf0 800113c: 6053 str r3, [r2, #4] 800113e: 4770 bx lr DMA1->IFCR |= DMA1_Channel3_IT_Mask; 8001140: 4a29 ldr r2, [pc, #164] ; (80011e8 ) 8001142: 6853 ldr r3, [r2, #4] 8001144: f443 6370 orr.w r3, r3, #3840 ; 0xf00 8001148: 6053 str r3, [r2, #4] 800114a: 4770 bx lr DMA1->IFCR |= DMA1_Channel4_IT_Mask; 800114c: 4a26 ldr r2, [pc, #152] ; (80011e8 ) 800114e: 6853 ldr r3, [r2, #4] 8001150: f443 4370 orr.w r3, r3, #61440 ; 0xf000 8001154: 6053 str r3, [r2, #4] 8001156: 4770 bx lr DMA1->IFCR |= DMA1_Channel5_IT_Mask; 8001158: 4a23 ldr r2, [pc, #140] ; (80011e8 ) 800115a: 6853 ldr r3, [r2, #4] 800115c: f443 2370 orr.w r3, r3, #983040 ; 0xf0000 8001160: 6053 str r3, [r2, #4] 8001162: 4770 bx lr DMA1->IFCR |= DMA1_Channel6_IT_Mask; 8001164: 4a20 ldr r2, [pc, #128] ; (80011e8 ) 8001166: 6853 ldr r3, [r2, #4] 8001168: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 800116c: 6053 str r3, [r2, #4] 800116e: 4770 bx lr DMA1->IFCR |= DMA1_Channel7_IT_Mask; 8001170: 4a1d ldr r2, [pc, #116] ; (80011e8 ) 8001172: 6853 ldr r3, [r2, #4] 8001174: f043 6370 orr.w r3, r3, #251658240 ; 0xf000000 8001178: 6053 str r3, [r2, #4] 800117a: 4770 bx lr DMA2->IFCR |= DMA2_Channel1_IT_Mask; 800117c: 4a1b ldr r2, [pc, #108] ; (80011ec ) 800117e: 6853 ldr r3, [r2, #4] 8001180: f043 030f orr.w r3, r3, #15 8001184: 6053 str r3, [r2, #4] 8001186: 4770 bx lr DMA2->IFCR |= DMA2_Channel2_IT_Mask; 8001188: 4a18 ldr r2, [pc, #96] ; (80011ec ) 800118a: 6853 ldr r3, [r2, #4] 800118c: f043 03f0 orr.w r3, r3, #240 ; 0xf0 8001190: 6053 str r3, [r2, #4] 8001192: 4770 bx lr DMA2->IFCR |= DMA2_Channel3_IT_Mask; 8001194: 4a15 ldr r2, [pc, #84] ; (80011ec ) 8001196: 6853 ldr r3, [r2, #4] 8001198: f443 6370 orr.w r3, r3, #3840 ; 0xf00 800119c: 6053 str r3, [r2, #4] 800119e: 4770 bx lr DMA2->IFCR |= DMA2_Channel4_IT_Mask; 80011a0: 4a12 ldr r2, [pc, #72] ; (80011ec ) 80011a2: 6853 ldr r3, [r2, #4] 80011a4: f443 4370 orr.w r3, r3, #61440 ; 0xf000 80011a8: 6053 str r3, [r2, #4] 80011aa: 4770 bx lr { /* Reset interrupt pending bits for DMA2 Channel5 */ DMA2->IFCR |= DMA2_Channel5_IT_Mask; 80011ac: 4a0f ldr r2, [pc, #60] ; (80011ec ) 80011ae: 6853 ldr r3, [r2, #4] 80011b0: f443 2370 orr.w r3, r3, #983040 ; 0xf0000 80011b4: 6053 str r3, [r2, #4] } } } 80011b6: e7b6 b.n 8001126 80011b8: 40020008 .word 0x40020008 80011bc: 4002001c .word 0x4002001c 80011c0: 40020030 .word 0x40020030 80011c4: 40020044 .word 0x40020044 80011c8: 40020058 .word 0x40020058 80011cc: 4002006c .word 0x4002006c 80011d0: 40020080 .word 0x40020080 80011d4: 40020408 .word 0x40020408 80011d8: 4002041c .word 0x4002041c 80011dc: 40020430 .word 0x40020430 80011e0: 40020444 .word 0x40020444 80011e4: 40020458 .word 0x40020458 80011e8: 40020000 .word 0x40020000 80011ec: 40020400 .word 0x40020400 080011f0 : * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that * contains the configuration information for the specified DMA Channel. * @retval None */ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) { 80011f0: b410 push {r4} assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ /* Get the DMAy_Channelx CCR value */ tmpreg = DMAy_Channelx->CCR; 80011f2: 6802 ldr r2, [r0, #0] /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmpreg &= CCR_CLEAR_Mask; 80011f4: f422 42ff bic.w r2, r2, #32640 ; 0x7f80 80011f8: f022 0270 bic.w r2, r2, #112 ; 0x70 /* Set MINC bit according to DMA_MemoryInc value */ /* Set PSIZE bits according to DMA_PeripheralDataSize value */ /* Set MSIZE bits according to DMA_MemoryDataSize value */ /* Set PL bits according to DMA_Priority value */ /* Set the MEM2MEM bit according to DMA_M2M value */ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | 80011fc: 688b ldr r3, [r1, #8] 80011fe: 6a0c ldr r4, [r1, #32] 8001200: 4323 orrs r3, r4 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | 8001202: 690c ldr r4, [r1, #16] tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | 8001204: 4323 orrs r3, r4 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | 8001206: 694c ldr r4, [r1, #20] 8001208: 4323 orrs r3, r4 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | 800120a: 698c ldr r4, [r1, #24] DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | 800120c: 4323 orrs r3, r4 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | 800120e: 69cc ldr r4, [r1, #28] 8001210: 4323 orrs r3, r4 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; 8001212: 6a4c ldr r4, [r1, #36] ; 0x24 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | 8001214: 4323 orrs r3, r4 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; 8001216: 6a8c ldr r4, [r1, #40] ; 0x28 8001218: 4323 orrs r3, r4 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | 800121a: 4313 orrs r3, r2 /* Write to DMAy Channelx CCR */ DMAy_Channelx->CCR = tmpreg; 800121c: 6003 str r3, [r0, #0] /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ /* Write to DMAy Channelx CNDTR */ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; 800121e: 68cb ldr r3, [r1, #12] 8001220: 6043 str r3, [r0, #4] /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ /* Write to DMAy Channelx CPAR */ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; 8001222: 680b ldr r3, [r1, #0] 8001224: 6083 str r3, [r0, #8] /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ /* Write to DMAy Channelx CMAR */ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; 8001226: 684b ldr r3, [r1, #4] 8001228: 60c3 str r3, [r0, #12] } 800122a: bc10 pop {r4} 800122c: 4770 bx lr 0800122e : { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 800122e: b931 cbnz r1, 800123e DMAy_Channelx->CCR |= DMA_CCR1_EN; } else { /* Disable the selected DMAy Channelx */ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); 8001230: 6803 ldr r3, [r0, #0] 8001232: f023 0301 bic.w r3, r3, #1 8001236: 041b lsls r3, r3, #16 8001238: 0c1b lsrs r3, r3, #16 800123a: 6003 str r3, [r0, #0] 800123c: 4770 bx lr DMAy_Channelx->CCR |= DMA_CCR1_EN; 800123e: 6803 ldr r3, [r0, #0] 8001240: f043 0301 orr.w r3, r3, #1 8001244: 6003 str r3, [r0, #0] 8001246: 4770 bx lr 08001248 : { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); assert_param(IS_DMA_CONFIG_IT(DMA_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8001248: b922 cbnz r2, 8001254 DMAy_Channelx->CCR |= DMA_IT; } else { /* Disable the selected DMA interrupts */ DMAy_Channelx->CCR &= ~DMA_IT; 800124a: 6803 ldr r3, [r0, #0] 800124c: ea23 0101 bic.w r1, r3, r1 8001250: 6001 str r1, [r0, #0] 8001252: 4770 bx lr DMAy_Channelx->CCR |= DMA_IT; 8001254: 6803 ldr r3, [r0, #0] 8001256: 4319 orrs r1, r3 8001258: 6001 str r1, [r0, #0] 800125a: 4770 bx lr 0800125c : /* Check the parameters */ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); /* Calculate the used DMAy */ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) 800125c: f010 5f80 tst.w r0, #268435456 ; 0x10000000 8001260: d005 beq.n 800126e { /* Get DMA2 ISR register value */ tmpreg = DMA2->ISR ; 8001262: 4b05 ldr r3, [pc, #20] ; (8001278 ) 8001264: 681b ldr r3, [r3, #0] /* Get DMA1 ISR register value */ tmpreg = DMA1->ISR ; } /* Check the status of the specified DMAy flag */ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) 8001266: 4203 tst r3, r0 8001268: d104 bne.n 8001274 bitstatus = SET; } else { /* DMAy_FLAG is reset */ bitstatus = RESET; 800126a: 2000 movs r0, #0 } /* Return the DMAy_FLAG status */ return bitstatus; } 800126c: 4770 bx lr tmpreg = DMA1->ISR ; 800126e: 4b03 ldr r3, [pc, #12] ; (800127c ) 8001270: 681b ldr r3, [r3, #0] 8001272: e7f8 b.n 8001266 bitstatus = SET; 8001274: 2001 movs r0, #1 8001276: 4770 bx lr 8001278: 40020400 .word 0x40020400 800127c: 40020000 .word 0x40020000 08001280 : /* Check the parameters */ assert_param(IS_DMA_GET_IT(DMAy_IT)); /* Calculate the used DMA */ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) 8001280: f010 5f80 tst.w r0, #268435456 ; 0x10000000 8001284: d005 beq.n 8001292 { /* Get DMA2 ISR register value */ tmpreg = DMA2->ISR; 8001286: 4b05 ldr r3, [pc, #20] ; (800129c ) 8001288: 681b ldr r3, [r3, #0] /* Get DMA1 ISR register value */ tmpreg = DMA1->ISR; } /* Check the status of the specified DMAy interrupt */ if ((tmpreg & DMAy_IT) != (uint32_t)RESET) 800128a: 4203 tst r3, r0 800128c: d104 bne.n 8001298 bitstatus = SET; } else { /* DMAy_IT is reset */ bitstatus = RESET; 800128e: 2000 movs r0, #0 } /* Return the DMA_IT status */ return bitstatus; } 8001290: 4770 bx lr tmpreg = DMA1->ISR; 8001292: 4b03 ldr r3, [pc, #12] ; (80012a0 ) 8001294: 681b ldr r3, [r3, #0] 8001296: e7f8 b.n 800128a bitstatus = SET; 8001298: 2001 movs r0, #1 800129a: 4770 bx lr 800129c: 40020400 .word 0x40020400 80012a0: 40020000 .word 0x40020000 080012a4 : { /* Check the parameters */ assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); /* Calculate the used DMAy */ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) 80012a4: f010 5f80 tst.w r0, #268435456 ; 0x10000000 80012a8: d102 bne.n 80012b0 DMA2->IFCR = DMAy_IT; } else { /* Clear the selected DMAy interrupt pending bits */ DMA1->IFCR = DMAy_IT; 80012aa: 4b03 ldr r3, [pc, #12] ; (80012b8 ) 80012ac: 6058 str r0, [r3, #4] 80012ae: 4770 bx lr DMA2->IFCR = DMAy_IT; 80012b0: 4b02 ldr r3, [pc, #8] ; (80012bc ) 80012b2: 6058 str r0, [r3, #4] 80012b4: 4770 bx lr 80012b6: bf00 nop 80012b8: 40020000 .word 0x40020000 80012bc: 40020400 .word 0x40020400 080012c0 : assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); tmp = (uint32_t)EXTI_BASE; if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 80012c0: 7983 ldrb r3, [r0, #6] 80012c2: 2b00 cmp r3, #0 80012c4: d035 beq.n 8001332 { 80012c6: b410 push {r4} { /* Clear EXTI line configuration */ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 80012c8: 4b1f ldr r3, [pc, #124] ; (8001348 ) 80012ca: 681a ldr r2, [r3, #0] 80012cc: 6801 ldr r1, [r0, #0] 80012ce: ea22 0201 bic.w r2, r2, r1 80012d2: 601a str r2, [r3, #0] EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 80012d4: 685a ldr r2, [r3, #4] 80012d6: 6801 ldr r1, [r0, #0] 80012d8: ea22 0201 bic.w r2, r2, r1 80012dc: 605a str r2, [r3, #4] tmp += EXTI_InitStruct->EXTI_Mode; 80012de: 7902 ldrb r2, [r0, #4] 80012e0: f102 4280 add.w r2, r2, #1073741824 ; 0x40000000 80012e4: f502 3282 add.w r2, r2, #66560 ; 0x10400 *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 80012e8: 6811 ldr r1, [r2, #0] 80012ea: 6804 ldr r4, [r0, #0] 80012ec: 4321 orrs r1, r4 80012ee: 6011 str r1, [r2, #0] /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 80012f0: 689a ldr r2, [r3, #8] 80012f2: 6801 ldr r1, [r0, #0] 80012f4: ea22 0201 bic.w r2, r2, r1 80012f8: 609a str r2, [r3, #8] EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 80012fa: 68da ldr r2, [r3, #12] 80012fc: 6801 ldr r1, [r0, #0] 80012fe: ea22 0201 bic.w r2, r2, r1 8001302: 60da str r2, [r3, #12] /* Select the trigger for the selected external interrupts */ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 8001304: 7943 ldrb r3, [r0, #5] 8001306: 2b10 cmp r3, #16 8001308: d009 beq.n 800131e EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; } else { tmp = (uint32_t)EXTI_BASE; tmp += EXTI_InitStruct->EXTI_Trigger; 800130a: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 800130e: f503 3382 add.w r3, r3, #66560 ; 0x10400 *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 8001312: 681a ldr r2, [r3, #0] 8001314: 6801 ldr r1, [r0, #0] 8001316: 430a orrs r2, r1 8001318: 601a str r2, [r3, #0] tmp += EXTI_InitStruct->EXTI_Mode; /* Disable the selected external lines */ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; } } 800131a: bc10 pop {r4} 800131c: 4770 bx lr EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 800131e: 4b0a ldr r3, [pc, #40] ; (8001348 ) 8001320: 689a ldr r2, [r3, #8] 8001322: 6801 ldr r1, [r0, #0] 8001324: 430a orrs r2, r1 8001326: 609a str r2, [r3, #8] EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 8001328: 68da ldr r2, [r3, #12] 800132a: 6801 ldr r1, [r0, #0] 800132c: 430a orrs r2, r1 800132e: 60da str r2, [r3, #12] 8001330: e7f3 b.n 800131a tmp += EXTI_InitStruct->EXTI_Mode; 8001332: 7903 ldrb r3, [r0, #4] 8001334: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 8001338: f503 3382 add.w r3, r3, #66560 ; 0x10400 *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 800133c: 681a ldr r2, [r3, #0] 800133e: 6801 ldr r1, [r0, #0] 8001340: ea22 0201 bic.w r2, r2, r1 8001344: 601a str r2, [r3, #0] } 8001346: 4770 bx lr 8001348: 40010400 .word 0x40010400 0800134c : * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that * contains the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { 800134c: b4f0 push {r4, r5, r6, r7} assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /*---------------------------- GPIO Mode Configuration -----------------------*/ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); 800134e: 78cb ldrb r3, [r1, #3] 8001350: f003 020f and.w r2, r3, #15 8001354: 4615 mov r5, r2 if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) 8001356: f013 0f10 tst.w r3, #16 800135a: d001 beq.n 8001360 { /* Check the parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Output mode */ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; 800135c: 788d ldrb r5, [r1, #2] 800135e: 4315 orrs r5, r2 } /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) 8001360: 780b ldrb r3, [r1, #0] 8001362: b1e3 cbz r3, 800139e { tmpreg = GPIOx->CRL; 8001364: 6806 ldr r6, [r0, #0] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 8001366: 2300 movs r3, #0 8001368: e001 b.n 800136e /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) { GPIOx->BRR = (((uint32_t)0x01) << pinpos); 800136a: 6142 str r2, [r0, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 800136c: 3301 adds r3, #1 800136e: 2b07 cmp r3, #7 8001370: d814 bhi.n 800139c pos = ((uint32_t)0x01) << pinpos; 8001372: 2201 movs r2, #1 8001374: 409a lsls r2, r3 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 8001376: 880c ldrh r4, [r1, #0] if (currentpin == pos) 8001378: ea32 0404 bics.w r4, r2, r4 800137c: d1f6 bne.n 800136c pos = pinpos << 2; 800137e: 009c lsls r4, r3, #2 pinmask = ((uint32_t)0x0F) << pos; 8001380: 270f movs r7, #15 8001382: 40a7 lsls r7, r4 tmpreg &= ~pinmask; 8001384: ea26 0607 bic.w r6, r6, r7 tmpreg |= (currentmode << pos); 8001388: fa05 f404 lsl.w r4, r5, r4 800138c: 4326 orrs r6, r4 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 800138e: 78cc ldrb r4, [r1, #3] 8001390: 2c28 cmp r4, #40 ; 0x28 8001392: d0ea beq.n 800136a } else { /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 8001394: 2c48 cmp r4, #72 ; 0x48 8001396: d1e9 bne.n 800136c { GPIOx->BSRR = (((uint32_t)0x01) << pinpos); 8001398: 6102 str r2, [r0, #16] 800139a: e7e7 b.n 800136c } } } } GPIOx->CRL = tmpreg; 800139c: 6006 str r6, [r0, #0] } /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) 800139e: 880b ldrh r3, [r1, #0] 80013a0: 2bff cmp r3, #255 ; 0xff 80013a2: d920 bls.n 80013e6 { tmpreg = GPIOx->CRH; 80013a4: 6846 ldr r6, [r0, #4] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 80013a6: 2300 movs r3, #0 80013a8: e002 b.n 80013b0 /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) { GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); 80013aa: 6142 str r2, [r0, #20] 80013ac: e015 b.n 80013da for (pinpos = 0x00; pinpos < 0x08; pinpos++) 80013ae: 3301 adds r3, #1 80013b0: 2b07 cmp r3, #7 80013b2: d817 bhi.n 80013e4 pos = (((uint32_t)0x01) << (pinpos + 0x08)); 80013b4: f103 0408 add.w r4, r3, #8 80013b8: 2201 movs r2, #1 80013ba: 40a2 lsls r2, r4 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); 80013bc: 880c ldrh r4, [r1, #0] if (currentpin == pos) 80013be: ea32 0404 bics.w r4, r2, r4 80013c2: d1f4 bne.n 80013ae pos = pinpos << 2; 80013c4: 009c lsls r4, r3, #2 pinmask = ((uint32_t)0x0F) << pos; 80013c6: 270f movs r7, #15 80013c8: 40a7 lsls r7, r4 tmpreg &= ~pinmask; 80013ca: ea26 0607 bic.w r6, r6, r7 tmpreg |= (currentmode << pos); 80013ce: fa05 f404 lsl.w r4, r5, r4 80013d2: 4326 orrs r6, r4 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 80013d4: 78cc ldrb r4, [r1, #3] 80013d6: 2c28 cmp r4, #40 ; 0x28 80013d8: d0e7 beq.n 80013aa } /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 80013da: 78cc ldrb r4, [r1, #3] 80013dc: 2c48 cmp r4, #72 ; 0x48 80013de: d1e6 bne.n 80013ae { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); 80013e0: 6102 str r2, [r0, #16] 80013e2: e7e4 b.n 80013ae } } } GPIOx->CRH = tmpreg; 80013e4: 6046 str r6, [r0, #4] } } 80013e6: bcf0 pop {r4, r5, r6, r7} 80013e8: 4770 bx lr 080013ea : { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRR = GPIO_Pin; 80013ea: 6101 str r1, [r0, #16] 80013ec: 4770 bx lr 080013ee : { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BRR = GPIO_Pin; 80013ee: 6141 str r1, [r0, #20] 80013f0: 4770 bx lr ... 080013f4 : * @param NewState: new state of the port pin remapping. * This parameter can be: ENABLE or DISABLE. * @retval None */ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) { 80013f4: b430 push {r4, r5} /* Check the parameters */ assert_param(IS_GPIO_REMAP(GPIO_Remap)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if((GPIO_Remap & 0x80000000) == 0x80000000) 80013f6: 2800 cmp r0, #0 80013f8: db1d blt.n 8001436 { tmpreg = AFIO->MAPR2; } else { tmpreg = AFIO->MAPR; 80013fa: 4b1a ldr r3, [pc, #104] ; (8001464 ) 80013fc: 685b ldr r3, [r3, #4] } tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; 80013fe: f3c0 4503 ubfx r5, r0, #16, #4 tmp = GPIO_Remap & LSB_MASK; 8001402: b282 uxth r2, r0 if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) 8001404: f400 1440 and.w r4, r0, #3145728 ; 0x300000 8001408: f5b4 1f40 cmp.w r4, #3145728 ; 0x300000 800140c: d016 beq.n 800143c { tmpreg &= DBGAFR_SWJCFG_MASK; AFIO->MAPR &= DBGAFR_SWJCFG_MASK; } else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) 800140e: f410 1f80 tst.w r0, #1048576 ; 0x100000 8001412: d01b beq.n 800144c { tmp1 = ((uint32_t)0x03) << tmpmask; 8001414: 2403 movs r4, #3 8001416: 40ac lsls r4, r5 tmpreg &= ~tmp1; 8001418: ea23 0304 bic.w r3, r3, r4 tmpreg |= ~DBGAFR_SWJCFG_MASK; 800141c: f043 6370 orr.w r3, r3, #251658240 ; 0xf000000 { tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); tmpreg |= ~DBGAFR_SWJCFG_MASK; } if (NewState != DISABLE) 8001420: b119 cbz r1, 800142a { tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); 8001422: 0d41 lsrs r1, r0, #21 8001424: 0109 lsls r1, r1, #4 8001426: 408a lsls r2, r1 8001428: 4313 orrs r3, r2 } if((GPIO_Remap & 0x80000000) == 0x80000000) 800142a: 2800 cmp r0, #0 800142c: db17 blt.n 800145e { AFIO->MAPR2 = tmpreg; } else { AFIO->MAPR = tmpreg; 800142e: 4a0d ldr r2, [pc, #52] ; (8001464 ) 8001430: 6053 str r3, [r2, #4] } } 8001432: bc30 pop {r4, r5} 8001434: 4770 bx lr tmpreg = AFIO->MAPR2; 8001436: 4b0b ldr r3, [pc, #44] ; (8001464 ) 8001438: 69db ldr r3, [r3, #28] 800143a: e7e0 b.n 80013fe tmpreg &= DBGAFR_SWJCFG_MASK; 800143c: f023 6370 bic.w r3, r3, #251658240 ; 0xf000000 AFIO->MAPR &= DBGAFR_SWJCFG_MASK; 8001440: 4d08 ldr r5, [pc, #32] ; (8001464 ) 8001442: 686c ldr r4, [r5, #4] 8001444: f024 6470 bic.w r4, r4, #251658240 ; 0xf000000 8001448: 606c str r4, [r5, #4] 800144a: e7e9 b.n 8001420 tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); 800144c: 0d44 lsrs r4, r0, #21 800144e: 0124 lsls r4, r4, #4 8001450: fa02 f404 lsl.w r4, r2, r4 8001454: ea23 0304 bic.w r3, r3, r4 tmpreg |= ~DBGAFR_SWJCFG_MASK; 8001458: f043 6370 orr.w r3, r3, #251658240 ; 0xf000000 800145c: e7e0 b.n 8001420 AFIO->MAPR2 = tmpreg; 800145e: 4a01 ldr r2, [pc, #4] ; (8001464 ) 8001460: 61d3 str r3, [r2, #28] 8001462: e7e6 b.n 8001432 8001464: 40010000 .word 0x40010000 08001468 : * @param GPIO_PinSource: specifies the EXTI line to be configured. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @retval None */ void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) { 8001468: b430 push {r4, r5} uint32_t tmp = 0x00; /* Check the parameters */ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); 800146a: f001 0303 and.w r3, r1, #3 800146e: 009b lsls r3, r3, #2 8001470: 240f movs r4, #15 8001472: fa04 f503 lsl.w r5, r4, r3 AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; 8001476: 0889 lsrs r1, r1, #2 8001478: 4a07 ldr r2, [pc, #28] ; (8001498 ) 800147a: 3102 adds r1, #2 800147c: f852 4021 ldr.w r4, [r2, r1, lsl #2] 8001480: ea24 0405 bic.w r4, r4, r5 8001484: f842 4021 str.w r4, [r2, r1, lsl #2] AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); 8001488: f852 4021 ldr.w r4, [r2, r1, lsl #2] 800148c: 4098 lsls r0, r3 800148e: 4320 orrs r0, r4 8001490: f842 0021 str.w r0, [r2, r1, lsl #2] } 8001494: bc30 pop {r4, r5} 8001496: 4770 bx lr 8001498: 40010000 .word 0x40010000 0800149c : void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); tmpreg = RCC->CFGR; 800149c: 4a03 ldr r2, [pc, #12] ; (80014ac ) 800149e: 6853 ldr r3, [r2, #4] /* Clear ADCPRE[1:0] bits */ tmpreg &= CFGR_ADCPRE_Reset_Mask; 80014a0: f423 4340 bic.w r3, r3, #49152 ; 0xc000 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ tmpreg |= RCC_PCLK2; 80014a4: 4318 orrs r0, r3 /* Store the new value */ RCC->CFGR = tmpreg; 80014a6: 6050 str r0, [r2, #4] 80014a8: 4770 bx lr 80014aa: bf00 nop 80014ac: 40021000 .word 0x40021000 080014b0 : * @note The result of this function could be not correct when using * fractional value for HSE crystal. * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { 80014b0: b410 push {r4} #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & CFGR_SWS_Mask; 80014b2: 4b29 ldr r3, [pc, #164] ; (8001558 ) 80014b4: 685b ldr r3, [r3, #4] 80014b6: f003 030c and.w r3, r3, #12 switch (tmp) 80014ba: 2b04 cmp r3, #4 80014bc: d02b beq.n 8001516 80014be: 2b08 cmp r3, #8 80014c0: d02c beq.n 800151c 80014c2: b113 cbz r3, 80014ca } #endif /* STM32F10X_CL */ break; default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 80014c4: 4b25 ldr r3, [pc, #148] ; (800155c ) 80014c6: 6003 str r3, [r0, #0] break; 80014c8: e001 b.n 80014ce RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 80014ca: 4b24 ldr r3, [pc, #144] ; (800155c ) 80014cc: 6003 str r3, [r0, #0] } /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ /* Get HCLK prescaler */ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; 80014ce: 4922 ldr r1, [pc, #136] ; (8001558 ) 80014d0: 684b ldr r3, [r1, #4] tmp = tmp >> 4; 80014d2: f3c3 1303 ubfx r3, r3, #4, #4 presc = APBAHBPrescTable[tmp]; 80014d6: 4c22 ldr r4, [pc, #136] ; (8001560 ) 80014d8: 5ce3 ldrb r3, [r4, r3] 80014da: b2da uxtb r2, r3 /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; 80014dc: 6803 ldr r3, [r0, #0] 80014de: 40d3 lsrs r3, r2 80014e0: 6043 str r3, [r0, #4] /* Get PCLK1 prescaler */ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; 80014e2: 684a ldr r2, [r1, #4] tmp = tmp >> 8; 80014e4: f3c2 2202 ubfx r2, r2, #8, #3 presc = APBAHBPrescTable[tmp]; 80014e8: 5ca2 ldrb r2, [r4, r2] 80014ea: b2d2 uxtb r2, r2 /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 80014ec: fa23 f202 lsr.w r2, r3, r2 80014f0: 6082 str r2, [r0, #8] /* Get PCLK2 prescaler */ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; 80014f2: 684a ldr r2, [r1, #4] tmp = tmp >> 11; 80014f4: f3c2 22c2 ubfx r2, r2, #11, #3 presc = APBAHBPrescTable[tmp]; 80014f8: 5ca2 ldrb r2, [r4, r2] 80014fa: b2d2 uxtb r2, r2 /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 80014fc: 40d3 lsrs r3, r2 80014fe: 60c3 str r3, [r0, #12] /* Get ADCCLK prescaler */ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; 8001500: 684a ldr r2, [r1, #4] tmp = tmp >> 14; 8001502: f3c2 3281 ubfx r2, r2, #14, #2 presc = ADCPrescTable[tmp]; 8001506: 4917 ldr r1, [pc, #92] ; (8001564 ) 8001508: 5c8a ldrb r2, [r1, r2] 800150a: b2d2 uxtb r2, r2 /* ADCCLK clock frequency */ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; 800150c: fbb3 f3f2 udiv r3, r3, r2 8001510: 6103 str r3, [r0, #16] } 8001512: bc10 pop {r4} 8001514: 4770 bx lr RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; 8001516: 4b11 ldr r3, [pc, #68] ; (800155c ) 8001518: 6003 str r3, [r0, #0] break; 800151a: e7d8 b.n 80014ce pllmull = RCC->CFGR & CFGR_PLLMull_Mask; 800151c: 4a0e ldr r2, [pc, #56] ; (8001558 ) 800151e: 6853 ldr r3, [r2, #4] pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; 8001520: 6852 ldr r2, [r2, #4] pllmull = ( pllmull >> 18) + 2; 8001522: f3c3 4383 ubfx r3, r3, #18, #4 8001526: 3302 adds r3, #2 if (pllsource == 0x00) 8001528: f412 3f80 tst.w r2, #65536 ; 0x10000 800152c: d009 beq.n 8001542 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) 800152e: 4a0a ldr r2, [pc, #40] ; (8001558 ) 8001530: 6852 ldr r2, [r2, #4] 8001532: f412 3f00 tst.w r2, #131072 ; 0x20000 8001536: d009 beq.n 800154c RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; 8001538: 4a0b ldr r2, [pc, #44] ; (8001568 ) 800153a: fb02 f303 mul.w r3, r2, r3 800153e: 6003 str r3, [r0, #0] 8001540: e7c5 b.n 80014ce RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; 8001542: 4a09 ldr r2, [pc, #36] ; (8001568 ) 8001544: fb02 f303 mul.w r3, r2, r3 8001548: 6003 str r3, [r0, #0] 800154a: e7c0 b.n 80014ce RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; 800154c: 4a03 ldr r2, [pc, #12] ; (800155c ) 800154e: fb02 f303 mul.w r3, r2, r3 8001552: 6003 str r3, [r0, #0] 8001554: e7bb b.n 80014ce 8001556: bf00 nop 8001558: 40021000 .word 0x40021000 800155c: 007a1200 .word 0x007a1200 8001560: 20000004 .word 0x20000004 8001564: 20000000 .word 0x20000000 8001568: 003d0900 .word 0x003d0900 0800156c : { /* Check the parameters */ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 800156c: b929 cbnz r1, 800157a { RCC->AHBENR |= RCC_AHBPeriph; } else { RCC->AHBENR &= ~RCC_AHBPeriph; 800156e: 4a05 ldr r2, [pc, #20] ; (8001584 ) 8001570: 6953 ldr r3, [r2, #20] 8001572: ea23 0000 bic.w r0, r3, r0 8001576: 6150 str r0, [r2, #20] 8001578: 4770 bx lr RCC->AHBENR |= RCC_AHBPeriph; 800157a: 4a02 ldr r2, [pc, #8] ; (8001584 ) 800157c: 6953 ldr r3, [r2, #20] 800157e: 4318 orrs r0, r3 8001580: 6150 str r0, [r2, #20] 8001582: 4770 bx lr 8001584: 40021000 .word 0x40021000 08001588 : void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8001588: b929 cbnz r1, 8001596 { RCC->APB2ENR |= RCC_APB2Periph; } else { RCC->APB2ENR &= ~RCC_APB2Periph; 800158a: 4a05 ldr r2, [pc, #20] ; (80015a0 ) 800158c: 6993 ldr r3, [r2, #24] 800158e: ea23 0000 bic.w r0, r3, r0 8001592: 6190 str r0, [r2, #24] 8001594: 4770 bx lr RCC->APB2ENR |= RCC_APB2Periph; 8001596: 4a02 ldr r2, [pc, #8] ; (80015a0 ) 8001598: 6993 ldr r3, [r2, #24] 800159a: 4318 orrs r0, r3 800159c: 6190 str r0, [r2, #24] 800159e: 4770 bx lr 80015a0: 40021000 .word 0x40021000 080015a4 : void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80015a4: b929 cbnz r1, 80015b2 { RCC->APB1ENR |= RCC_APB1Periph; } else { RCC->APB1ENR &= ~RCC_APB1Periph; 80015a6: 4a05 ldr r2, [pc, #20] ; (80015bc ) 80015a8: 69d3 ldr r3, [r2, #28] 80015aa: ea23 0000 bic.w r0, r3, r0 80015ae: 61d0 str r0, [r2, #28] 80015b0: 4770 bx lr RCC->APB1ENR |= RCC_APB1Periph; 80015b2: 4a02 ldr r2, [pc, #8] ; (80015bc ) 80015b4: 69d3 ldr r3, [r2, #28] 80015b6: 4318 orrs r0, r3 80015b8: 61d0 str r0, [r2, #28] 80015ba: 4770 bx lr 80015bc: 40021000 .word 0x40021000 080015c0 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 80015c0: b430 push {r4, r5} uint16_t tmpccmr1 = 0, tmpccer = 0; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); 80015c2: 8c04 ldrh r4, [r0, #32] 80015c4: b2a4 uxth r4, r4 80015c6: f024 0401 bic.w r4, r4, #1 80015ca: b2a4 uxth r4, r4 80015cc: 8404 strh r4, [r0, #32] tmpccmr1 = TIMx->CCMR1; 80015ce: 8b04 ldrh r4, [r0, #24] 80015d0: b2a4 uxth r4, r4 tmpccer = TIMx->CCER; 80015d2: 8c05 ldrh r5, [r0, #32] 80015d4: b2ad uxth r5, r5 /* Select the Input and set the filter */ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); 80015d6: f024 04f3 bic.w r4, r4, #243 ; 0xf3 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 80015da: 011b lsls r3, r3, #4 80015dc: b29b uxth r3, r3 80015de: 431a orrs r2, r3 80015e0: 4314 orrs r4, r2 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 80015e2: 4a12 ldr r2, [pc, #72] ; (800162c ) 80015e4: 4290 cmp r0, r2 80015e6: d01a beq.n 800161e 80015e8: 4b11 ldr r3, [pc, #68] ; (8001630 ) 80015ea: 4298 cmp r0, r3 80015ec: d017 beq.n 800161e 80015ee: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 80015f2: d014 beq.n 800161e 80015f4: f5a3 3398 sub.w r3, r3, #77824 ; 0x13000 80015f8: 4298 cmp r0, r3 80015fa: d010 beq.n 800161e 80015fc: f503 6380 add.w r3, r3, #1024 ; 0x400 8001600: 4298 cmp r0, r3 8001602: d00c beq.n 800161e (TIMx == TIM4) ||(TIMx == TIM5)) 8001604: f503 6380 add.w r3, r3, #1024 ; 0x400 8001608: 4298 cmp r0, r3 800160a: d008 beq.n 800161e tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); } else { /* Select the Polarity and set the CC1E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); 800160c: f025 030a bic.w r3, r5, #10 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 8001610: 4319 orrs r1, r3 8001612: f041 0101 orr.w r1, r1, #1 } /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8001616: 8304 strh r4, [r0, #24] TIMx->CCER = tmpccer; 8001618: 8401 strh r1, [r0, #32] } 800161a: bc30 pop {r4, r5} 800161c: 4770 bx lr tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); 800161e: f025 0302 bic.w r3, r5, #2 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 8001622: 4319 orrs r1, r3 8001624: f041 0101 orr.w r1, r1, #1 8001628: e7f5 b.n 8001616 800162a: bf00 nop 800162c: 40012c00 .word 0x40012c00 8001630: 40013400 .word 0x40013400 08001634 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 8001634: b470 push {r4, r5, r6} uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); 8001636: 8c05 ldrh r5, [r0, #32] 8001638: b2ad uxth r5, r5 800163a: f025 0510 bic.w r5, r5, #16 800163e: b2ad uxth r5, r5 8001640: 8405 strh r5, [r0, #32] tmpccmr1 = TIMx->CCMR1; 8001642: 8b05 ldrh r5, [r0, #24] tmpccer = TIMx->CCER; 8001644: 8c04 ldrh r4, [r0, #32] 8001646: b2a4 uxth r4, r4 tmp = (uint16_t)(TIM_ICPolarity << 4); 8001648: 010e lsls r6, r1, #4 800164a: b2b6 uxth r6, r6 /* Select the Input and set the filter */ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); 800164c: f425 7540 bic.w r5, r5, #768 ; 0x300 8001650: 052d lsls r5, r5, #20 8001652: 0d2d lsrs r5, r5, #20 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); 8001654: 031b lsls r3, r3, #12 8001656: b29b uxth r3, r3 8001658: 431d orrs r5, r3 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 800165a: 0212 lsls r2, r2, #8 800165c: b292 uxth r2, r2 800165e: 4315 orrs r5, r2 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 8001660: 4b12 ldr r3, [pc, #72] ; (80016ac ) 8001662: 4298 cmp r0, r3 8001664: d01b beq.n 800169e 8001666: f503 6300 add.w r3, r3, #2048 ; 0x800 800166a: 4298 cmp r0, r3 800166c: d017 beq.n 800169e 800166e: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 8001672: d014 beq.n 800169e 8001674: f5a3 3398 sub.w r3, r3, #77824 ; 0x13000 8001678: 4298 cmp r0, r3 800167a: d010 beq.n 800169e 800167c: f503 6380 add.w r3, r3, #1024 ; 0x400 8001680: 4298 cmp r0, r3 8001682: d00c beq.n 800169e (TIMx == TIM4) ||(TIMx == TIM5)) 8001684: f503 6380 add.w r3, r3, #1024 ; 0x400 8001688: 4298 cmp r0, r3 800168a: d008 beq.n 800169e tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); } else { /* Select the Polarity and set the CC2E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); 800168c: f024 04a0 bic.w r4, r4, #160 ; 0xa0 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); 8001690: 430c orrs r4, r1 8001692: f044 0410 orr.w r4, r4, #16 } /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8001696: 8305 strh r5, [r0, #24] TIMx->CCER = tmpccer; 8001698: 8404 strh r4, [r0, #32] } 800169a: bc70 pop {r4, r5, r6} 800169c: 4770 bx lr tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); 800169e: f024 0420 bic.w r4, r4, #32 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); 80016a2: 4334 orrs r4, r6 80016a4: f044 0410 orr.w r4, r4, #16 80016a8: e7f5 b.n 8001696 80016aa: bf00 nop 80016ac: 40012c00 .word 0x40012c00 080016b0 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 80016b0: b470 push {r4, r5, r6} uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); 80016b2: 8c04 ldrh r4, [r0, #32] 80016b4: b2a4 uxth r4, r4 80016b6: f424 7480 bic.w r4, r4, #256 ; 0x100 80016ba: b2a4 uxth r4, r4 80016bc: 8404 strh r4, [r0, #32] tmpccmr2 = TIMx->CCMR2; 80016be: 8b84 ldrh r4, [r0, #28] 80016c0: b2a4 uxth r4, r4 tmpccer = TIMx->CCER; 80016c2: 8c05 ldrh r5, [r0, #32] 80016c4: b2ae uxth r6, r5 tmp = (uint16_t)(TIM_ICPolarity << 8); 80016c6: 020d lsls r5, r1, #8 80016c8: b2ad uxth r5, r5 /* Select the Input and set the filter */ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); 80016ca: f024 04f3 bic.w r4, r4, #243 ; 0xf3 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 80016ce: 011b lsls r3, r3, #4 80016d0: b29b uxth r3, r3 80016d2: 4313 orrs r3, r2 80016d4: 431c orrs r4, r3 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 80016d6: 4b12 ldr r3, [pc, #72] ; (8001720 ) 80016d8: 4298 cmp r0, r3 80016da: d01b beq.n 8001714 80016dc: f503 6300 add.w r3, r3, #2048 ; 0x800 80016e0: 4298 cmp r0, r3 80016e2: d017 beq.n 8001714 80016e4: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 80016e8: d014 beq.n 8001714 80016ea: f5a3 3398 sub.w r3, r3, #77824 ; 0x13000 80016ee: 4298 cmp r0, r3 80016f0: d010 beq.n 8001714 80016f2: f503 6380 add.w r3, r3, #1024 ; 0x400 80016f6: 4298 cmp r0, r3 80016f8: d00c beq.n 8001714 (TIMx == TIM4) ||(TIMx == TIM5)) 80016fa: f503 6380 add.w r3, r3, #1024 ; 0x400 80016fe: 4298 cmp r0, r3 8001700: d008 beq.n 8001714 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); } else { /* Select the Polarity and set the CC3E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8001702: f426 6320 bic.w r3, r6, #2560 ; 0xa00 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); 8001706: 4319 orrs r1, r3 8001708: f441 7180 orr.w r1, r1, #256 ; 0x100 } /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 800170c: 8384 strh r4, [r0, #28] TIMx->CCER = tmpccer; 800170e: 8401 strh r1, [r0, #32] } 8001710: bc70 pop {r4, r5, r6} 8001712: 4770 bx lr tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); 8001714: f426 7100 bic.w r1, r6, #512 ; 0x200 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); 8001718: 4329 orrs r1, r5 800171a: f441 7180 orr.w r1, r1, #256 ; 0x100 800171e: e7f5 b.n 800170c 8001720: 40012c00 .word 0x40012c00 08001724 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 8001724: b470 push {r4, r5, r6} uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); 8001726: 8c04 ldrh r4, [r0, #32] 8001728: b2a4 uxth r4, r4 800172a: f424 5480 bic.w r4, r4, #4096 ; 0x1000 800172e: b2a4 uxth r4, r4 8001730: 8404 strh r4, [r0, #32] tmpccmr2 = TIMx->CCMR2; 8001732: 8b84 ldrh r4, [r0, #28] tmpccer = TIMx->CCER; 8001734: 8c05 ldrh r5, [r0, #32] 8001736: b2ad uxth r5, r5 tmp = (uint16_t)(TIM_ICPolarity << 12); 8001738: 030e lsls r6, r1, #12 800173a: b2b6 uxth r6, r6 /* Select the Input and set the filter */ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); 800173c: f424 7440 bic.w r4, r4, #768 ; 0x300 8001740: 0524 lsls r4, r4, #20 8001742: 0d24 lsrs r4, r4, #20 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); 8001744: 0212 lsls r2, r2, #8 8001746: b292 uxth r2, r2 8001748: 4314 orrs r4, r2 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); 800174a: 031b lsls r3, r3, #12 800174c: b29b uxth r3, r3 800174e: 431c orrs r4, r3 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 8001750: 4b13 ldr r3, [pc, #76] ; (80017a0 ) 8001752: 4298 cmp r0, r3 8001754: d01d beq.n 8001792 8001756: f503 6300 add.w r3, r3, #2048 ; 0x800 800175a: 4298 cmp r0, r3 800175c: d019 beq.n 8001792 800175e: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 8001762: d016 beq.n 8001792 8001764: f5a3 3398 sub.w r3, r3, #77824 ; 0x13000 8001768: 4298 cmp r0, r3 800176a: d012 beq.n 8001792 800176c: f503 6380 add.w r3, r3, #1024 ; 0x400 8001770: 4298 cmp r0, r3 8001772: d00e beq.n 8001792 (TIMx == TIM4) ||(TIMx == TIM5)) 8001774: f503 6380 add.w r3, r3, #1024 ; 0x400 8001778: 4298 cmp r0, r3 800177a: d00a beq.n 8001792 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); } else { /* Select the Polarity and set the CC4E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); 800177c: f425 7500 bic.w r5, r5, #512 ; 0x200 8001780: 046d lsls r5, r5, #17 8001782: 0c6d lsrs r5, r5, #17 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); 8001784: 4329 orrs r1, r5 8001786: f441 5180 orr.w r1, r1, #4096 ; 0x1000 } /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 800178a: 8384 strh r4, [r0, #28] TIMx->CCER = tmpccer; 800178c: 8401 strh r1, [r0, #32] } 800178e: bc70 pop {r4, r5, r6} 8001790: 4770 bx lr tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); 8001792: f425 5100 bic.w r1, r5, #8192 ; 0x2000 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); 8001796: 4331 orrs r1, r6 8001798: f441 5180 orr.w r1, r1, #4096 ; 0x1000 800179c: e7f5 b.n 800178a 800179e: bf00 nop 80017a0: 40012c00 .word 0x40012c00 080017a4 : tmpcr1 = TIMx->CR1; 80017a4: 8803 ldrh r3, [r0, #0] 80017a6: b29b uxth r3, r3 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| 80017a8: 4a21 ldr r2, [pc, #132] ; (8001830 ) 80017aa: 4290 cmp r0, r2 80017ac: d012 beq.n 80017d4 80017ae: f502 6200 add.w r2, r2, #2048 ; 0x800 80017b2: 4290 cmp r0, r2 80017b4: d00e beq.n 80017d4 80017b6: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 80017ba: d00b beq.n 80017d4 80017bc: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 80017c0: 4290 cmp r0, r2 80017c2: d007 beq.n 80017d4 80017c4: f502 6280 add.w r2, r2, #1024 ; 0x400 80017c8: 4290 cmp r0, r2 80017ca: d003 beq.n 80017d4 (TIMx == TIM4) || (TIMx == TIM5)) 80017cc: f502 6280 add.w r2, r2, #1024 ; 0x400 80017d0: 4290 cmp r0, r2 80017d2: d103 bne.n 80017dc tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); 80017d4: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 80017d8: 884a ldrh r2, [r1, #2] 80017da: 4313 orrs r3, r2 if((TIMx != TIM6) && (TIMx != TIM7)) 80017dc: 4a15 ldr r2, [pc, #84] ; (8001834 ) 80017de: 4290 cmp r0, r2 80017e0: d008 beq.n 80017f4 80017e2: f502 6280 add.w r2, r2, #1024 ; 0x400 80017e6: 4290 cmp r0, r2 80017e8: d004 beq.n 80017f4 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); 80017ea: f423 7340 bic.w r3, r3, #768 ; 0x300 80017ee: b29b uxth r3, r3 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 80017f0: 88ca ldrh r2, [r1, #6] 80017f2: 4313 orrs r3, r2 TIMx->CR1 = tmpcr1; 80017f4: 8003 strh r3, [r0, #0] TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 80017f6: 888b ldrh r3, [r1, #4] 80017f8: 8583 strh r3, [r0, #44] ; 0x2c TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 80017fa: 880b ldrh r3, [r1, #0] 80017fc: 8503 strh r3, [r0, #40] ; 0x28 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) 80017fe: 4b0c ldr r3, [pc, #48] ; (8001830 ) 8001800: 4298 cmp r0, r3 8001802: d00f beq.n 8001824 8001804: f503 6300 add.w r3, r3, #2048 ; 0x800 8001808: 4298 cmp r0, r3 800180a: d00b beq.n 8001824 800180c: f503 6340 add.w r3, r3, #3072 ; 0xc00 8001810: 4298 cmp r0, r3 8001812: d007 beq.n 8001824 8001814: f503 6380 add.w r3, r3, #1024 ; 0x400 8001818: 4298 cmp r0, r3 800181a: d003 beq.n 8001824 800181c: f503 6380 add.w r3, r3, #1024 ; 0x400 8001820: 4298 cmp r0, r3 8001822: d101 bne.n 8001828 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 8001824: 7a0b ldrb r3, [r1, #8] 8001826: 8603 strh r3, [r0, #48] ; 0x30 TIMx->EGR = TIM_PSCReloadMode_Immediate; 8001828: 2301 movs r3, #1 800182a: 8283 strh r3, [r0, #20] 800182c: 4770 bx lr 800182e: bf00 nop 8001830: 40012c00 .word 0x40012c00 8001834: 40001000 .word 0x40001000 08001838 : { 8001838: b430 push {r4, r5} TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); 800183a: 8c03 ldrh r3, [r0, #32] 800183c: b29b uxth r3, r3 800183e: f023 0310 bic.w r3, r3, #16 8001842: b29b uxth r3, r3 8001844: 8403 strh r3, [r0, #32] tmpccer = TIMx->CCER; 8001846: 8c03 ldrh r3, [r0, #32] 8001848: b29b uxth r3, r3 tmpcr2 = TIMx->CR2; 800184a: 8885 ldrh r5, [r0, #4] 800184c: b2ad uxth r5, r5 tmpccmrx = TIMx->CCMR1; 800184e: 8b02 ldrh r2, [r0, #24] 8001850: b292 uxth r2, r2 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); 8001852: f422 44e6 bic.w r4, r2, #29440 ; 0x7300 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 8001856: 880a ldrh r2, [r1, #0] 8001858: 0212 lsls r2, r2, #8 800185a: b292 uxth r2, r2 800185c: 4322 orrs r2, r4 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); 800185e: f023 0320 bic.w r3, r3, #32 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); 8001862: 890c ldrh r4, [r1, #8] 8001864: 0124 lsls r4, r4, #4 8001866: b2a4 uxth r4, r4 8001868: 4323 orrs r3, r4 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); 800186a: 884c ldrh r4, [r1, #2] 800186c: 0124 lsls r4, r4, #4 800186e: b2a4 uxth r4, r4 8001870: 4323 orrs r3, r4 if((TIMx == TIM1) || (TIMx == TIM8)) 8001872: 4c12 ldr r4, [pc, #72] ; (80018bc ) 8001874: 42a0 cmp r0, r4 8001876: d00a beq.n 800188e 8001878: f504 6400 add.w r4, r4, #2048 ; 0x800 800187c: 42a0 cmp r0, r4 800187e: d006 beq.n 800188e TIMx->CR2 = tmpcr2; 8001880: 8085 strh r5, [r0, #4] TIMx->CCMR1 = tmpccmrx; 8001882: 8302 strh r2, [r0, #24] TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; 8001884: 88ca ldrh r2, [r1, #6] 8001886: 8702 strh r2, [r0, #56] ; 0x38 TIMx->CCER = tmpccer; 8001888: 8403 strh r3, [r0, #32] } 800188a: bc30 pop {r4, r5} 800188c: 4770 bx lr tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); 800188e: f023 0380 bic.w r3, r3, #128 ; 0x80 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); 8001892: 894c ldrh r4, [r1, #10] 8001894: 0124 lsls r4, r4, #4 8001896: b2a4 uxth r4, r4 8001898: 4323 orrs r3, r4 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); 800189a: f023 0440 bic.w r4, r3, #64 ; 0x40 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); 800189e: 888b ldrh r3, [r1, #4] 80018a0: 011b lsls r3, r3, #4 80018a2: b29b uxth r3, r3 80018a4: 4323 orrs r3, r4 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); 80018a6: f425 6540 bic.w r5, r5, #3072 ; 0xc00 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); 80018aa: 898c ldrh r4, [r1, #12] 80018ac: 00a4 lsls r4, r4, #2 80018ae: b2a4 uxth r4, r4 80018b0: 4325 orrs r5, r4 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); 80018b2: 89cc ldrh r4, [r1, #14] 80018b4: 00a4 lsls r4, r4, #2 80018b6: b2a4 uxth r4, r4 80018b8: 4325 orrs r5, r4 80018ba: e7e1 b.n 8001880 80018bc: 40012c00 .word 0x40012c00 080018c0 : { 80018c0: b430 push {r4, r5} TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); 80018c2: 8c03 ldrh r3, [r0, #32] 80018c4: b29b uxth r3, r3 80018c6: f423 7380 bic.w r3, r3, #256 ; 0x100 80018ca: b29b uxth r3, r3 80018cc: 8403 strh r3, [r0, #32] tmpccer = TIMx->CCER; 80018ce: 8c03 ldrh r3, [r0, #32] 80018d0: b29b uxth r3, r3 tmpcr2 = TIMx->CR2; 80018d2: 8885 ldrh r5, [r0, #4] 80018d4: b2ad uxth r5, r5 tmpccmrx = TIMx->CCMR2; 80018d6: 8b82 ldrh r2, [r0, #28] 80018d8: b292 uxth r2, r2 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); 80018da: f022 0273 bic.w r2, r2, #115 ; 0x73 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 80018de: 880c ldrh r4, [r1, #0] 80018e0: 4322 orrs r2, r4 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); 80018e2: f423 7300 bic.w r3, r3, #512 ; 0x200 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); 80018e6: 890c ldrh r4, [r1, #8] 80018e8: 0224 lsls r4, r4, #8 80018ea: b2a4 uxth r4, r4 80018ec: 4323 orrs r3, r4 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); 80018ee: 884c ldrh r4, [r1, #2] 80018f0: 0224 lsls r4, r4, #8 80018f2: b2a4 uxth r4, r4 80018f4: 4323 orrs r3, r4 if((TIMx == TIM1) || (TIMx == TIM8)) 80018f6: 4c12 ldr r4, [pc, #72] ; (8001940 ) 80018f8: 42a0 cmp r0, r4 80018fa: d00a beq.n 8001912 80018fc: f504 6400 add.w r4, r4, #2048 ; 0x800 8001900: 42a0 cmp r0, r4 8001902: d006 beq.n 8001912 TIMx->CR2 = tmpcr2; 8001904: 8085 strh r5, [r0, #4] TIMx->CCMR2 = tmpccmrx; 8001906: 8382 strh r2, [r0, #28] TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; 8001908: 88ca ldrh r2, [r1, #6] 800190a: 8782 strh r2, [r0, #60] ; 0x3c TIMx->CCER = tmpccer; 800190c: 8403 strh r3, [r0, #32] } 800190e: bc30 pop {r4, r5} 8001910: 4770 bx lr tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); 8001912: f423 6300 bic.w r3, r3, #2048 ; 0x800 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); 8001916: 894c ldrh r4, [r1, #10] 8001918: 0224 lsls r4, r4, #8 800191a: b2a4 uxth r4, r4 800191c: 4323 orrs r3, r4 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); 800191e: f423 6480 bic.w r4, r3, #1024 ; 0x400 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); 8001922: 888b ldrh r3, [r1, #4] 8001924: 021b lsls r3, r3, #8 8001926: b29b uxth r3, r3 8001928: 4323 orrs r3, r4 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); 800192a: f425 5540 bic.w r5, r5, #12288 ; 0x3000 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); 800192e: 898c ldrh r4, [r1, #12] 8001930: 0124 lsls r4, r4, #4 8001932: b2a4 uxth r4, r4 8001934: 4325 orrs r5, r4 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); 8001936: 89cc ldrh r4, [r1, #14] 8001938: 0124 lsls r4, r4, #4 800193a: b2a4 uxth r4, r4 800193c: 4325 orrs r5, r4 800193e: e7e1 b.n 8001904 8001940: 40012c00 .word 0x40012c00 08001944 : if (NewState != DISABLE) 8001944: b931 cbnz r1, 8001954 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); 8001946: 8803 ldrh r3, [r0, #0] 8001948: b29b uxth r3, r3 800194a: f023 0301 bic.w r3, r3, #1 800194e: b29b uxth r3, r3 8001950: 8003 strh r3, [r0, #0] 8001952: 4770 bx lr TIMx->CR1 |= TIM_CR1_CEN; 8001954: 8803 ldrh r3, [r0, #0] 8001956: b29b uxth r3, r3 8001958: f043 0301 orr.w r3, r3, #1 800195c: 8003 strh r3, [r0, #0] 800195e: 4770 bx lr 08001960 : if (NewState != DISABLE) 8001960: b931 cbnz r1, 8001970 TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); 8001962: f8b0 3044 ldrh.w r3, [r0, #68] ; 0x44 8001966: f3c3 030e ubfx r3, r3, #0, #15 800196a: f8a0 3044 strh.w r3, [r0, #68] ; 0x44 800196e: 4770 bx lr TIMx->BDTR |= TIM_BDTR_MOE; 8001970: f8b0 3044 ldrh.w r3, [r0, #68] ; 0x44 8001974: ea6f 4343 mvn.w r3, r3, lsl #17 8001978: ea6f 4353 mvn.w r3, r3, lsr #17 800197c: b29b uxth r3, r3 800197e: f8a0 3044 strh.w r3, [r0, #68] ; 0x44 8001982: 4770 bx lr 08001984 : if (NewState != DISABLE) 8001984: b92a cbnz r2, 8001992 TIMx->DIER &= (uint16_t)~TIM_IT; 8001986: 8983 ldrh r3, [r0, #12] 8001988: 43c9 mvns r1, r1 800198a: b289 uxth r1, r1 800198c: 4019 ands r1, r3 800198e: 8181 strh r1, [r0, #12] 8001990: 4770 bx lr TIMx->DIER |= TIM_IT; 8001992: 8983 ldrh r3, [r0, #12] 8001994: b29b uxth r3, r3 8001996: 4319 orrs r1, r3 8001998: 8181 strh r1, [r0, #12] 800199a: 4770 bx lr 0800199c : if (NewState != DISABLE) 800199c: b931 cbnz r1, 80019ac TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); 800199e: 8803 ldrh r3, [r0, #0] 80019a0: b29b uxth r3, r3 80019a2: f023 0380 bic.w r3, r3, #128 ; 0x80 80019a6: b29b uxth r3, r3 80019a8: 8003 strh r3, [r0, #0] 80019aa: 4770 bx lr TIMx->CR1 |= TIM_CR1_ARPE; 80019ac: 8803 ldrh r3, [r0, #0] 80019ae: b29b uxth r3, r3 80019b0: f043 0380 orr.w r3, r3, #128 ; 0x80 80019b4: 8003 strh r3, [r0, #0] 80019b6: 4770 bx lr 080019b8 : tmpccmr1 = TIMx->CCMR1; 80019b8: 8b03 ldrh r3, [r0, #24] 80019ba: b29b uxth r3, r3 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); 80019bc: f423 6300 bic.w r3, r3, #2048 ; 0x800 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); 80019c0: 0209 lsls r1, r1, #8 80019c2: b289 uxth r1, r1 80019c4: 430b orrs r3, r1 TIMx->CCMR1 = tmpccmr1; 80019c6: 8303 strh r3, [r0, #24] 80019c8: 4770 bx lr 080019ca : tmpccmr2 = TIMx->CCMR2; 80019ca: 8b83 ldrh r3, [r0, #28] 80019cc: b29b uxth r3, r3 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); 80019ce: f023 0308 bic.w r3, r3, #8 tmpccmr2 |= TIM_OCPreload; 80019d2: 4319 orrs r1, r3 TIMx->CCMR2 = tmpccmr2; 80019d4: 8381 strh r1, [r0, #28] 80019d6: 4770 bx lr 080019d8 : TIMx->CCR2 = Compare2; 80019d8: 8701 strh r1, [r0, #56] ; 0x38 80019da: 4770 bx lr 080019dc : TIMx->CCR3 = Compare3; 80019dc: 8781 strh r1, [r0, #60] ; 0x3c 80019de: 4770 bx lr 080019e0 : TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); 80019e0: 8b03 ldrh r3, [r0, #24] 80019e2: b29b uxth r3, r3 80019e4: f023 030c bic.w r3, r3, #12 80019e8: b29b uxth r3, r3 80019ea: 8303 strh r3, [r0, #24] TIMx->CCMR1 |= TIM_ICPSC; 80019ec: 8b03 ldrh r3, [r0, #24] 80019ee: b29b uxth r3, r3 80019f0: 4319 orrs r1, r3 80019f2: 8301 strh r1, [r0, #24] 80019f4: 4770 bx lr 080019f6 : TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); 80019f6: 8b03 ldrh r3, [r0, #24] 80019f8: b29b uxth r3, r3 80019fa: f423 6340 bic.w r3, r3, #3072 ; 0xc00 80019fe: b29b uxth r3, r3 8001a00: 8303 strh r3, [r0, #24] TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); 8001a02: 8b03 ldrh r3, [r0, #24] 8001a04: b29b uxth r3, r3 8001a06: 0209 lsls r1, r1, #8 8001a08: b289 uxth r1, r1 8001a0a: 430b orrs r3, r1 8001a0c: 8303 strh r3, [r0, #24] 8001a0e: 4770 bx lr 08001a10 : TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); 8001a10: 8b83 ldrh r3, [r0, #28] 8001a12: b29b uxth r3, r3 8001a14: f023 030c bic.w r3, r3, #12 8001a18: b29b uxth r3, r3 8001a1a: 8383 strh r3, [r0, #28] TIMx->CCMR2 |= TIM_ICPSC; 8001a1c: 8b83 ldrh r3, [r0, #28] 8001a1e: b29b uxth r3, r3 8001a20: 4319 orrs r1, r3 8001a22: 8381 strh r1, [r0, #28] 8001a24: 4770 bx lr 08001a26 : TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); 8001a26: 8b83 ldrh r3, [r0, #28] 8001a28: b29b uxth r3, r3 8001a2a: f423 6340 bic.w r3, r3, #3072 ; 0xc00 8001a2e: b29b uxth r3, r3 8001a30: 8383 strh r3, [r0, #28] TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); 8001a32: 8b83 ldrh r3, [r0, #28] 8001a34: b29b uxth r3, r3 8001a36: 0209 lsls r1, r1, #8 8001a38: b289 uxth r1, r1 8001a3a: 430b orrs r3, r1 8001a3c: 8383 strh r3, [r0, #28] 8001a3e: 4770 bx lr 08001a40 : { 8001a40: b538 push {r3, r4, r5, lr} 8001a42: 4605 mov r5, r0 8001a44: 460c mov r4, r1 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 8001a46: 880b ldrh r3, [r1, #0] 8001a48: b16b cbz r3, 8001a66 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) 8001a4a: 2b04 cmp r3, #4 8001a4c: d015 beq.n 8001a7a else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) 8001a4e: 2b08 cmp r3, #8 8001a50: d01d beq.n 8001a8e TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 8001a52: 890b ldrh r3, [r1, #8] 8001a54: 888a ldrh r2, [r1, #4] 8001a56: 8849 ldrh r1, [r1, #2] 8001a58: f7ff fe64 bl 8001724 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 8001a5c: 88e1 ldrh r1, [r4, #6] 8001a5e: 4628 mov r0, r5 8001a60: f7ff ffe1 bl 8001a26 8001a64: bd38 pop {r3, r4, r5, pc} TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 8001a66: 890b ldrh r3, [r1, #8] 8001a68: 888a ldrh r2, [r1, #4] 8001a6a: 8849 ldrh r1, [r1, #2] 8001a6c: f7ff fda8 bl 80015c0 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 8001a70: 88e1 ldrh r1, [r4, #6] 8001a72: 4628 mov r0, r5 8001a74: f7ff ffb4 bl 80019e0 8001a78: bd38 pop {r3, r4, r5, pc} TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 8001a7a: 890b ldrh r3, [r1, #8] 8001a7c: 888a ldrh r2, [r1, #4] 8001a7e: 8849 ldrh r1, [r1, #2] 8001a80: f7ff fdd8 bl 8001634 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 8001a84: 88e1 ldrh r1, [r4, #6] 8001a86: 4628 mov r0, r5 8001a88: f7ff ffb5 bl 80019f6 8001a8c: bd38 pop {r3, r4, r5, pc} TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 8001a8e: 890b ldrh r3, [r1, #8] 8001a90: 888a ldrh r2, [r1, #4] 8001a92: 8849 ldrh r1, [r1, #2] 8001a94: f7ff fe0c bl 80016b0 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 8001a98: 88e1 ldrh r1, [r4, #6] 8001a9a: 4628 mov r0, r5 8001a9c: f7ff ffb8 bl 8001a10 8001aa0: bd38 pop {r3, r4, r5, pc} 08001aa2 : itstatus = TIMx->SR & TIM_IT; 8001aa2: 8a02 ldrh r2, [r0, #16] itenable = TIMx->DIER & TIM_IT; 8001aa4: 8983 ldrh r3, [r0, #12] 8001aa6: 400b ands r3, r1 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 8001aa8: 4211 tst r1, r2 8001aaa: d002 beq.n 8001ab2 8001aac: b91b cbnz r3, 8001ab6 bitstatus = RESET; 8001aae: 2000 movs r0, #0 8001ab0: 4770 bx lr 8001ab2: 2000 movs r0, #0 8001ab4: 4770 bx lr bitstatus = SET; 8001ab6: 2001 movs r0, #1 } 8001ab8: 4770 bx lr 08001aba : TIMx->SR = (uint16_t)~TIM_IT; 8001aba: 43c9 mvns r1, r1 8001abc: b289 uxth r1, r1 8001abe: 8201 strh r1, [r0, #16] 8001ac0: 4770 bx lr ... 08001ac4 : * that contains the configuration information for the specified USART * peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { 8001ac4: b530 push {r4, r5, lr} 8001ac6: b087 sub sp, #28 8001ac8: 4604 mov r4, r0 8001aca: 460d mov r5, r1 } usartxbase = (uint32_t)USARTx; /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; 8001acc: 8a03 ldrh r3, [r0, #16] 8001ace: b29b uxth r3, r3 /* Clear STOP[13:12] bits */ tmpreg &= CR2_STOP_CLEAR_Mask; /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ /* Set STOP[13:12] bits according to USART_StopBits value */ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; 8001ad0: 88ca ldrh r2, [r1, #6] 8001ad2: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001ad6: 4313 orrs r3, r2 /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; 8001ad8: 8203 strh r3, [r0, #16] /*---------------------------- USART CR1 Configuration -----------------------*/ tmpreg = USARTx->CR1; 8001ada: 8983 ldrh r3, [r0, #12] 8001adc: b29b uxth r3, r3 tmpreg &= CR1_CLEAR_Mask; /* Configure the USART Word Length, Parity and mode ----------------------- */ /* Set the M bits according to USART_WordLength value */ /* Set PCE and PS bits according to USART_Parity value */ /* Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 8001ade: 8889 ldrh r1, [r1, #4] 8001ae0: 8928 ldrh r0, [r5, #8] USART_InitStruct->USART_Mode; 8001ae2: 896a ldrh r2, [r5, #10] tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 8001ae4: 4301 orrs r1, r0 8001ae6: 430a orrs r2, r1 8001ae8: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8001aec: f023 030c bic.w r3, r3, #12 8001af0: 4313 orrs r3, r2 /* Write to USART CR1 */ USARTx->CR1 = (uint16_t)tmpreg; 8001af2: 81a3 strh r3, [r4, #12] /*---------------------------- USART CR3 Configuration -----------------------*/ tmpreg = USARTx->CR3; 8001af4: 8aa3 ldrh r3, [r4, #20] 8001af6: b29b uxth r3, r3 /* Clear CTSE and RTSE bits */ tmpreg &= CR3_CLEAR_Mask; /* Configure the USART HFC -------------------------------------------------*/ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ tmpreg |= USART_InitStruct->USART_HardwareFlowControl; 8001af8: 89aa ldrh r2, [r5, #12] 8001afa: f423 7340 bic.w r3, r3, #768 ; 0x300 8001afe: 4313 orrs r3, r2 /* Write to USART CR3 */ USARTx->CR3 = (uint16_t)tmpreg; 8001b00: 82a3 strh r3, [r4, #20] /*---------------------------- USART BRR Configuration -----------------------*/ /* Configure the USART Baud Rate -------------------------------------------*/ RCC_GetClocksFreq(&RCC_ClocksStatus); 8001b02: a801 add r0, sp, #4 8001b04: f7ff fcd4 bl 80014b0 if (usartxbase == USART1_BASE) 8001b08: 4b1e ldr r3, [pc, #120] ; (8001b84 ) 8001b0a: 429c cmp r4, r3 8001b0c: d024 beq.n 8001b58 { apbclock = RCC_ClocksStatus.PCLK2_Frequency; } else { apbclock = RCC_ClocksStatus.PCLK1_Frequency; 8001b0e: 9b03 ldr r3, [sp, #12] } /* Determine the integer part */ if ((USARTx->CR1 & CR1_OVER8_Set) != 0) 8001b10: 89a2 ldrh r2, [r4, #12] 8001b12: f412 4f00 tst.w r2, #32768 ; 0x8000 8001b16: d121 bne.n 8001b5c integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); } else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ { /* Integer part computing in case Oversampling mode is 16 Samples */ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); 8001b18: eb03 0383 add.w r3, r3, r3, lsl #2 8001b1c: eb03 0383 add.w r3, r3, r3, lsl #2 8001b20: 6829 ldr r1, [r5, #0] 8001b22: 0089 lsls r1, r1, #2 8001b24: fbb3 f1f1 udiv r1, r3, r1 } tmpreg = (integerdivider / 100) << 4; 8001b28: 4b17 ldr r3, [pc, #92] ; (8001b88 ) 8001b2a: fba3 2301 umull r2, r3, r3, r1 8001b2e: 0958 lsrs r0, r3, #5 8001b30: 0105 lsls r5, r0, #4 /* Determine the fractional part */ fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); 8001b32: 2364 movs r3, #100 ; 0x64 8001b34: fb00 1313 mls r3, r0, r3, r1 /* Implement the fractional part in the register */ if ((USARTx->CR1 & CR1_OVER8_Set) != 0) 8001b38: 89a2 ldrh r2, [r4, #12] 8001b3a: f412 4f00 tst.w r2, #32768 ; 0x8000 8001b3e: d116 bne.n 8001b6e { tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); } else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ { tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); 8001b40: 011b lsls r3, r3, #4 8001b42: 3332 adds r3, #50 ; 0x32 8001b44: 4a10 ldr r2, [pc, #64] ; (8001b88 ) 8001b46: fba2 2303 umull r2, r3, r2, r3 8001b4a: f3c3 1343 ubfx r3, r3, #5, #4 8001b4e: 432b orrs r3, r5 } /* Write to USART BRR */ USARTx->BRR = (uint16_t)tmpreg; 8001b50: b29b uxth r3, r3 8001b52: 8123 strh r3, [r4, #8] } 8001b54: b007 add sp, #28 8001b56: bd30 pop {r4, r5, pc} apbclock = RCC_ClocksStatus.PCLK2_Frequency; 8001b58: 9b04 ldr r3, [sp, #16] 8001b5a: e7d9 b.n 8001b10 integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); 8001b5c: eb03 0383 add.w r3, r3, r3, lsl #2 8001b60: eb03 0383 add.w r3, r3, r3, lsl #2 8001b64: 6829 ldr r1, [r5, #0] 8001b66: 0049 lsls r1, r1, #1 8001b68: fbb3 f1f1 udiv r1, r3, r1 8001b6c: e7dc b.n 8001b28 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); 8001b6e: 00d9 lsls r1, r3, #3 8001b70: 3132 adds r1, #50 ; 0x32 8001b72: 4a05 ldr r2, [pc, #20] ; (8001b88 ) 8001b74: fba2 3101 umull r3, r1, r2, r1 8001b78: f3c1 1242 ubfx r2, r1, #5, #3 8001b7c: ea45 0302 orr.w r3, r5, r2 8001b80: e7e6 b.n 8001b50 8001b82: bf00 nop 8001b84: 40013800 .word 0x40013800 8001b88: 51eb851f .word 0x51eb851f 08001b8c : { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8001b8c: b931 cbnz r1, 8001b9c USARTx->CR1 |= CR1_UE_Set; } else { /* Disable the selected USART by clearing the UE bit in the CR1 register */ USARTx->CR1 &= CR1_UE_Reset; 8001b8e: 8983 ldrh r3, [r0, #12] 8001b90: b29b uxth r3, r3 8001b92: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8001b96: b29b uxth r3, r3 8001b98: 8183 strh r3, [r0, #12] 8001b9a: 4770 bx lr USARTx->CR1 |= CR1_UE_Set; 8001b9c: 8983 ldrh r3, [r0, #12] 8001b9e: b29b uxth r3, r3 8001ba0: f443 5300 orr.w r3, r3, #8192 ; 0x2000 8001ba4: 8183 strh r3, [r0, #12] 8001ba6: 4770 bx lr 08001ba8 : * @param NewState: new state of the specified USARTx interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) { 8001ba8: b410 push {r4} } usartxbase = (uint32_t)USARTx; /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); 8001baa: f3c1 1442 ubfx r4, r1, #5, #3 /* Get the interrupt position */ itpos = USART_IT & IT_Mask; 8001bae: f001 011f and.w r1, r1, #31 itmask = (((uint32_t)0x01) << itpos); 8001bb2: 2301 movs r3, #1 8001bb4: fa03 f101 lsl.w r1, r3, r1 if (usartreg == 0x01) /* The IT is in CR1 register */ 8001bb8: 429c cmp r4, r3 8001bba: d009 beq.n 8001bd0 { usartxbase += 0x0C; } else if (usartreg == 0x02) /* The IT is in CR2 register */ 8001bbc: 2c02 cmp r4, #2 8001bbe: d009 beq.n 8001bd4 { usartxbase += 0x10; } else /* The IT is in CR3 register */ { usartxbase += 0x14; 8001bc0: 3014 adds r0, #20 } if (NewState != DISABLE) 8001bc2: b94a cbnz r2, 8001bd8 { *(__IO uint32_t*)usartxbase |= itmask; } else { *(__IO uint32_t*)usartxbase &= ~itmask; 8001bc4: 6803 ldr r3, [r0, #0] 8001bc6: ea23 0101 bic.w r1, r3, r1 8001bca: 6001 str r1, [r0, #0] } } 8001bcc: bc10 pop {r4} 8001bce: 4770 bx lr usartxbase += 0x0C; 8001bd0: 300c adds r0, #12 8001bd2: e7f6 b.n 8001bc2 usartxbase += 0x10; 8001bd4: 3010 adds r0, #16 8001bd6: e7f4 b.n 8001bc2 *(__IO uint32_t*)usartxbase |= itmask; 8001bd8: 6803 ldr r3, [r0, #0] 8001bda: 4319 orrs r1, r3 8001bdc: 6001 str r1, [r0, #0] 8001bde: e7f5 b.n 8001bcc 08001be0 : { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DMAREQ(USART_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8001be0: b92a cbnz r2, 8001bee } else { /* Disable the DMA transfer for selected requests by clearing the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 &= (uint16_t)~USART_DMAReq; 8001be2: 8a83 ldrh r3, [r0, #20] 8001be4: 43c9 mvns r1, r1 8001be6: b289 uxth r1, r1 8001be8: 4019 ands r1, r3 8001bea: 8281 strh r1, [r0, #20] 8001bec: 4770 bx lr USARTx->CR3 |= USART_DMAReq; 8001bee: 8a83 ldrh r3, [r0, #20] 8001bf0: b29b uxth r3, r3 8001bf2: 4319 orrs r1, r3 8001bf4: 8281 strh r1, [r0, #20] 8001bf6: 4770 bx lr 08001bf8 : { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Receive Data */ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); 8001bf8: 8880 ldrh r0, [r0, #4] } 8001bfa: f3c0 0008 ubfx r0, r0, #0, #9 8001bfe: 4770 bx lr 08001c00 : if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) { assert_param(IS_USART_123_PERIPH(USARTx)); } USARTx->SR = (uint16_t)~USART_FLAG; 8001c00: 43c9 mvns r1, r1 8001c02: b289 uxth r1, r1 8001c04: 8001 strh r1, [r0, #0] 8001c06: 4770 bx lr 08001c08 : * @arg USART_IT_FE: Framing Error interrupt * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of USART_IT (SET or RESET). */ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) { 8001c08: b410 push {r4} { assert_param(IS_USART_123_PERIPH(USARTx)); } /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); 8001c0a: f3c1 1242 ubfx r2, r1, #5, #3 /* Get the interrupt position */ itmask = USART_IT & IT_Mask; 8001c0e: f001 041f and.w r4, r1, #31 itmask = (uint32_t)0x01 << itmask; 8001c12: 2301 movs r3, #1 8001c14: 40a3 lsls r3, r4 if (usartreg == 0x01) /* The IT is in CR1 register */ 8001c16: 2a01 cmp r2, #1 8001c18: d00f beq.n 8001c3a { itmask &= USARTx->CR1; } else if (usartreg == 0x02) /* The IT is in CR2 register */ 8001c1a: 2a02 cmp r2, #2 8001c1c: d011 beq.n 8001c42 { itmask &= USARTx->CR2; } else /* The IT is in CR3 register */ { itmask &= USARTx->CR3; 8001c1e: 8a82 ldrh r2, [r0, #20] 8001c20: b292 uxth r2, r2 8001c22: 4013 ands r3, r2 } bitpos = USART_IT >> 0x08; 8001c24: 0a09 lsrs r1, r1, #8 bitpos = (uint32_t)0x01 << bitpos; 8001c26: 2201 movs r2, #1 8001c28: fa02 f101 lsl.w r1, r2, r1 bitpos &= USARTx->SR; 8001c2c: 8802 ldrh r2, [r0, #0] 8001c2e: b292 uxth r2, r2 8001c30: 4011 ands r1, r2 if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) 8001c32: b153 cbz r3, 8001c4a 8001c34: b961 cbnz r1, 8001c50 { bitstatus = SET; } else { bitstatus = RESET; 8001c36: 2000 movs r0, #0 8001c38: e008 b.n 8001c4c itmask &= USARTx->CR1; 8001c3a: 8982 ldrh r2, [r0, #12] 8001c3c: b292 uxth r2, r2 8001c3e: 4013 ands r3, r2 8001c40: e7f0 b.n 8001c24 itmask &= USARTx->CR2; 8001c42: 8a02 ldrh r2, [r0, #16] 8001c44: b292 uxth r2, r2 8001c46: 4013 ands r3, r2 8001c48: e7ec b.n 8001c24 bitstatus = RESET; 8001c4a: 2000 movs r0, #0 } return bitstatus; } 8001c4c: bc10 pop {r4} 8001c4e: 4770 bx lr bitstatus = SET; 8001c50: 2001 movs r0, #1 8001c52: e7fb b.n 8001c4c 08001c54 : * @retval None * */ void batteryConfigure(void) { 8001c54: b5f0 push {r4, r5, r6, r7, lr} 8001c56: b08b sub sp, #44 ; 0x2c GPIO_InitTypeDef Init_Structure; NVIC_InitTypeDef NVIC_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; ADC_InitTypeDef ADC_InitStructure; Init_Structure.GPIO_Pin = GPIO_Pin_3; 8001c58: 2608 movs r6, #8 8001c5a: f8ad 6024 strh.w r6, [sp, #36] ; 0x24 Init_Structure.GPIO_Speed = GPIO_Speed_10MHz; 8001c5e: 2401 movs r4, #1 8001c60: f88d 4026 strb.w r4, [sp, #38] ; 0x26 Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP; 8001c64: 2318 movs r3, #24 8001c66: f88d 3027 strb.w r3, [sp, #39] ; 0x27 GPIO_Init(GPIOA, &Init_Structure); 8001c6a: 4f4a ldr r7, [pc, #296] ; (8001d94 ) 8001c6c: a909 add r1, sp, #36 ; 0x24 8001c6e: 4638 mov r0, r7 8001c70: f7ff fb6c bl 800134c // Configure les PIN A0,A4 en input floating. Init_Structure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_4; 8001c74: 2311 movs r3, #17 8001c76: f8ad 3024 strh.w r3, [sp, #36] ; 0x24 Init_Structure.GPIO_Mode = GPIO_Mode_AIN; 8001c7a: 2500 movs r5, #0 8001c7c: f88d 5027 strb.w r5, [sp, #39] ; 0x27 GPIO_Init(GPIOA, &Init_Structure); 8001c80: a909 add r1, sp, #36 ; 0x24 8001c82: 4638 mov r0, r7 8001c84: f7ff fb62 bl 800134c // Configure PB11 en input pullup Init_Structure.GPIO_Pin = GPIO_Pin_11; 8001c88: f44f 6700 mov.w r7, #2048 ; 0x800 8001c8c: f8ad 7024 strh.w r7, [sp, #36] ; 0x24 Init_Structure.GPIO_Mode = GPIO_Mode_IPU; 8001c90: 2348 movs r3, #72 ; 0x48 8001c92: f88d 3027 strb.w r3, [sp, #39] ; 0x27 GPIO_Init(GPIOB, &Init_Structure); 8001c96: a909 add r1, sp, #36 ; 0x24 8001c98: 483f ldr r0, [pc, #252] ; (8001d98 ) 8001c9a: f7ff fb57 bl 800134c GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource11); 8001c9e: 210b movs r1, #11 8001ca0: 4620 mov r0, r4 8001ca2: f7ff fbe1 bl 8001468 EXTI_InitStructure.EXTI_Line = EXTI_Line11; 8001ca6: 9706 str r7, [sp, #24] EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; 8001ca8: f88d 501c strb.w r5, [sp, #28] EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; 8001cac: f88d 601d strb.w r6, [sp, #29] EXTI_InitStructure.EXTI_LineCmd = ENABLE; 8001cb0: f88d 401e strb.w r4, [sp, #30] EXTI_Init(&EXTI_InitStructure); 8001cb4: a806 add r0, sp, #24 8001cb6: f7ff fb03 bl 80012c0 NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn; 8001cba: 2328 movs r3, #40 ; 0x28 8001cbc: f88d 3020 strb.w r3, [sp, #32] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; 8001cc0: 2303 movs r3, #3 8001cc2: f88d 3021 strb.w r3, [sp, #33] ; 0x21 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 8001cc6: f88d 5022 strb.w r5, [sp, #34] ; 0x22 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 8001cca: f88d 4023 strb.w r4, [sp, #35] ; 0x23 NVIC_Init(&NVIC_InitStructure); 8001cce: a808 add r0, sp, #32 8001cd0: f7ff f92c bl 8000f2c // Initialise la dma pour stocker les valeur dans ADCConvertedValue. DMA_DeInit(DMA1_Channel1); 8001cd4: f106 4680 add.w r6, r6, #1073741824 ; 0x40000000 8001cd8: f506 3600 add.w r6, r6, #131072 ; 0x20000 8001cdc: 4630 mov r0, r6 8001cde: f7ff f9f3 bl 80010c8 DMA_BAT_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(ADC1->DR); // ADC1_DR_Address; 8001ce2: 492e ldr r1, [pc, #184] ; (8001d9c ) 8001ce4: 4b2e ldr r3, [pc, #184] ; (8001da0 ) 8001ce6: 600b str r3, [r1, #0] DMA_BAT_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADCConvertedValue; 8001ce8: 4b2e ldr r3, [pc, #184] ; (8001da4 ) 8001cea: 604b str r3, [r1, #4] DMA_BAT_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 8001cec: 608d str r5, [r1, #8] DMA_BAT_InitStructure.DMA_BufferSize = VOLTAGE_BUFFER_SIZE; // voir schèmas ci dessus 8001cee: 2340 movs r3, #64 ; 0x40 8001cf0: 60cb str r3, [r1, #12] DMA_BAT_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 8001cf2: 610d str r5, [r1, #16] DMA_BAT_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 8001cf4: 2380 movs r3, #128 ; 0x80 8001cf6: 614b str r3, [r1, #20] DMA_BAT_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; 8001cf8: f44f 7380 mov.w r3, #256 ; 0x100 8001cfc: 618b str r3, [r1, #24] DMA_BAT_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; 8001cfe: f44f 6380 mov.w r3, #1024 ; 0x400 8001d02: 61cb str r3, [r1, #28] DMA_BAT_InitStructure.DMA_Mode = DMA_Mode_Normal; 8001d04: 620d str r5, [r1, #32] DMA_BAT_InitStructure.DMA_Priority = DMA_Priority_High; 8001d06: f44f 5300 mov.w r3, #8192 ; 0x2000 8001d0a: 624b str r3, [r1, #36] ; 0x24 DMA_BAT_InitStructure.DMA_M2M = DMA_M2M_Disable; 8001d0c: 628d str r5, [r1, #40] ; 0x28 DMA_Init(DMA1_Channel1, &DMA_BAT_InitStructure); 8001d0e: 4630 mov r0, r6 8001d10: f7ff fa6e bl 80011f0 DMA_Cmd(DMA1_Channel1, ENABLE); 8001d14: 4621 mov r1, r4 8001d16: 4630 mov r0, r6 8001d18: f7ff fa89 bl 800122e DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE); 8001d1c: 4622 mov r2, r4 8001d1e: 2102 movs r1, #2 8001d20: 4630 mov r0, r6 8001d22: f7ff fa91 bl 8001248 // Configuration et Calibration de l'ADC1 sur 1 channel. ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 8001d26: 9501 str r5, [sp, #4] ADC_InitStructure.ADC_ScanConvMode = ENABLE; 8001d28: f88d 4008 strb.w r4, [sp, #8] ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; 8001d2c: f88d 4009 strb.w r4, [sp, #9] ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; 8001d30: f44f 2360 mov.w r3, #917504 ; 0xe0000 8001d34: 9303 str r3, [sp, #12] ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 8001d36: 9504 str r5, [sp, #16] ADC_InitStructure.ADC_NbrOfChannel = 1; 8001d38: f88d 4014 strb.w r4, [sp, #20] ADC_Init(ADC1, &ADC_InitStructure); 8001d3c: 4e1a ldr r6, [pc, #104] ; (8001da8 ) 8001d3e: a901 add r1, sp, #4 8001d40: 4630 mov r0, r6 8001d42: f7ff f927 bl 8000f94 /* ADC1 regular channel1 configuration */ ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_71Cycles5); 8001d46: 2306 movs r3, #6 8001d48: 4622 mov r2, r4 8001d4a: 4629 mov r1, r5 8001d4c: 4630 mov r0, r6 8001d4e: f7ff f973 bl 8001038 /* Start ADC1 Software Conversion */ ADC_Cmd(ADC1, ENABLE); 8001d52: 4621 mov r1, r4 8001d54: 4630 mov r0, r6 8001d56: f7ff f941 bl 8000fdc ADC_StartCalibration(ADC1); 8001d5a: 4630 mov r0, r6 8001d5c: f7ff f954 bl 8001008 /* Check the end of ADC1 calibration */ while(ADC_GetCalibrationStatus(ADC1)); 8001d60: 4811 ldr r0, [pc, #68] ; (8001da8 ) 8001d62: f7ff f956 bl 8001012 8001d66: 2800 cmp r0, #0 8001d68: d1fa bne.n 8001d60 ADC_SoftwareStartConvCmd(ADC1, ENABLE); 8001d6a: 2101 movs r1, #1 8001d6c: 480e ldr r0, [pc, #56] ; (8001da8 ) 8001d6e: f7ff f958 bl 8001022 /* Enable the ADC1 DMA Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn; 8001d72: 230b movs r3, #11 8001d74: f88d 3020 strb.w r3, [sp, #32] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; 8001d78: 2302 movs r3, #2 8001d7a: f88d 3021 strb.w r3, [sp, #33] ; 0x21 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 8001d7e: 2300 movs r3, #0 8001d80: f88d 3022 strb.w r3, [sp, #34] ; 0x22 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 8001d84: 2301 movs r3, #1 8001d86: f88d 3023 strb.w r3, [sp, #35] ; 0x23 NVIC_Init(&NVIC_InitStructure); 8001d8a: a808 add r0, sp, #32 8001d8c: f7ff f8ce bl 8000f2c } 8001d90: b00b add sp, #44 ; 0x2c 8001d92: bdf0 pop {r4, r5, r6, r7, pc} 8001d94: 40010800 .word 0x40010800 8001d98: 40010c00 .word 0x40010c00 8001d9c: 20000238 .word 0x20000238 8001da0: 4001244c .word 0x4001244c 8001da4: 20000264 .word 0x20000264 8001da8: 40012400 .word 0x40012400 08001dac : * @retval None * */ void batteryStartAcquisition(void) { 8001dac: b510 push {r4, lr} ADC_DMACmd(ADC1, ENABLE); 8001dae: 2101 movs r1, #1 8001db0: 480a ldr r0, [pc, #40] ; (8001ddc ) 8001db2: f7ff f91e bl 8000ff2 DMA_DeInit(DMA1_Channel1); 8001db6: 4c0a ldr r4, [pc, #40] ; (8001de0 ) 8001db8: 4620 mov r0, r4 8001dba: f7ff f985 bl 80010c8 DMA_Init(DMA1_Channel1, &DMA_BAT_InitStructure); 8001dbe: 4909 ldr r1, [pc, #36] ; (8001de4 ) 8001dc0: 4620 mov r0, r4 8001dc2: f7ff fa15 bl 80011f0 DMA_Cmd(DMA1_Channel1, ENABLE); 8001dc6: 2101 movs r1, #1 8001dc8: 4620 mov r0, r4 8001dca: f7ff fa30 bl 800122e DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE); 8001dce: 2201 movs r2, #1 8001dd0: 2102 movs r1, #2 8001dd2: 4620 mov r0, r4 8001dd4: f7ff fa38 bl 8001248 8001dd8: bd10 pop {r4, pc} 8001dda: bf00 nop 8001ddc: 40012400 .word 0x40012400 8001de0: 40020008 .word 0x40020008 8001de4: 20000238 .word 0x20000238 08001de8 : * @retval None * */ void batteryRefreshData(void) { 8001de8: b510 push {r4, lr} DMA_BAT_InitStructure.DMA_BufferSize = VOLTAGE_BUFFER_SIZE; 8001dea: 2240 movs r2, #64 ; 0x40 8001dec: 4b07 ldr r3, [pc, #28] ; (8001e0c ) 8001dee: 60da str r2, [r3, #12] ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_55Cycles5); 8001df0: 4c07 ldr r4, [pc, #28] ; (8001e10 ) 8001df2: 2305 movs r3, #5 8001df4: 2201 movs r2, #1 8001df6: 2104 movs r1, #4 8001df8: 4620 mov r0, r4 8001dfa: f7ff f91d bl 8001038 ADC_Cmd(ADC1, ENABLE); 8001dfe: 2101 movs r1, #1 8001e00: 4620 mov r0, r4 8001e02: f7ff f8eb bl 8000fdc batteryStartAcquisition(); 8001e06: f7ff ffd1 bl 8001dac 8001e0a: bd10 pop {r4, pc} 8001e0c: 20000238 .word 0x20000238 8001e10: 40012400 .word 0x40012400 08001e14 : * @brief Appelé de manière régulière pour mettre à jour le niveau batterie * * @param None * @retval None */ void batteryManagement(void) { 8001e14: b508 push {r3, lr} int k; if(Dumber.acquisition==VOLTAGE && Dumber.BatterieChecking==TRUE) { 8001e16: 4b42 ldr r3, [pc, #264] ; (8001f20 ) 8001e18: 7d1b ldrb r3, [r3, #20] 8001e1a: 2b62 cmp r3, #98 ; 0x62 8001e1c: d000 beq.n 8001e20 8001e1e: bd08 pop {r3, pc} 8001e20: 4b3f ldr r3, [pc, #252] ; (8001f20 ) 8001e22: 799b ldrb r3, [r3, #6] 8001e24: 2b28 cmp r3, #40 ; 0x28 8001e26: d1fa bne.n 8001e1e vbatLowerVal = 0xFFF; 8001e28: f640 72ff movw r2, #4095 ; 0xfff 8001e2c: 4b3d ldr r3, [pc, #244] ; (8001f24 ) 8001e2e: 801a strh r2, [r3, #0] vbatHighVal = 0; 8001e30: 2200 movs r2, #0 8001e32: 4b3d ldr r3, [pc, #244] ; (8001f28 ) 8001e34: 801a strh r2, [r3, #0] for(k=0; k 8001e38: 3201 adds r2, #1 8001e3a: 2a3f cmp r2, #63 ; 0x3f 8001e3c: dc13 bgt.n 8001e66 { meanVoltage+=ADCConvertedValue[k]; 8001e3e: 4b3b ldr r3, [pc, #236] ; (8001f2c ) 8001e40: f833 3012 ldrh.w r3, [r3, r2, lsl #1] 8001e44: 483a ldr r0, [pc, #232] ; (8001f30 ) 8001e46: 6801 ldr r1, [r0, #0] 8001e48: 4419 add r1, r3 8001e4a: 6001 str r1, [r0, #0] if (vbatLowerVal> ADCConvertedValue[k]) vbatLowerVal = ADCConvertedValue[k]; 8001e4c: 4935 ldr r1, [pc, #212] ; (8001f24 ) 8001e4e: 8809 ldrh r1, [r1, #0] 8001e50: 428b cmp r3, r1 8001e52: d201 bcs.n 8001e58 8001e54: 4933 ldr r1, [pc, #204] ; (8001f24 ) 8001e56: 800b strh r3, [r1, #0] if (vbatHighVal< ADCConvertedValue[k]) vbatHighVal = ADCConvertedValue[k]; 8001e58: 4933 ldr r1, [pc, #204] ; (8001f28 ) 8001e5a: 8809 ldrh r1, [r1, #0] 8001e5c: 428b cmp r3, r1 8001e5e: d9eb bls.n 8001e38 8001e60: 4931 ldr r1, [pc, #196] ; (8001f28 ) 8001e62: 800b strh r3, [r1, #0] 8001e64: e7e8 b.n 8001e38 } vbatDiff = vbatHighVal - vbatLowerVal; 8001e66: 4b30 ldr r3, [pc, #192] ; (8001f28 ) 8001e68: 881b ldrh r3, [r3, #0] 8001e6a: 4a2e ldr r2, [pc, #184] ; (8001f24 ) 8001e6c: 8812 ldrh r2, [r2, #0] 8001e6e: 1a9b subs r3, r3, r2 8001e70: 4a30 ldr r2, [pc, #192] ; (8001f34 ) 8001e72: 8013 strh r3, [r2, #0] meanVoltage= meanVoltage/VOLTAGE_BUFFER_SIZE; 8001e74: 4a2e ldr r2, [pc, #184] ; (8001f30 ) 8001e76: 6813 ldr r3, [r2, #0] 8001e78: 099b lsrs r3, r3, #6 8001e7a: 6013 str r3, [r2, #0] mesureVoltage = meanVoltage; 8001e7c: 4a2e ldr r2, [pc, #184] ; (8001f38 ) 8001e7e: 6013 str r3, [r2, #0] Dumber.BatteryPercentage = mesureVoltage; 8001e80: b29b uxth r3, r3 8001e82: 4a27 ldr r2, [pc, #156] ; (8001f20 ) 8001e84: 8013 strh r3, [r2, #0] Dumber.acquisition=FALSE; 8001e86: 2132 movs r1, #50 ; 0x32 8001e88: 7511 strb r1, [r2, #20] if(Dumber.BatteryPercentage >= VBAT_SEUIL_LOW) 8001e8a: f640 0277 movw r2, #2167 ; 0x877 8001e8e: 4293 cmp r3, r2 8001e90: d91b bls.n 8001eca { cptMesureHigh++; 8001e92: 4a2a ldr r2, [pc, #168] ; (8001f3c ) 8001e94: 7813 ldrb r3, [r2, #0] 8001e96: 3301 adds r3, #1 8001e98: b2db uxtb r3, r3 8001e9a: 7013 strb r3, [r2, #0] if(cptMesureHigh >= COMPTEUR_SEUIL_HIGH) 8001e9c: 2b07 cmp r3, #7 8001e9e: d9be bls.n 8001e1e { if(Dumber.StateSystem == STATE_LOW) 8001ea0: 4b1f ldr r3, [pc, #124] ; (8001f20 ) 8001ea2: 791b ldrb r3, [r3, #4] 8001ea4: 2b02 cmp r3, #2 8001ea6: d00c beq.n 8001ec2 systemChangeState(STATE_RUN); Dumber.stateBattery = 2; 8001ea8: 2202 movs r2, #2 8001eaa: 4b1d ldr r3, [pc, #116] ; (8001f20 ) 8001eac: 755a strb r2, [r3, #21] cptMesureHigh=0; 8001eae: 2300 movs r3, #0 8001eb0: 4a22 ldr r2, [pc, #136] ; (8001f3c ) 8001eb2: 7013 strb r3, [r2, #0] cptMesureLow=0; 8001eb4: 4a22 ldr r2, [pc, #136] ; (8001f40 ) 8001eb6: 7013 strb r3, [r2, #0] cptMesureDisable=0; 8001eb8: 4a22 ldr r2, [pc, #136] ; (8001f44 ) 8001eba: 7013 strb r3, [r2, #0] cptMesureEmergencyHalt=0; 8001ebc: 4a22 ldr r2, [pc, #136] ; (8001f48 ) 8001ebe: 6013 str r3, [r2, #0] 8001ec0: bd08 pop {r3, pc} systemChangeState(STATE_RUN); 8001ec2: 2001 movs r0, #1 8001ec4: f000 ff9c bl 8002e00 8001ec8: e7ee b.n 8001ea8 } } else if (Dumber.BatteryPercentage < VBAT_SEUIL_LOW && Dumber.BatteryPercentage >= VBAT_SEUIL_DISABLE) 8001eca: f2a3 73ca subw r3, r3, #1994 ; 0x7ca 8001ece: b29b uxth r3, r3 8001ed0: 2bad cmp r3, #173 ; 0xad 8001ed2: d819 bhi.n 8001f08 { cptMesureLow++; 8001ed4: 4a1a ldr r2, [pc, #104] ; (8001f40 ) 8001ed6: 7813 ldrb r3, [r2, #0] 8001ed8: 3301 adds r3, #1 8001eda: b2db uxtb r3, r3 8001edc: 7013 strb r3, [r2, #0] if(cptMesureLow >= COMPTEUR_SEUIL_LOW) 8001ede: 2b07 cmp r3, #7 8001ee0: d99d bls.n 8001e1e { if(Dumber.StateSystem == STATE_RUN) 8001ee2: 4b0f ldr r3, [pc, #60] ; (8001f20 ) 8001ee4: 791b ldrb r3, [r3, #4] 8001ee6: 2b01 cmp r3, #1 8001ee8: d00a beq.n 8001f00 systemChangeState(STATE_LOW); Dumber.stateBattery =1; 8001eea: 2201 movs r2, #1 8001eec: 4b0c ldr r3, [pc, #48] ; (8001f20 ) 8001eee: 755a strb r2, [r3, #21] cptMesureHigh=0; 8001ef0: 2300 movs r3, #0 8001ef2: 4a12 ldr r2, [pc, #72] ; (8001f3c ) 8001ef4: 7013 strb r3, [r2, #0] cptMesureLow=0; 8001ef6: 4a12 ldr r2, [pc, #72] ; (8001f40 ) 8001ef8: 7013 strb r3, [r2, #0] cptMesureDisable=0; 8001efa: 4a12 ldr r2, [pc, #72] ; (8001f44 ) 8001efc: 7013 strb r3, [r2, #0] 8001efe: bd08 pop {r3, pc} systemChangeState(STATE_LOW); 8001f00: 2002 movs r0, #2 8001f02: f000 ff7d bl 8002e00 8001f06: e7f0 b.n 8001eea } } else // Dumber.BatteryPercentage < VBAT_SEUIL_DISABLE { cptMesureDisable++; 8001f08: 4a0e ldr r2, [pc, #56] ; (8001f44 ) 8001f0a: 7813 ldrb r3, [r2, #0] 8001f0c: 3301 adds r3, #1 8001f0e: b2db uxtb r3, r3 8001f10: 7013 strb r3, [r2, #0] if(cptMesureDisable >= COMPTEUR_SEUIL_DISABLE) 8001f12: 2b07 cmp r3, #7 8001f14: d983 bls.n 8001e1e { systemChangeState(STATE_DISABLE); 8001f16: 2003 movs r0, #3 8001f18: f000 ff72 bl 8002e00 } } } } 8001f1c: e77f b.n 8001e1e 8001f1e: bf00 nop 8001f20: 20000330 .word 0x20000330 8001f24: 200002ec .word 0x200002ec 8001f28: 200002e4 .word 0x200002e4 8001f2c: 20000264 .word 0x20000264 8001f30: 200002f0 .word 0x200002f0 8001f34: 200002f4 .word 0x200002f4 8001f38: 200002e8 .word 0x200002e8 8001f3c: 20000210 .word 0x20000210 8001f40: 20000211 .word 0x20000211 8001f44: 20000208 .word 0x20000208 8001f48: 2000020c .word 0x2000020c 08001f4c : * @param None * @retval None * */ void DMA1_Channel1_IRQHandler(void) { 8001f4c: b508 push {r3, lr} //Test on DMA1 Channel1 Transfer Complete interrupt if (DMA_GetITStatus(DMA1_IT_TC1)) 8001f4e: 2002 movs r0, #2 8001f50: f7ff f996 bl 8001280 8001f54: b900 cbnz r0, 8001f58 8001f56: bd08 pop {r3, pc} { Dumber.BatterieChecking=TRUE; 8001f58: 2228 movs r2, #40 ; 0x28 8001f5a: 4b03 ldr r3, [pc, #12] ; (8001f68 ) 8001f5c: 719a strb r2, [r3, #6] //Clear DMA1 Channel1 Half Transfer, Transfer Complete and Global interrupt pending bits DMA_ClearITPendingBit(DMA1_IT_GL1); 8001f5e: 2001 movs r0, #1 8001f60: f7ff f9a0 bl 80012a4 } } 8001f64: e7f7 b.n 8001f56 8001f66: bf00 nop 8001f68: 20000330 .word 0x20000330 08001f6c : * @param None * @retval None * */ void EXTI15_10_IRQHandler(void) { 8001f6c: b508 push {r3, lr} systemShutDown(); 8001f6e: f000 ff3d bl 8002dec 8001f72: e7fe b.n 8001f72 08001f74 : * @retval 0 ou 1 * */ void cmdAddChecksum(void) { uint16_t j; unsigned char checksum=0; 8001f74: 2100 movs r1, #0 for (j = 0; sendString[j] != '\r'; j++) 8001f76: 460b mov r3, r1 8001f78: e002 b.n 8001f80 checksum ^= sendString[j]; 8001f7a: 4051 eors r1, r2 for (j = 0; sendString[j] != '\r'; j++) 8001f7c: 3301 adds r3, #1 8001f7e: b29b uxth r3, r3 8001f80: 4618 mov r0, r3 8001f82: 4a07 ldr r2, [pc, #28] ; (8001fa0 ) 8001f84: 5cd2 ldrb r2, [r2, r3] 8001f86: 2a0d cmp r2, #13 8001f88: d1f7 bne.n 8001f7a if (checksum == '\r') 8001f8a: 290d cmp r1, #13 8001f8c: d005 beq.n 8001f9a checksum++; sendString[j] = checksum; 8001f8e: 4b04 ldr r3, [pc, #16] ; (8001fa0 ) 8001f90: 5419 strb r1, [r3, r0] sendString[j + 1] = '\r'; 8001f92: 3001 adds r0, #1 8001f94: 220d movs r2, #13 8001f96: 541a strb r2, [r3, r0] 8001f98: 4770 bx lr checksum++; 8001f9a: 3101 adds r1, #1 8001f9c: b2c9 uxtb r1, r1 8001f9e: e7f6 b.n 8001f8e 8001fa0: 20000370 .word 0x20000370 08001fa4 : * sinon il retournera 1 sans faire de modification. * @param None * @retval 0 ou 1 * */ char cmdVerifyChecksum(void) { 8001fa4: b538 push {r3, r4, r5, lr} uint16_t j; uint16_t length; unsigned char checksum=0; length = strlen(receiptString); 8001fa6: 4811 ldr r0, [pc, #68] ; (8001fec ) 8001fa8: f7fe f8d2 bl 8000150 unsigned char checksum=0; 8001fac: 2200 movs r2, #0 for (j = 0; j < length - 2; j++) { 8001fae: 4613 mov r3, r2 8001fb0: e004 b.n 8001fbc checksum ^= receiptString[j]; 8001fb2: 490e ldr r1, [pc, #56] ; (8001fec ) 8001fb4: 5cc9 ldrb r1, [r1, r3] 8001fb6: 404a eors r2, r1 for (j = 0; j < length - 2; j++) { 8001fb8: 3301 adds r3, #1 8001fba: b29b uxth r3, r3 8001fbc: 461d mov r5, r3 8001fbe: b281 uxth r1, r0 8001fc0: 1e8c subs r4, r1, #2 8001fc2: 42a3 cmp r3, r4 8001fc4: dbf5 blt.n 8001fb2 } if (checksum == '\r') 8001fc6: 2a0d cmp r2, #13 8001fc8: d005 beq.n 8001fd6 checksum++; if (receiptString[j] == checksum) { 8001fca: 4b08 ldr r3, [pc, #32] ; (8001fec ) 8001fcc: 5d5b ldrb r3, [r3, r5] 8001fce: 429a cmp r2, r3 8001fd0: d004 beq.n 8001fdc receiptString[length - 1] = 0; receiptString[length] = 0; return 0; } else return 1; 8001fd2: 2001 movs r0, #1 } 8001fd4: bd38 pop {r3, r4, r5, pc} checksum++; 8001fd6: 3201 adds r2, #1 8001fd8: b2d2 uxtb r2, r2 8001fda: e7f6 b.n 8001fca receiptString[length - 2] = 13; 8001fdc: 4b03 ldr r3, [pc, #12] ; (8001fec ) 8001fde: 220d movs r2, #13 8001fe0: 551a strb r2, [r3, r4] receiptString[length - 1] = 0; 8001fe2: 1e4a subs r2, r1, #1 8001fe4: 2000 movs r0, #0 8001fe6: 5498 strb r0, [r3, r2] receiptString[length] = 0; 8001fe8: 5458 strb r0, [r3, r1] return 0; 8001fea: bd38 pop {r3, r4, r5, pc} 8001fec: 2000034c .word 0x2000034c 08001ff0 : * @param None * @retval None */ void cmdPingAction(void) { if (receiptString[1] == '\r') 8001ff0: 4b08 ldr r3, [pc, #32] ; (8002014 ) 8001ff2: 785b ldrb r3, [r3, #1] 8001ff4: 2b0d cmp r3, #13 8001ff6: d006 beq.n 8002006 strcpy(sendString, OK_ANS); else strcpy(sendString, ERR_ANS); 8001ff8: 4b07 ldr r3, [pc, #28] ; (8002018 ) 8001ffa: 4a08 ldr r2, [pc, #32] ; (800201c ) 8001ffc: 8811 ldrh r1, [r2, #0] 8001ffe: 7892 ldrb r2, [r2, #2] 8002000: 8019 strh r1, [r3, #0] 8002002: 709a strb r2, [r3, #2] 8002004: 4770 bx lr strcpy(sendString, OK_ANS); 8002006: 4b04 ldr r3, [pc, #16] ; (8002018 ) 8002008: 4a05 ldr r2, [pc, #20] ; (8002020 ) 800200a: 8811 ldrh r1, [r2, #0] 800200c: 7892 ldrb r2, [r2, #2] 800200e: 8019 strh r1, [r3, #0] 8002010: 709a strb r2, [r3, #2] 8002012: 4770 bx lr 8002014: 2000034c .word 0x2000034c 8002018: 20000370 .word 0x20000370 800201c: 08004098 .word 0x08004098 8002020: 08004094 .word 0x08004094 08002024 : * Retourne OK_ANS si success dans sendString. Sinon return ERR_ANS. * * @param None * @retval None */ void cmdResetAction(void) { 8002024: b508 push {r3, lr} systemChangeState(STATE_IDLE); 8002026: 2000 movs r0, #0 8002028: f000 feea bl 8002e00 strcpy(sendString, OK_ANS); 800202c: 4b03 ldr r3, [pc, #12] ; (800203c ) 800202e: 4a04 ldr r2, [pc, #16] ; (8002040 ) 8002030: 8811 ldrh r1, [r2, #0] 8002032: 7892 ldrb r2, [r2, #2] 8002034: 8019 strh r1, [r3, #0] 8002036: 709a strb r2, [r3, #2] 8002038: bd08 pop {r3, pc} 800203a: bf00 nop 800203c: 20000370 .word 0x20000370 8002040: 08004094 .word 0x08004094 08002044 : * Retourne la version du soft dans sendString. * @param None * @retval None */ void cmdVersionAction(void) { if (receiptString[1] == '\r') 8002044: 4b0a ldr r3, [pc, #40] ; (8002070 ) 8002046: 785b ldrb r3, [r3, #1] 8002048: 2b0d cmp r3, #13 800204a: d006 beq.n 800205a strcpy(sendString, VERSION); else strcpy(sendString, ERR_ANS); 800204c: 4b09 ldr r3, [pc, #36] ; (8002074 ) 800204e: 4a0a ldr r2, [pc, #40] ; (8002078 ) 8002050: 8811 ldrh r1, [r2, #0] 8002052: 7892 ldrb r2, [r2, #2] 8002054: 8019 strh r1, [r3, #0] 8002056: 709a strb r2, [r3, #2] } 8002058: 4770 bx lr void cmdVersionAction(void) { 800205a: b410 push {r4} strcpy(sendString, VERSION); 800205c: 4c05 ldr r4, [pc, #20] ; (8002074 ) 800205e: 4b07 ldr r3, [pc, #28] ; (800207c ) 8002060: cb07 ldmia r3!, {r0, r1, r2} 8002062: 6020 str r0, [r4, #0] 8002064: 6061 str r1, [r4, #4] 8002066: 60a2 str r2, [r4, #8] 8002068: 781b ldrb r3, [r3, #0] 800206a: 7323 strb r3, [r4, #12] } 800206c: bc10 pop {r4} 800206e: 4770 bx lr 8002070: 2000034c .word 0x2000034c 8002074: 20000370 .word 0x20000370 8002078: 08004098 .word 0x08004098 800207c: 080040a4 .word 0x080040a4 08002080 : * * @param None * @retval None */ void cmdBusyStateAction(void) { if ((Dumber.StateSystem == STATE_RUN) || (Dumber.StateSystem == STATE_LOW)) { 8002080: 4b0f ldr r3, [pc, #60] ; (80020c0 ) 8002082: 791b ldrb r3, [r3, #4] 8002084: 3b01 subs r3, #1 8002086: b2db uxtb r3, r3 8002088: 2b01 cmp r3, #1 800208a: d906 bls.n 800209a if (Dumber.busyState == TRUE) strcpy(sendString, "1\r"); else strcpy(sendString, "0\r"); } else { strcpy(sendString, ERR_ANS); 800208c: 4b0d ldr r3, [pc, #52] ; (80020c4 ) 800208e: 4a0e ldr r2, [pc, #56] ; (80020c8 ) 8002090: 8811 ldrh r1, [r2, #0] 8002092: 7892 ldrb r2, [r2, #2] 8002094: 8019 strh r1, [r3, #0] 8002096: 709a strb r2, [r3, #2] 8002098: 4770 bx lr if (Dumber.busyState == TRUE) 800209a: 4b09 ldr r3, [pc, #36] ; (80020c0 ) 800209c: 7bdb ldrb r3, [r3, #15] 800209e: 2b28 cmp r3, #40 ; 0x28 80020a0: d006 beq.n 80020b0 strcpy(sendString, "0\r"); 80020a2: 4b08 ldr r3, [pc, #32] ; (80020c4 ) 80020a4: 4a09 ldr r2, [pc, #36] ; (80020cc ) 80020a6: 8811 ldrh r1, [r2, #0] 80020a8: 7892 ldrb r2, [r2, #2] 80020aa: 8019 strh r1, [r3, #0] 80020ac: 709a strb r2, [r3, #2] 80020ae: 4770 bx lr strcpy(sendString, "1\r"); 80020b0: 4b04 ldr r3, [pc, #16] ; (80020c4 ) 80020b2: 4a07 ldr r2, [pc, #28] ; (80020d0 ) 80020b4: 8811 ldrh r1, [r2, #0] 80020b6: 7892 ldrb r2, [r2, #2] 80020b8: 8019 strh r1, [r3, #0] 80020ba: 709a strb r2, [r3, #2] 80020bc: 4770 bx lr 80020be: bf00 nop 80020c0: 20000330 .word 0x20000330 80020c4: 20000370 .word 0x20000370 80020c8: 08004098 .word 0x08004098 80020cc: 08004064 .word 0x08004064 80020d0: 08004060 .word 0x08004060 080020d4 : * @brief Effectue une remise à zéro du watchdog. * * @param None * @retval None */ void cmdResetWatchdogAction(void) { 80020d4: b508 push {r3, lr} if (systemResetWatchdog()!=0) { // Réussite 80020d6: f000 ff03 bl 8002ee0 80020da: b930 cbnz r0, 80020ea strcpy(sendString, OK_ANS); } else strcpy(sendString, ERR_ANS); 80020dc: 4b06 ldr r3, [pc, #24] ; (80020f8 ) 80020de: 4a07 ldr r2, [pc, #28] ; (80020fc ) 80020e0: 8811 ldrh r1, [r2, #0] 80020e2: 7892 ldrb r2, [r2, #2] 80020e4: 8019 strh r1, [r3, #0] 80020e6: 709a strb r2, [r3, #2] 80020e8: bd08 pop {r3, pc} strcpy(sendString, OK_ANS); 80020ea: 4b03 ldr r3, [pc, #12] ; (80020f8 ) 80020ec: 4a04 ldr r2, [pc, #16] ; (8002100 ) 80020ee: 8811 ldrh r1, [r2, #0] 80020f0: 7892 ldrb r2, [r2, #2] 80020f2: 8019 strh r1, [r3, #0] 80020f4: 709a strb r2, [r3, #2] 80020f6: bd08 pop {r3, pc} 80020f8: 20000370 .word 0x20000370 80020fc: 08004098 .word 0x08004098 8002100: 08004094 .word 0x08004094 08002104 : * Qu'il faut remettre à zero entre 950ms et 1050ms. * * @param None * @retval None */ void cmdStartWithWatchdogAction(void) { 8002104: b508 push {r3, lr} if (Dumber.StateSystem == STATE_IDLE && receiptString[1] == '\r') { 8002106: 4b0d ldr r3, [pc, #52] ; (800213c ) 8002108: 791b ldrb r3, [r3, #4] 800210a: b91b cbnz r3, 8002114 800210c: 4b0c ldr r3, [pc, #48] ; (8002140 ) 800210e: 785b ldrb r3, [r3, #1] 8002110: 2b0d cmp r3, #13 8002112: d006 beq.n 8002122 Dumber.WatchDogStartEnable = TRUE; systemChangeState(STATE_RUN); strcpy(sendString, OK_ANS); } else strcpy(sendString, ERR_ANS); 8002114: 4b0b ldr r3, [pc, #44] ; (8002144 ) 8002116: 4a0c ldr r2, [pc, #48] ; (8002148 ) 8002118: 8811 ldrh r1, [r2, #0] 800211a: 7892 ldrb r2, [r2, #2] 800211c: 8019 strh r1, [r3, #0] 800211e: 709a strb r2, [r3, #2] 8002120: bd08 pop {r3, pc} Dumber.WatchDogStartEnable = TRUE; 8002122: 2228 movs r2, #40 ; 0x28 8002124: 4b05 ldr r3, [pc, #20] ; (800213c ) 8002126: 729a strb r2, [r3, #10] systemChangeState(STATE_RUN); 8002128: 2001 movs r0, #1 800212a: f000 fe69 bl 8002e00 strcpy(sendString, OK_ANS); 800212e: 4b05 ldr r3, [pc, #20] ; (8002144 ) 8002130: 4a06 ldr r2, [pc, #24] ; (800214c ) 8002132: 8811 ldrh r1, [r2, #0] 8002134: 7892 ldrb r2, [r2, #2] 8002136: 8019 strh r1, [r3, #0] 8002138: 709a strb r2, [r3, #2] 800213a: bd08 pop {r3, pc} 800213c: 20000330 .word 0x20000330 8002140: 2000034c .word 0x2000034c 8002144: 20000370 .word 0x20000370 8002148: 08004098 .word 0x08004098 800214c: 08004094 .word 0x08004094 08002150 : * Necessite que dumby soit en mode IDLE au prealable. * * @param None * @retval None */ void cmdStartWithoutWatchdogAction(void) { 8002150: b508 push {r3, lr} if (Dumber.StateSystem == STATE_IDLE && receiptString[1] == '\r') { 8002152: 4b0d ldr r3, [pc, #52] ; (8002188 ) 8002154: 791b ldrb r3, [r3, #4] 8002156: b91b cbnz r3, 8002160 8002158: 4b0c ldr r3, [pc, #48] ; (800218c ) 800215a: 785b ldrb r3, [r3, #1] 800215c: 2b0d cmp r3, #13 800215e: d006 beq.n 800216e Dumber.WatchDogStartEnable = FALSE; systemChangeState(STATE_RUN); strcpy(sendString, OK_ANS); } else strcpy(sendString, ERR_ANS); 8002160: 4b0b ldr r3, [pc, #44] ; (8002190 ) 8002162: 4a0c ldr r2, [pc, #48] ; (8002194 ) 8002164: 8811 ldrh r1, [r2, #0] 8002166: 7892 ldrb r2, [r2, #2] 8002168: 8019 strh r1, [r3, #0] 800216a: 709a strb r2, [r3, #2] 800216c: bd08 pop {r3, pc} Dumber.WatchDogStartEnable = FALSE; 800216e: 2232 movs r2, #50 ; 0x32 8002170: 4b05 ldr r3, [pc, #20] ; (8002188 ) 8002172: 729a strb r2, [r3, #10] systemChangeState(STATE_RUN); 8002174: 2001 movs r0, #1 8002176: f000 fe43 bl 8002e00 strcpy(sendString, OK_ANS); 800217a: 4b05 ldr r3, [pc, #20] ; (8002190 ) 800217c: 4a06 ldr r2, [pc, #24] ; (8002198 ) 800217e: 8811 ldrh r1, [r2, #0] 8002180: 7892 ldrb r2, [r2, #2] 8002182: 8019 strh r1, [r3, #0] 8002184: 709a strb r2, [r3, #2] 8002186: bd08 pop {r3, pc} 8002188: 20000330 .word 0x20000330 800218c: 2000034c .word 0x2000034c 8002190: 20000370 .word 0x20000370 8002194: 08004098 .word 0x08004098 8002198: 08004094 .word 0x08004094 0800219c : * * @param NSTART_WITH_WDone * @retval None */ void cmdMoveAction(void) { if (Dumber.StateSystem == STATE_RUN || Dumber.StateSystem == STATE_LOW) { 800219c: 4b1e ldr r3, [pc, #120] ; (8002218 ) 800219e: 791b ldrb r3, [r3, #4] 80021a0: 3b01 subs r3, #1 80021a2: b2db uxtb r3, r3 80021a4: 2b01 cmp r3, #1 80021a6: d900 bls.n 80021aa 80021a8: 4770 bx lr void cmdMoveAction(void) { 80021aa: b500 push {lr} 80021ac: b085 sub sp, #20 int laps; uint16_t testReception = sscanf(receiptString, "M=%i\r", &laps); 80021ae: aa03 add r2, sp, #12 80021b0: 491a ldr r1, [pc, #104] ; (800221c ) 80021b2: 481b ldr r0, [pc, #108] ; (8002220 ) 80021b4: f001 f946 bl 8003444 80021b8: b280 uxth r0, r0 unsigned char mod = 0; tourPositionG = 0; 80021ba: 2300 movs r3, #0 80021bc: 4a19 ldr r2, [pc, #100] ; (8002224 ) 80021be: 8013 strh r3, [r2, #0] tourPositionD = 0; 80021c0: 4a19 ldr r2, [pc, #100] ; (8002228 ) 80021c2: 8013 strh r3, [r2, #0] if (testReception == 1) { 80021c4: 2801 cmp r0, #1 80021c6: d008 beq.n 80021da motorRegulation(mod, mod, (unsigned) laps, (unsigned) laps, COMMONSPEED, COMMONSPEED); strcpy(sendString, OK_ANS); } else strcpy(sendString, ERR_ANS); 80021c8: 4b18 ldr r3, [pc, #96] ; (800222c ) 80021ca: 4a19 ldr r2, [pc, #100] ; (8002230 ) 80021cc: 8811 ldrh r1, [r2, #0] 80021ce: 7892 ldrb r2, [r2, #2] 80021d0: 8019 strh r1, [r3, #0] 80021d2: 709a strb r2, [r3, #2] } } 80021d4: b005 add sp, #20 80021d6: f85d fb04 ldr.w pc, [sp], #4 Dumber.cpt_inactivity = 0; 80021da: 4b0f ldr r3, [pc, #60] ; (8002218 ) 80021dc: 2200 movs r2, #0 80021de: 611a str r2, [r3, #16] Dumber.busyState = TRUE; 80021e0: 2228 movs r2, #40 ; 0x28 80021e2: 73da strb r2, [r3, #15] if (laps < 0) { 80021e4: 9b03 ldr r3, [sp, #12] 80021e6: 2b00 cmp r3, #0 80021e8: db12 blt.n 8002210 mod = FORWARD; 80021ea: 200b movs r0, #11 laps = laps * 2; 80021ec: 9a03 ldr r2, [sp, #12] 80021ee: 0052 lsls r2, r2, #1 80021f0: 9203 str r2, [sp, #12] motorRegulation(mod, mod, (unsigned) laps, (unsigned) laps, 80021f2: b292 uxth r2, r2 80021f4: 2305 movs r3, #5 80021f6: 9301 str r3, [sp, #4] 80021f8: 9300 str r3, [sp, #0] 80021fa: 4613 mov r3, r2 80021fc: 4601 mov r1, r0 80021fe: f000 fba9 bl 8002954 strcpy(sendString, OK_ANS); 8002202: 4b0a ldr r3, [pc, #40] ; (800222c ) 8002204: 4a0b ldr r2, [pc, #44] ; (8002234 ) 8002206: 8811 ldrh r1, [r2, #0] 8002208: 7892 ldrb r2, [r2, #2] 800220a: 8019 strh r1, [r3, #0] 800220c: 709a strb r2, [r3, #2] 800220e: e7e1 b.n 80021d4 laps = laps * -1; 8002210: 425b negs r3, r3 8002212: 9303 str r3, [sp, #12] mod = REVERSE; 8002214: 200c movs r0, #12 8002216: e7e9 b.n 80021ec 8002218: 20000330 .word 0x20000330 800221c: 0800408c .word 0x0800408c 8002220: 2000034c .word 0x2000034c 8002224: 20000328 .word 0x20000328 8002228: 20000318 .word 0x20000318 800222c: 20000370 .word 0x20000370 8002230: 08004098 .word 0x08004098 8002234: 08004094 .word 0x08004094 08002238 : * * @param None * @retval None */ void cmdTurnAction(void) { if (Dumber.StateSystem == STATE_RUN || Dumber.StateSystem == STATE_LOW) { 8002238: 4b29 ldr r3, [pc, #164] ; (80022e0 ) 800223a: 791b ldrb r3, [r3, #4] 800223c: 3b01 subs r3, #1 800223e: b2db uxtb r3, r3 8002240: 2b01 cmp r3, #1 8002242: d900 bls.n 8002246 8002244: 4770 bx lr void cmdTurnAction(void) { 8002246: b500 push {lr} 8002248: b085 sub sp, #20 int degree; uint16_t testReception = sscanf(receiptString, "T=%i\r", °ree); 800224a: aa03 add r2, sp, #12 800224c: 4925 ldr r1, [pc, #148] ; (80022e4 ) 800224e: 4826 ldr r0, [pc, #152] ; (80022e8 ) 8002250: f001 f8f8 bl 8003444 8002254: b280 uxth r0, r0 tourPositionG = 0; 8002256: 2300 movs r3, #0 8002258: 4a24 ldr r2, [pc, #144] ; (80022ec ) 800225a: 8013 strh r3, [r2, #0] tourPositionD = 0; 800225c: 4a24 ldr r2, [pc, #144] ; (80022f0 ) 800225e: 8013 strh r3, [r2, #0] if (testReception == 1) { 8002260: 2801 cmp r0, #1 8002262: d008 beq.n 8002276 motorRegulation(REVERSE, FORWARD, (unsigned) degree, (unsigned) degree, LOWSPEED, LOWSPEED); } strcpy(sendString, OK_ANS); } else strcpy(sendString, ERR_ANS); 8002264: 4b23 ldr r3, [pc, #140] ; (80022f4 ) 8002266: 4a24 ldr r2, [pc, #144] ; (80022f8 ) 8002268: 8811 ldrh r1, [r2, #0] 800226a: 7892 ldrb r2, [r2, #2] 800226c: 8019 strh r1, [r3, #0] 800226e: 709a strb r2, [r3, #2] } } 8002270: b005 add sp, #20 8002272: f85d fb04 ldr.w pc, [sp], #4 degree = degree * 1.40; 8002276: 9803 ldr r0, [sp, #12] 8002278: f7fe f8c4 bl 8000404 <__aeabi_i2d> 800227c: a316 add r3, pc, #88 ; (adr r3, 80022d8 ) 800227e: e9d3 2300 ldrd r2, r3, [r3] 8002282: f7fe f925 bl 80004d0 <__aeabi_dmul> 8002286: f7fe fb35 bl 80008f4 <__aeabi_d2iz> 800228a: 9003 str r0, [sp, #12] Dumber.cpt_inactivity = 0; 800228c: 4b14 ldr r3, [pc, #80] ; (80022e0 ) 800228e: 2200 movs r2, #0 8002290: 611a str r2, [r3, #16] Dumber.busyState = TRUE; 8002292: 2228 movs r2, #40 ; 0x28 8002294: 73da strb r2, [r3, #15] if (degree < 0) { 8002296: 2800 cmp r0, #0 8002298: db0f blt.n 80022ba motorRegulation(REVERSE, FORWARD, (unsigned) degree, 800229a: b282 uxth r2, r0 800229c: 2302 movs r3, #2 800229e: 9301 str r3, [sp, #4] 80022a0: 9300 str r3, [sp, #0] 80022a2: 4613 mov r3, r2 80022a4: 210b movs r1, #11 80022a6: 200c movs r0, #12 80022a8: f000 fb54 bl 8002954 strcpy(sendString, OK_ANS); 80022ac: 4b11 ldr r3, [pc, #68] ; (80022f4 ) 80022ae: 4a13 ldr r2, [pc, #76] ; (80022fc ) 80022b0: 8811 ldrh r1, [r2, #0] 80022b2: 7892 ldrb r2, [r2, #2] 80022b4: 8019 strh r1, [r3, #0] 80022b6: 709a strb r2, [r3, #2] 80022b8: e7da b.n 8002270 degree = degree * -1; 80022ba: 4242 negs r2, r0 80022bc: 9203 str r2, [sp, #12] motorRegulation(FORWARD, REVERSE, (unsigned) degree, 80022be: b292 uxth r2, r2 80022c0: 2302 movs r3, #2 80022c2: 9301 str r3, [sp, #4] 80022c4: 9300 str r3, [sp, #0] 80022c6: 4613 mov r3, r2 80022c8: 210c movs r1, #12 80022ca: 200b movs r0, #11 80022cc: f000 fb42 bl 8002954 80022d0: e7ec b.n 80022ac 80022d2: bf00 nop 80022d4: f3af 8000 nop.w 80022d8: 66666666 .word 0x66666666 80022dc: 3ff66666 .word 0x3ff66666 80022e0: 20000330 .word 0x20000330 80022e4: 0800409c .word 0x0800409c 80022e8: 2000034c .word 0x2000034c 80022ec: 20000328 .word 0x20000328 80022f0: 20000318 .word 0x20000318 80022f4: 20000370 .word 0x20000370 80022f8: 08004098 .word 0x08004098 80022fc: 08004094 .word 0x08004094 08002300 : * Lorsque la batterie est vide, la valeur retournée est 0. * * @param None * @retval None */ void cmdBatteryVoltageAction(void) { 8002300: b500 push {lr} 8002302: b083 sub sp, #12 char battery[2]; battery[0] = Dumber.stateBattery + '0'; 8002304: 4b07 ldr r3, [pc, #28] ; (8002324 ) 8002306: 7d5b ldrb r3, [r3, #21] 8002308: 3330 adds r3, #48 ; 0x30 800230a: f88d 3004 strb.w r3, [sp, #4] battery[1] = '\r'; 800230e: 230d movs r3, #13 8002310: f88d 3005 strb.w r3, [sp, #5] strcpy(sendString, battery); 8002314: a901 add r1, sp, #4 8002316: 4804 ldr r0, [pc, #16] ; (8002328 ) 8002318: f001 f8c0 bl 800349c } 800231c: b003 add sp, #12 800231e: f85d fb04 ldr.w pc, [sp], #4 8002322: bf00 nop 8002324: 20000330 .word 0x20000330 8002328: 20000370 .word 0x20000370 0800232c : * Re- Nombre de tour reel effectué. * * @param None * @retval None */ void cmdDebugAction(void) { 800232c: b508 push {r3, lr} uint8_t j; sprintf(sendString, "Th-D=%u G=%u\r", tourPositionD, tourPositionG); 800232e: 4b0d ldr r3, [pc, #52] ; (8002364 ) 8002330: 881b ldrh r3, [r3, #0] 8002332: 4a0d ldr r2, [pc, #52] ; (8002368 ) 8002334: 8812 ldrh r2, [r2, #0] 8002336: 490d ldr r1, [pc, #52] ; (800236c ) 8002338: 480d ldr r0, [pc, #52] ; (8002370 ) 800233a: f000 fef7 bl 800312c usartSendData(); 800233e: f000 ff7f bl 8003240 for (j = 0; j < 200; j++); 8002342: 2300 movs r3, #0 8002344: e001 b.n 800234a 8002346: 3301 adds r3, #1 8002348: b2db uxtb r3, r3 800234a: 2bc7 cmp r3, #199 ; 0xc7 800234c: d9fb bls.n 8002346 sprintf(sendString, "Re-D=%u G=%u\r", G_lapsRight, G_lapsLeft); 800234e: 4b09 ldr r3, [pc, #36] ; (8002374 ) 8002350: 881b ldrh r3, [r3, #0] 8002352: 4a09 ldr r2, [pc, #36] ; (8002378 ) 8002354: 8812 ldrh r2, [r2, #0] 8002356: 4909 ldr r1, [pc, #36] ; (800237c ) 8002358: 4805 ldr r0, [pc, #20] ; (8002370 ) 800235a: f000 fee7 bl 800312c usartSendData(); 800235e: f000 ff6f bl 8003240 8002362: bd08 pop {r3, pc} 8002364: 20000328 .word 0x20000328 8002368: 20000318 .word 0x20000318 800236c: 08004068 .word 0x08004068 8002370: 20000370 .word 0x20000370 8002374: 2000031e .word 0x2000031e 8002378: 2000032c .word 0x2000032c 800237c: 08004078 .word 0x08004078 08002380 : * @brief Eteint le robot * * @param None * @retval None */ void cmdPowerOffAction(void) { 8002380: b500 push {lr} 8002382: b083 sub sp, #12 volatile int i; systemChangeState(STATE_DISABLE); 8002384: 2003 movs r0, #3 8002386: f000 fd3b bl 8002e00 strcpy(sendString, OK_ANS); 800238a: 4b0c ldr r3, [pc, #48] ; (80023bc ) 800238c: 4a0c ldr r2, [pc, #48] ; (80023c0 ) 800238e: 8811 ldrh r1, [r2, #0] 8002390: 7892 ldrb r2, [r2, #2] 8002392: 8019 strh r1, [r3, #0] 8002394: 709a strb r2, [r3, #2] cmdAddChecksum(); 8002396: f7ff fded bl 8001f74 usartSendData(); 800239a: f000 ff51 bl 8003240 /* Attente d'un certain temps (100 ms), pour que la reponse parte */ for (i=0; i<100000; i++); 800239e: 2300 movs r3, #0 80023a0: 9301 str r3, [sp, #4] 80023a2: e002 b.n 80023aa 80023a4: 9b01 ldr r3, [sp, #4] 80023a6: 3301 adds r3, #1 80023a8: 9301 str r3, [sp, #4] 80023aa: 9a01 ldr r2, [sp, #4] 80023ac: 4b05 ldr r3, [pc, #20] ; (80023c4 ) 80023ae: 429a cmp r2, r3 80023b0: ddf8 ble.n 80023a4 systemShutDown(); // Ne ressort jamais de cette fonction 80023b2: f000 fd1b bl 8002dec } 80023b6: b003 add sp, #12 80023b8: f85d fb04 ldr.w pc, [sp], #4 80023bc: 20000370 .word 0x20000370 80023c0: 08004094 .word 0x08004094 80023c4: 0001869f .word 0x0001869f 080023c8 : void cmdManage(void) { 80023c8: b508 push {r3, lr} if (cmdVerifyChecksum() != 0) { 80023ca: f7ff fdeb bl 8001fa4 80023ce: bb08 cbnz r0, 8002414 if (Dumber.StateSystem==STATE_DISABLE) { // SI la batterie est trop faible, impossible d'accepter une commande sauf poweroff: on reste dans ce mode 80023d0: 4b32 ldr r3, [pc, #200] ; (800249c ) 80023d2: 791b ldrb r3, [r3, #4] 80023d4: 2b03 cmp r3, #3 80023d6: d027 beq.n 8002428 switch (receiptString[0]) { 80023d8: 4b31 ldr r3, [pc, #196] ; (80024a0 ) 80023da: 781b ldrb r3, [r3, #0] 80023dc: 3b4d subs r3, #77 ; 0x4d 80023de: 2b2d cmp r3, #45 ; 0x2d 80023e0: d854 bhi.n 800248c 80023e2: e8df f003 tbb [pc, r3] 80023e6: 5344 .short 0x5344 80023e8: 53535353 .word 0x53535353 80023ec: 3e534753 .word 0x3e534753 80023f0: 53535335 .word 0x53535335 80023f4: 53535353 .word 0x53535353 80023f8: 4a4d5353 .word 0x4a4d5353 80023fc: 53535353 .word 0x53535353 8002400: 53535353 .word 0x53535353 8002404: 53535353 .word 0x53535353 8002408: 32532f53 .word 0x32532f53 800240c: 3b415353 .word 0x3b415353 8002410: 50535338 .word 0x50535338 strcpy(sendString, UNKNOW_ANS); 8002414: 4b23 ldr r3, [pc, #140] ; (80024a4 ) 8002416: 4a24 ldr r2, [pc, #144] ; (80024a8 ) 8002418: 8811 ldrh r1, [r2, #0] 800241a: 7892 ldrb r2, [r2, #2] 800241c: 8019 strh r1, [r3, #0] 800241e: 709a strb r2, [r3, #2] Dumber.cpt_inactivity=0; // remise a zéro du compteur d'inativité 8002420: 2200 movs r2, #0 8002422: 4b1e ldr r3, [pc, #120] ; (800249c ) 8002424: 611a str r2, [r3, #16] 8002426: bd08 pop {r3, pc} if (receiptString[0]==PowerOffCMD) 8002428: 4b1d ldr r3, [pc, #116] ; (80024a0 ) 800242a: 781b ldrb r3, [r3, #0] 800242c: 2b7a cmp r3, #122 ; 0x7a 800242e: d006 beq.n 800243e strcpy(sendString, ERR_ANS); 8002430: 4b1c ldr r3, [pc, #112] ; (80024a4 ) 8002432: 4a1e ldr r2, [pc, #120] ; (80024ac ) 8002434: 8811 ldrh r1, [r2, #0] 8002436: 7892 ldrb r2, [r2, #2] 8002438: 8019 strh r1, [r3, #0] 800243a: 709a strb r2, [r3, #2] 800243c: e7f0 b.n 8002420 cmdPowerOffAction(); 800243e: f7ff ff9f bl 8002380 8002442: e7ed b.n 8002420 cmdPingAction(); 8002444: f7ff fdd4 bl 8001ff0 break; 8002448: e7ea b.n 8002420 cmdResetAction(); 800244a: f7ff fdeb bl 8002024 break; 800244e: e7e7 b.n 8002420 cmdStartWithWatchdogAction(); 8002450: f7ff fe58 bl 8002104 break; 8002454: e7e4 b.n 8002420 cmdResetWatchdogAction(); 8002456: f7ff fe3d bl 80020d4 break; 800245a: e7e1 b.n 8002420 cmdBatteryVoltageAction(); 800245c: f7ff ff50 bl 8002300 break; 8002460: e7de b.n 8002420 cmdVersionAction(); 8002462: f7ff fdef bl 8002044 break; 8002466: e7db b.n 8002420 cmdStartWithoutWatchdogAction(); 8002468: f7ff fe72 bl 8002150 break; 800246c: e7d8 b.n 8002420 cmdMoveAction(); 800246e: f7ff fe95 bl 800219c break; 8002472: e7d5 b.n 8002420 cmdTurnAction(); 8002474: f7ff fee0 bl 8002238 break; 8002478: e7d2 b.n 8002420 cmdBusyStateAction(); 800247a: f7ff fe01 bl 8002080 break; 800247e: e7cf b.n 8002420 cmdDebugAction(); 8002480: f7ff ff54 bl 800232c break; 8002484: e7cc b.n 8002420 cmdPowerOffAction(); 8002486: f7ff ff7b bl 8002380 break; 800248a: e7c9 b.n 8002420 strcpy(sendString, UNKNOW_ANS); 800248c: 4b05 ldr r3, [pc, #20] ; (80024a4 ) 800248e: 4a06 ldr r2, [pc, #24] ; (80024a8 ) 8002490: 8811 ldrh r1, [r2, #0] 8002492: 7892 ldrb r2, [r2, #2] 8002494: 8019 strh r1, [r3, #0] 8002496: 709a strb r2, [r3, #2] 8002498: e7c2 b.n 8002420 800249a: bf00 nop 800249c: 20000330 .word 0x20000330 80024a0: 2000034c .word 0x2000034c 80024a4: 20000370 .word 0x20000370 80024a8: 08004088 .word 0x08004088 80024ac: 08004098 .word 0x08004098 080024b0 : /** * @brief Configure le GPIO PB0 et PB1 afin de contrôler la led. * @param Aucun */ void ledConfigure(void) { 80024b0: b500 push {lr} 80024b2: b083 sub sp, #12 GPIO_InitTypeDef Init_Structure; // Configure les PIN B0 et B1 en output / alternate fonction Init_Structure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; 80024b4: 2303 movs r3, #3 80024b6: f8ad 3004 strh.w r3, [sp, #4] Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 80024ba: f88d 3006 strb.w r3, [sp, #6] Init_Structure.GPIO_Mode = GPIO_Mode_Out_PP; 80024be: 2310 movs r3, #16 80024c0: f88d 3007 strb.w r3, [sp, #7] GPIO_Init(GPIOB, &Init_Structure); 80024c4: a901 add r1, sp, #4 80024c6: 4806 ldr r0, [pc, #24] ; (80024e0 ) 80024c8: f7fe ff40 bl 800134c etatLED = 1; 80024cc: 2201 movs r2, #1 80024ce: 4b05 ldr r3, [pc, #20] ; (80024e4 ) 80024d0: 701a strb r2, [r3, #0] LEDON =0; 80024d2: 2200 movs r2, #0 80024d4: 4b04 ldr r3, [pc, #16] ; (80024e8 ) 80024d6: 701a strb r2, [r3, #0] } 80024d8: b003 add sp, #12 80024da: f85d fb04 ldr.w pc, [sp], #4 80024de: bf00 nop 80024e0: 40010c00 .word 0x40010c00 80024e4: 20000315 .word 0x20000315 80024e8: 20000314 .word 0x20000314 080024ec : /** * @brief Eteint les LED. * @param Aucun */ void ledOff(void) { 80024ec: b510 push {r4, lr} GPIO_ResetBits(GPIOB,GPIO_Pin_0); 80024ee: 4c05 ldr r4, [pc, #20] ; (8002504 ) 80024f0: 2101 movs r1, #1 80024f2: 4620 mov r0, r4 80024f4: f7fe ff7b bl 80013ee GPIO_ResetBits(GPIOB,GPIO_Pin_1); 80024f8: 2102 movs r1, #2 80024fa: 4620 mov r0, r4 80024fc: f7fe ff77 bl 80013ee 8002500: bd10 pop {r4, pc} 8002502: bf00 nop 8002504: 40010c00 .word 0x40010c00 08002508 : /** * @brief Allume une couleur de LED. * @param Aucun */ void ledOn(char color) { 8002508: b510 push {r4, lr} switch (color) 800250a: 2801 cmp r0, #1 800250c: d00f beq.n 800252e 800250e: b120 cbz r0, 800251a 8002510: 2802 cmp r0, #2 8002512: d016 beq.n 8002542 GPIO_SetBits(GPIOB, GPIO_Pin_1); GPIO_SetBits(GPIOB,GPIO_Pin_0); break; default: ledOff(); 8002514: f7ff ffea bl 80024ec 8002518: bd10 pop {r4, pc} GPIO_SetBits(GPIOB, GPIO_Pin_1); 800251a: 4c0f ldr r4, [pc, #60] ; (8002558 ) 800251c: 2102 movs r1, #2 800251e: 4620 mov r0, r4 8002520: f7fe ff63 bl 80013ea GPIO_ResetBits(GPIOB,GPIO_Pin_0); 8002524: 2101 movs r1, #1 8002526: 4620 mov r0, r4 8002528: f7fe ff61 bl 80013ee break; 800252c: bd10 pop {r4, pc} GPIO_ResetBits(GPIOB, GPIO_Pin_1); 800252e: 4c0a ldr r4, [pc, #40] ; (8002558 ) 8002530: 2102 movs r1, #2 8002532: 4620 mov r0, r4 8002534: f7fe ff5b bl 80013ee GPIO_SetBits(GPIOB,GPIO_Pin_0); 8002538: 2101 movs r1, #1 800253a: 4620 mov r0, r4 800253c: f7fe ff55 bl 80013ea break; 8002540: bd10 pop {r4, pc} GPIO_SetBits(GPIOB, GPIO_Pin_1); 8002542: 4c05 ldr r4, [pc, #20] ; (8002558 ) 8002544: 2102 movs r1, #2 8002546: 4620 mov r0, r4 8002548: f7fe ff4f bl 80013ea GPIO_SetBits(GPIOB,GPIO_Pin_0); 800254c: 2101 movs r1, #1 800254e: 4620 mov r0, r4 8002550: f7fe ff4b bl 80013ea break; 8002554: bd10 pop {r4, pc} 8002556: bf00 nop 8002558: 40010c00 .word 0x40010c00 0800255c : * @brief Gere l'etat du clignotement de la led en fonction de l'etat du système * Appelée toutes les 10 ms * @param state: état actuel du système * @param batteryState: état de la batterie */ void ledManagement(States state, char batteryState) { 800255c: b508 push {r3, lr} static char ledCounter=0; char color; if (batteryState>1) color=LED_GREEN; 800255e: 2901 cmp r1, #1 8002560: d907 bls.n 8002572 8002562: 2300 movs r3, #0 else color = LED_RED; switch (state) 8002564: 2804 cmp r0, #4 8002566: d82e bhi.n 80025c6 8002568: e8df f000 tbb [pc, r0] 800256c: 2d141405 .word 0x2d141405 8002570: 22 .byte 0x22 8002571: 00 .byte 0x00 else color = LED_RED; 8002572: 2301 movs r3, #1 8002574: e7f6 b.n 8002564 { case STATE_IDLE: if ((ledCounter<15) || ((ledCounter>=100) && (ledCounter<115))) ledOn(color); 8002576: 4a1e ldr r2, [pc, #120] ; (80025f0 ) 8002578: 7812 ldrb r2, [r2, #0] 800257a: 2a0e cmp r2, #14 800257c: d903 bls.n 8002586 800257e: 3a64 subs r2, #100 ; 0x64 8002580: b2d2 uxtb r2, r2 8002582: 2a0e cmp r2, #14 8002584: d803 bhi.n 800258e 8002586: 4618 mov r0, r3 8002588: f7ff ffbe bl 8002508 800258c: e005 b.n 800259a else ledOff(); 800258e: f7ff ffad bl 80024ec 8002592: e002 b.n 800259a break; case STATE_RUN: case STATE_LOW: ledOn(color); 8002594: 4618 mov r0, r3 8002596: f7ff ffb7 bl 8002508 default: if (ledCounter%10 ==0) ledOn(LED_RED); else ledOff(); } ledCounter++; 800259a: 4a15 ldr r2, [pc, #84] ; (80025f0 ) 800259c: 7813 ldrb r3, [r2, #0] 800259e: 3301 adds r3, #1 80025a0: b2db uxtb r3, r3 80025a2: 7013 strb r3, [r2, #0] if (ledCounter>200) ledCounter=0; 80025a4: 2bc8 cmp r3, #200 ; 0xc8 80025a6: d902 bls.n 80025ae 80025a8: 2200 movs r2, #0 80025aa: 4b11 ldr r3, [pc, #68] ; (80025f0 ) 80025ac: 701a strb r2, [r3, #0] 80025ae: bd08 pop {r3, pc} if (ledCounter<100) ledOn(LED_RED); 80025b0: 4b0f ldr r3, [pc, #60] ; (80025f0 ) 80025b2: 781b ldrb r3, [r3, #0] 80025b4: 2b63 cmp r3, #99 ; 0x63 80025b6: d803 bhi.n 80025c0 80025b8: 2001 movs r0, #1 80025ba: f7ff ffa5 bl 8002508 80025be: e7ec b.n 800259a else ledOff(); 80025c0: f7ff ff94 bl 80024ec 80025c4: e7e9 b.n 800259a if (ledCounter%10 ==0) ledOn(LED_RED); 80025c6: 4b0a ldr r3, [pc, #40] ; (80025f0 ) 80025c8: 781a ldrb r2, [r3, #0] 80025ca: 4b0a ldr r3, [pc, #40] ; (80025f4 ) 80025cc: fba3 1302 umull r1, r3, r3, r2 80025d0: 08db lsrs r3, r3, #3 80025d2: eb03 0383 add.w r3, r3, r3, lsl #2 80025d6: 0059 lsls r1, r3, #1 80025d8: 1a52 subs r2, r2, r1 80025da: f012 0fff tst.w r2, #255 ; 0xff 80025de: d103 bne.n 80025e8 80025e0: 2001 movs r0, #1 80025e2: f7ff ff91 bl 8002508 80025e6: e7d8 b.n 800259a else ledOff(); 80025e8: f7ff ff80 bl 80024ec 80025ec: e7d5 b.n 800259a 80025ee: bf00 nop 80025f0: 20000212 .word 0x20000212 80025f4: cccccccd .word 0xcccccccd 080025f8
: * @brief Initialise les horloges du micro et de ses périphériques. * @param None * @retval None */ int main(void) { 80025f8: b580 push {r7, lr} 80025fa: af00 add r7, sp, #0 /** * Initialisation */ mainPeripheralsInit(); 80025fc: f000 f82a bl 8002654 Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) { __ASM volatile ("wfe"); 8002600: bf20 wfe while (1){ __WFE(); // Bascule la puce en sleep mode if (Dumber.flagSystick == 1) 8002602: 4b12 ldr r3, [pc, #72] ; (800264c ) 8002604: 7d9b ldrb r3, [r3, #22] 8002606: 2b01 cmp r3, #1 8002608: d1fa bne.n 8002600 { Dumber.flagSystick = 0; 800260a: 4b10 ldr r3, [pc, #64] ; (800264c ) 800260c: 2200 movs r2, #0 800260e: 759a strb r2, [r3, #22] /* Gestion des niveaux de batterie */ batteryManagement(); 8002610: f7ff fc00 bl 8001e14 /* Gestion des moteurs (asservissement, .. */ motorManagement(); 8002614: f000 fa70 bl 8002af8 /* Gestion du clignotement de la led, f=100Hz*/ ledManagement(Dumber.StateSystem, Dumber.stateBattery); 8002618: 4b0c ldr r3, [pc, #48] ; (800264c ) 800261a: 791a ldrb r2, [r3, #4] 800261c: 4b0b ldr r3, [pc, #44] ; (800264c ) 800261e: 7d5b ldrb r3, [r3, #21] 8002620: 4619 mov r1, r3 8002622: 4610 mov r0, r2 8002624: f7ff ff9a bl 800255c if (Dumber.StateSystem == STATE_DISABLE) { 8002628: 4b08 ldr r3, [pc, #32] ; (800264c ) 800262a: 791b ldrb r3, [r3, #4] 800262c: 2b03 cmp r3, #3 800262e: d1e7 bne.n 8002600 cptMesureEmergencyHalt++; 8002630: 4b07 ldr r3, [pc, #28] ; (8002650 ) 8002632: 681b ldr r3, [r3, #0] 8002634: 3301 adds r3, #1 8002636: 4a06 ldr r2, [pc, #24] ; (8002650 ) 8002638: 6013 str r3, [r2, #0] if (cptMesureEmergencyHalt >= COMPTEUR_SEUIL_EMERGENCY_HALT) { 800263a: 4b05 ldr r3, [pc, #20] ; (8002650 ) 800263c: 681b ldr r3, [r3, #0] 800263e: f640 32b7 movw r2, #2999 ; 0xbb7 8002642: 4293 cmp r3, r2 8002644: d9dc bls.n 8002600 systemShutDown(); 8002646: f000 fbd1 bl 8002dec while (1); 800264a: e7fe b.n 800264a 800264c: 20000330 .word 0x20000330 8002650: 2000020c .word 0x2000020c 08002654 : /** * @brief Initialise les périphériques pour leur utilisation. * @param None * @retval None */ void mainPeripheralsInit(void) { 8002654: b580 push {r7, lr} 8002656: af00 add r7, sp, #0 mainConfigureClock(); 8002658: f000 f80c bl 8002674 systemConfigure(); 800265c: f000 fb7c bl 8002d58 motorConfigure(); 8002660: f000 f81e bl 80026a0 ledConfigure(); 8002664: f7ff ff24 bl 80024b0 usartConfigure(); 8002668: f000 fd6e bl 8003148 batteryConfigure(); 800266c: f7ff faf2 bl 8001c54 } 8002670: bf00 nop 8002672: bd80 pop {r7, pc} 08002674 : * @brief Initialise les horloges du micro et de ses périphériques. * @param None * @retval None */ void mainConfigureClock(void) { 8002674: b580 push {r7, lr} 8002676: af00 add r7, sp, #0 //Configuration de la fréquence d'horloge de l'adc */ RCC_ADCCLKConfig(RCC_PCLK2_Div2); 8002678: 2000 movs r0, #0 800267a: f7fe ff0f bl 800149c RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); 800267e: 2101 movs r1, #1 8002680: 2001 movs r0, #1 8002682: f7fe ff73 bl 800156c //Activation de l'horloge du GPIO, de A, B et C, de ADC1, de AFIO RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3|RCC_APB1Periph_TIM2|RCC_APB2Periph_USART1, ENABLE); 8002686: 2101 movs r1, #1 8002688: f244 0003 movw r0, #16387 ; 0x4003 800268c: f7fe ff8a bl 80015a4 RCC_APB2PeriphClockCmd( RCC_APB2Periph_ADC1| RCC_APB2Periph_TIM1 |RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | 8002690: 2101 movs r1, #1 8002692: f645 201d movw r0, #23069 ; 0x5a1d 8002696: f7fe ff77 bl 8001588 RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO|RCC_APB2Periph_USART1|RCC_APB2Periph_SPI1, ENABLE); } 800269a: bf00 nop 800269c: bd80 pop {r7, pc} ... 080026a0 : * @param None * @retval None * */ void motorConfigure(void) { 80026a0: b5f0 push {r4, r5, r6, r7, lr} 80026a2: b08d sub sp, #52 ; 0x34 TIM_OCInitTypeDef TIM2_Configure; TIM_ICInitTypeDef TIM_ICInitStructure; NVIC_InitTypeDef NVIC_InitStructure; // Configure les PIN A1 et A2 en output / alternate fonction Init_Structure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2; 80026a4: 2306 movs r3, #6 80026a6: f8ad 302c strh.w r3, [sp, #44] ; 0x2c Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 80026aa: 2403 movs r4, #3 80026ac: f88d 402e strb.w r4, [sp, #46] ; 0x2e Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP; 80026b0: 2318 movs r3, #24 80026b2: f88d 302f strb.w r3, [sp, #47] ; 0x2f GPIO_Init(GPIOA, &Init_Structure); 80026b6: 4d57 ldr r5, [pc, #348] ; (8002814 ) 80026b8: a90b add r1, sp, #44 ; 0x2c 80026ba: 4628 mov r0, r5 80026bc: f7fe fe46 bl 800134c // Configure les PIN B12,B13,B14, et B15 en output ppull. Init_Structure.GPIO_Pin = GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15; 80026c0: f44f 4370 mov.w r3, #61440 ; 0xf000 80026c4: f8ad 302c strh.w r3, [sp, #44] ; 0x2c Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 80026c8: f88d 402e strb.w r4, [sp, #46] ; 0x2e Init_Structure.GPIO_Mode = GPIO_Mode_Out_PP; 80026cc: 2610 movs r6, #16 80026ce: f88d 602f strb.w r6, [sp, #47] ; 0x2f GPIO_Init(GPIOB, &Init_Structure); 80026d2: a90b add r1, sp, #44 ; 0x2c 80026d4: 4850 ldr r0, [pc, #320] ; (8002818 ) 80026d6: f7fe fe39 bl 800134c // Configure les PIN A12 en output ppull - enable encodeurs Init_Structure.GPIO_Pin = GPIO_Pin_12; 80026da: f44f 5380 mov.w r3, #4096 ; 0x1000 80026de: f8ad 302c strh.w r3, [sp, #44] ; 0x2c Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 80026e2: f88d 402e strb.w r4, [sp, #46] ; 0x2e Init_Structure.GPIO_Mode = GPIO_Mode_Out_PP; 80026e6: f88d 602f strb.w r6, [sp, #47] ; 0x2f GPIO_Init(GPIOA, &Init_Structure); 80026ea: a90b add r1, sp, #44 ; 0x2c 80026ec: 4628 mov r0, r5 80026ee: f7fe fe2d bl 800134c // Configure les PIN A8,A9,A10, et A11 en input floating. Init_Structure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|GPIO_Pin_11; 80026f2: f44f 6370 mov.w r3, #3840 ; 0xf00 80026f6: f8ad 302c strh.w r3, [sp, #44] ; 0x2c Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 80026fa: f88d 402e strb.w r4, [sp, #46] ; 0x2e Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 80026fe: 2604 movs r6, #4 8002700: f88d 602f strb.w r6, [sp, #47] ; 0x2f GPIO_Init(GPIOA, &Init_Structure); 8002704: a90b add r1, sp, #44 ; 0x2c 8002706: 4628 mov r0, r5 8002708: f7fe fe20 bl 800134c // Configuration du timer 2 (pwm moteurs* // On souhaite une résolution du PWM de 256 valeurs MOTOR1 TIM2 TIM2_TempsPWMsettings.TIM_Period = 255; 800270c: 23ff movs r3, #255 ; 0xff 800270e: f8ad 3024 strh.w r3, [sp, #36] ; 0x24 TIM2_TempsPWMsettings.TIM_Prescaler = 0; 8002712: 2400 movs r4, #0 8002714: f8ad 4020 strh.w r4, [sp, #32] TIM2_TempsPWMsettings.TIM_ClockDivision=0; 8002718: f8ad 4026 strh.w r4, [sp, #38] ; 0x26 TIM2_TempsPWMsettings.TIM_CounterMode=TIM_CounterMode_Up; 800271c: f8ad 4022 strh.w r4, [sp, #34] ; 0x22 TIM_TimeBaseInit(TIM2, &TIM2_TempsPWMsettings); 8002720: a908 add r1, sp, #32 8002722: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002726: f7ff f83d bl 80017a4 // Configuration du PWM sur le timer 2 TIM2_Configure.TIM_OCMode=TIM_OCMode_PWM2; 800272a: 2370 movs r3, #112 ; 0x70 800272c: f8ad 3010 strh.w r3, [sp, #16] TIM2_Configure.TIM_OutputState = TIM_OutputState_Enable; 8002730: 2501 movs r5, #1 8002732: f8ad 5012 strh.w r5, [sp, #18] TIM2_Configure.TIM_OutputNState = TIM_OutputNState_Enable; 8002736: f8ad 6014 strh.w r6, [sp, #20] TIM2_Configure.TIM_Pulse = 256; // Constante initialisée à 256, pour un rapport cyclique nul 800273a: f44f 7380 mov.w r3, #256 ; 0x100 800273e: f8ad 3016 strh.w r3, [sp, #22] TIM2_Configure.TIM_OCPolarity = TIM_OCPolarity_High; 8002742: f8ad 4018 strh.w r4, [sp, #24] TIM_OC3Init(TIM2, &TIM2_Configure); 8002746: a904 add r1, sp, #16 8002748: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800274c: f7ff f8b8 bl 80018c0 TIM_OC3PreloadConfig(TIM2,TIM_OCPreload_Enable); 8002750: 2108 movs r1, #8 8002752: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002756: f7ff f938 bl 80019ca TIM_OC2Init(TIM2, &TIM2_Configure); 800275a: a904 add r1, sp, #16 800275c: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002760: f7ff f86a bl 8001838 TIM_OC2PreloadConfig(TIM2,TIM_OCPreload_Enable); 8002764: 2108 movs r1, #8 8002766: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800276a: f7ff f925 bl 80019b8 TIM_ARRPreloadConfig(TIM2, ENABLE); 800276e: 4629 mov r1, r5 8002770: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002774: f7ff f912 bl 800199c // Enable Counter TIM_Cmd(TIM2, ENABLE); 8002778: 4629 mov r1, r5 800277a: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800277e: f7ff f8e1 bl 8001944 TIM_CtrlPWMOutputs(TIM2,ENABLE); 8002782: 4629 mov r1, r5 8002784: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002788: f7ff f8ea bl 8001960 // Configuration de la capture de l'encodeur 1 TIM_ICInitStructure.TIM_Channel = TIM_Channel_1; 800278c: f8ad 4004 strh.w r4, [sp, #4] TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; 8002790: f8ad 4006 strh.w r4, [sp, #6] TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; 8002794: f8ad 5008 strh.w r5, [sp, #8] TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; 8002798: f8ad 400a strh.w r4, [sp, #10] TIM_ICInitStructure.TIM_ICFilter = 0x0; 800279c: f8ad 400c strh.w r4, [sp, #12] TIM_ICInit(TIM1, &TIM_ICInitStructure); 80027a0: 4e1e ldr r6, [pc, #120] ; (800281c ) 80027a2: a901 add r1, sp, #4 80027a4: 4630 mov r0, r6 80027a6: f7ff f94b bl 8001a40 TIM_Cmd(TIM1, ENABLE); 80027aa: 4629 mov r1, r5 80027ac: 4630 mov r0, r6 80027ae: f7ff f8c9 bl 8001944 TIM_ITConfig(TIM1, TIM_IT_CC1, ENABLE); 80027b2: 462a mov r2, r5 80027b4: 2102 movs r1, #2 80027b6: 4630 mov r0, r6 80027b8: f7ff f8e4 bl 8001984 // Configuration de la capture de l'encodeur 1 TIM_ICInitStructure.TIM_Channel = TIM_Channel_3; 80027bc: 2708 movs r7, #8 80027be: f8ad 7004 strh.w r7, [sp, #4] TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; 80027c2: f8ad 4006 strh.w r4, [sp, #6] TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; 80027c6: f8ad 5008 strh.w r5, [sp, #8] TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; 80027ca: f8ad 400a strh.w r4, [sp, #10] TIM_ICInitStructure.TIM_ICFilter = 0x0; 80027ce: f8ad 400c strh.w r4, [sp, #12] TIM_ICInit(TIM1, &TIM_ICInitStructure); 80027d2: a901 add r1, sp, #4 80027d4: 4630 mov r0, r6 80027d6: f7ff f933 bl 8001a40 TIM_Cmd(TIM1, ENABLE); 80027da: 4629 mov r1, r5 80027dc: 4630 mov r0, r6 80027de: f7ff f8b1 bl 8001944 TIM_ITConfig(TIM1, TIM_IT_CC3, ENABLE); 80027e2: 462a mov r2, r5 80027e4: 4639 mov r1, r7 80027e6: 4630 mov r0, r6 80027e8: f7ff f8cc bl 8001984 // Enable the TIM1 Capture interrupt NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn; 80027ec: 231b movs r3, #27 80027ee: f88d 3000 strb.w r3, [sp] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; 80027f2: f88d 5001 strb.w r5, [sp, #1] NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; 80027f6: f88d 5002 strb.w r5, [sp, #2] NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 80027fa: f88d 5003 strb.w r5, [sp, #3] NVIC_Init(&NVIC_InitStructure); 80027fe: 4668 mov r0, sp 8002800: f7fe fb94 bl 8000f2c // RAZ des variables regulation_vitesseD = 0; 8002804: 4b06 ldr r3, [pc, #24] ; (8002820 ) 8002806: 801c strh r4, [r3, #0] regulation_vitesseG = 0; 8002808: 4b06 ldr r3, [pc, #24] ; (8002824 ) 800280a: 801c strh r4, [r3, #0] asservissement =0; 800280c: 4b06 ldr r3, [pc, #24] ; (8002828 ) 800280e: 801c strh r4, [r3, #0] } 8002810: b00d add sp, #52 ; 0x34 8002812: bdf0 pop {r4, r5, r6, r7, pc} 8002814: 40010800 .word 0x40010800 8002818: 40010c00 .word 0x40010c00 800281c: 40012c00 .word 0x40012c00 8002820: 2000032a .word 0x2000032a 8002824: 2000031c .word 0x2000031c 8002828: 2000031a .word 0x2000031a 0800282c : * @param Consigne de vitesse du moteur, défini par un pwm entre 0 et 255. * @retval None */ void motorCmdRight(char mod, uint16_t pwm) { 800282c: b538 push {r3, r4, r5, lr} pwm = 256 - pwm; 800282e: f5c1 7180 rsb r1, r1, #256 ; 0x100 8002832: b28c uxth r4, r1 switch (mod) { 8002834: 280c cmp r0, #12 8002836: d02a beq.n 800288e 8002838: 280d cmp r0, #13 800283a: d00b beq.n 8002854 800283c: 280b cmp r0, #11 800283e: d01a beq.n 8002876 GPIO_SetBits(GPIOB, GPIO_Pin_13); GPIO_ResetBits(GPIOB, GPIO_Pin_12); break; default: GPIO_ResetBits(GPIOB, 12); 8002840: 4d19 ldr r5, [pc, #100] ; (80028a8 ) 8002842: 210c movs r1, #12 8002844: 4628 mov r0, r5 8002846: f7fe fdd2 bl 80013ee GPIO_ResetBits(GPIOB, 13); 800284a: 210d movs r1, #13 800284c: 4628 mov r0, r5 800284e: f7fe fdce bl 80013ee 8002852: e00a b.n 800286a GPIO_SetBits(GPIOB, GPIO_Pin_12); 8002854: 4d14 ldr r5, [pc, #80] ; (80028a8 ) 8002856: f44f 5180 mov.w r1, #4096 ; 0x1000 800285a: 4628 mov r0, r5 800285c: f7fe fdc5 bl 80013ea GPIO_SetBits(GPIOB, GPIO_Pin_13); 8002860: f44f 5100 mov.w r1, #8192 ; 0x2000 8002864: 4628 mov r0, r5 8002866: f7fe fdc0 bl 80013ea } TIM_SetCompare3(TIM2, pwm); 800286a: 4621 mov r1, r4 800286c: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002870: f7ff f8b4 bl 80019dc 8002874: bd38 pop {r3, r4, r5, pc} GPIO_SetBits(GPIOB, GPIO_Pin_12); 8002876: 4d0c ldr r5, [pc, #48] ; (80028a8 ) 8002878: f44f 5180 mov.w r1, #4096 ; 0x1000 800287c: 4628 mov r0, r5 800287e: f7fe fdb4 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_13); 8002882: f44f 5100 mov.w r1, #8192 ; 0x2000 8002886: 4628 mov r0, r5 8002888: f7fe fdb1 bl 80013ee break; 800288c: e7ed b.n 800286a GPIO_SetBits(GPIOB, GPIO_Pin_13); 800288e: 4d06 ldr r5, [pc, #24] ; (80028a8 ) 8002890: f44f 5100 mov.w r1, #8192 ; 0x2000 8002894: 4628 mov r0, r5 8002896: f7fe fda8 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_12); 800289a: f44f 5180 mov.w r1, #4096 ; 0x1000 800289e: 4628 mov r0, r5 80028a0: f7fe fda5 bl 80013ee break; 80028a4: e7e1 b.n 800286a 80028a6: bf00 nop 80028a8: 40010c00 .word 0x40010c00 080028ac : * @param Mode de fonctionnement du moteur, peut être égal aux constantes BRAKE, FORWARD, REVERSE définis dans moteur.h * @param Consigne de vitesse du moteur, défini par un pwm entre 0 et 255. * @retval None */ void motorCmdLeft(char mod, uint16_t pwm) { 80028ac: b538 push {r3, r4, r5, lr} pwm = 256 - pwm; 80028ae: f5c1 7180 rsb r1, r1, #256 ; 0x100 80028b2: b28c uxth r4, r1 switch (mod) { 80028b4: 280c cmp r0, #12 80028b6: d02c beq.n 8002912 80028b8: 280d cmp r0, #13 80028ba: d00d beq.n 80028d8 80028bc: 280b cmp r0, #11 80028be: d01c beq.n 80028fa GPIO_SetBits(GPIOB, GPIO_Pin_14); GPIO_ResetBits(GPIOB, GPIO_Pin_15); break; default: GPIO_ResetBits(GPIOB, GPIO_Pin_14); 80028c0: 4d1a ldr r5, [pc, #104] ; (800292c ) 80028c2: f44f 4180 mov.w r1, #16384 ; 0x4000 80028c6: 4628 mov r0, r5 80028c8: f7fe fd91 bl 80013ee GPIO_ResetBits(GPIOB, GPIO_Pin_15); 80028cc: f44f 4100 mov.w r1, #32768 ; 0x8000 80028d0: 4628 mov r0, r5 80028d2: f7fe fd8c bl 80013ee 80028d6: e00a b.n 80028ee GPIO_SetBits(GPIOB, GPIO_Pin_14); 80028d8: 4d14 ldr r5, [pc, #80] ; (800292c ) 80028da: f44f 4180 mov.w r1, #16384 ; 0x4000 80028de: 4628 mov r0, r5 80028e0: f7fe fd83 bl 80013ea GPIO_SetBits(GPIOB, GPIO_Pin_15); 80028e4: f44f 4100 mov.w r1, #32768 ; 0x8000 80028e8: 4628 mov r0, r5 80028ea: f7fe fd7e bl 80013ea } TIM_SetCompare2(TIM2, pwm); 80028ee: 4621 mov r1, r4 80028f0: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 80028f4: f7ff f870 bl 80019d8 80028f8: bd38 pop {r3, r4, r5, pc} GPIO_SetBits(GPIOB, GPIO_Pin_15); 80028fa: 4d0c ldr r5, [pc, #48] ; (800292c ) 80028fc: f44f 4100 mov.w r1, #32768 ; 0x8000 8002900: 4628 mov r0, r5 8002902: f7fe fd72 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_14); 8002906: f44f 4180 mov.w r1, #16384 ; 0x4000 800290a: 4628 mov r0, r5 800290c: f7fe fd6f bl 80013ee break; 8002910: e7ed b.n 80028ee GPIO_SetBits(GPIOB, GPIO_Pin_14); 8002912: 4d06 ldr r5, [pc, #24] ; (800292c ) 8002914: f44f 4180 mov.w r1, #16384 ; 0x4000 8002918: 4628 mov r0, r5 800291a: f7fe fd66 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_15); 800291e: f44f 4100 mov.w r1, #32768 ; 0x8000 8002922: 4628 mov r0, r5 8002924: f7fe fd63 bl 80013ee break; 8002928: e7e1 b.n 80028ee 800292a: bf00 nop 800292c: 40010c00 .word 0x40010c00 08002930 : * @brief Commande de plus haut niveau pour contrôler la vitesse moteur Gauche. * * @param Consigne de vitesse du moteur, défini par un pwm entre 0 et 255. * @retval None */ void motorSpeedUpdateLeft(uint16_t pwm) { 8002930: b508 push {r3, lr} pwm = 256 - pwm; 8002932: f5c0 7180 rsb r1, r0, #256 ; 0x100 TIM_SetCompare2(TIM2, pwm); 8002936: b289 uxth r1, r1 8002938: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800293c: f7ff f84c bl 80019d8 8002940: bd08 pop {r3, pc} 08002942 : * @brief Commande de plus haut niveau pour contrôler la vitesse moteur Droit. * * @param Consigne de vitesse du moteur, défini par un pwm entre 0 et 255. * @retval None */ void motorSpeedUpdateRight(uint16_t pwm) { 8002942: b508 push {r3, lr} pwm = 256 - pwm; 8002944: f5c0 7180 rsb r1, r0, #256 ; 0x100 TIM_SetCompare3(TIM2, pwm); 8002948: b289 uxth r1, r1 800294a: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800294e: f7ff f845 bl 80019dc 8002952: bd08 pop {r3, pc} 08002954 : * @param Vitesse de la roue de gauche. * * @retval None */ void motorRegulation(char modRight, char modLeft, uint16_t lapsRight, uint16_t lapsLeft, uint16_t speedRight, uint16_t speedLeft) { 8002954: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8002958: 460c mov r4, r1 800295a: 4616 mov r6, r2 800295c: 4698 mov r8, r3 800295e: f8bd 5020 ldrh.w r5, [sp, #32] 8002962: f8bd 7024 ldrh.w r7, [sp, #36] ; 0x24 /*Moteur Droit*/ switch (modRight) { 8002966: 280c cmp r0, #12 8002968: d039 beq.n 80029de 800296a: 280d cmp r0, #13 800296c: d00c beq.n 8002988 800296e: 280b cmp r0, #11 8002970: d028 beq.n 80029c4 GPIO_SetBits(GPIOB, GPIO_Pin_13); GPIO_ResetBits(GPIOB, GPIO_Pin_12); break; default: GPIO_ResetBits(GPIOB, 12); 8002972: f8df 9100 ldr.w r9, [pc, #256] ; 8002a74 8002976: 210c movs r1, #12 8002978: 4648 mov r0, r9 800297a: f7fe fd38 bl 80013ee GPIO_ResetBits(GPIOB, 13); 800297e: 210d movs r1, #13 8002980: 4648 mov r0, r9 8002982: f7fe fd34 bl 80013ee 8002986: e00b b.n 80029a0 GPIO_SetBits(GPIOB, GPIO_Pin_12); 8002988: f8df 90e8 ldr.w r9, [pc, #232] ; 8002a74 800298c: f44f 5180 mov.w r1, #4096 ; 0x1000 8002990: 4648 mov r0, r9 8002992: f7fe fd2a bl 80013ea GPIO_SetBits(GPIOB, GPIO_Pin_13); 8002996: f44f 5100 mov.w r1, #8192 ; 0x2000 800299a: 4648 mov r0, r9 800299c: f7fe fd25 bl 80013ea } /* Moteur Gauche */ switch (modLeft) { 80029a0: 2c0c cmp r4, #12 80029a2: d047 beq.n 8002a34 80029a4: 2c0d cmp r4, #13 80029a6: d027 beq.n 80029f8 80029a8: 2c0b cmp r4, #11 80029aa: d037 beq.n 8002a1c GPIO_SetBits(GPIOB, GPIO_Pin_14); GPIO_ResetBits(GPIOB, GPIO_Pin_15); break; default: GPIO_ResetBits(GPIOB, GPIO_Pin_14); 80029ac: 4c31 ldr r4, [pc, #196] ; (8002a74 ) 80029ae: f44f 4180 mov.w r1, #16384 ; 0x4000 80029b2: 4620 mov r0, r4 80029b4: f7fe fd1b bl 80013ee GPIO_ResetBits(GPIOB, GPIO_Pin_15); 80029b8: f44f 4100 mov.w r1, #32768 ; 0x8000 80029bc: 4620 mov r0, r4 80029be: f7fe fd16 bl 80013ee 80029c2: e024 b.n 8002a0e GPIO_SetBits(GPIOB, GPIO_Pin_12); 80029c4: f8df 90ac ldr.w r9, [pc, #172] ; 8002a74 80029c8: f44f 5180 mov.w r1, #4096 ; 0x1000 80029cc: 4648 mov r0, r9 80029ce: f7fe fd0c bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_13); 80029d2: f44f 5100 mov.w r1, #8192 ; 0x2000 80029d6: 4648 mov r0, r9 80029d8: f7fe fd09 bl 80013ee break; 80029dc: e7e0 b.n 80029a0 GPIO_SetBits(GPIOB, GPIO_Pin_13); 80029de: f8df 9094 ldr.w r9, [pc, #148] ; 8002a74 80029e2: f44f 5100 mov.w r1, #8192 ; 0x2000 80029e6: 4648 mov r0, r9 80029e8: f7fe fcff bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_12); 80029ec: f44f 5180 mov.w r1, #4096 ; 0x1000 80029f0: 4648 mov r0, r9 80029f2: f7fe fcfc bl 80013ee break; 80029f6: e7d3 b.n 80029a0 GPIO_SetBits(GPIOB, GPIO_Pin_14); 80029f8: 4c1e ldr r4, [pc, #120] ; (8002a74 ) 80029fa: f44f 4180 mov.w r1, #16384 ; 0x4000 80029fe: 4620 mov r0, r4 8002a00: f7fe fcf3 bl 80013ea GPIO_SetBits(GPIOB, GPIO_Pin_15); 8002a04: f44f 4100 mov.w r1, #32768 ; 0x8000 8002a08: 4620 mov r0, r4 8002a0a: f7fe fcee bl 80013ea } if ((speedRight == 0 && lapsRight > 0) 8002a0e: b905 cbnz r5, 8002a12 8002a10: b91e cbnz r6, 8002a1a || (speedLeft == 0 && lapsLeft > 0)) { 8002a12: b9df cbnz r7, 8002a4c 8002a14: f1b8 0f00 cmp.w r8, #0 8002a18: d018 beq.n 8002a4c 8002a1a: e7fe b.n 8002a1a GPIO_SetBits(GPIOB, GPIO_Pin_15); 8002a1c: 4c15 ldr r4, [pc, #84] ; (8002a74 ) 8002a1e: f44f 4100 mov.w r1, #32768 ; 0x8000 8002a22: 4620 mov r0, r4 8002a24: f7fe fce1 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_14); 8002a28: f44f 4180 mov.w r1, #16384 ; 0x4000 8002a2c: 4620 mov r0, r4 8002a2e: f7fe fcde bl 80013ee break; 8002a32: e7ec b.n 8002a0e GPIO_SetBits(GPIOB, GPIO_Pin_14); 8002a34: 4c0f ldr r4, [pc, #60] ; (8002a74 ) 8002a36: f44f 4180 mov.w r1, #16384 ; 0x4000 8002a3a: 4620 mov r0, r4 8002a3c: f7fe fcd5 bl 80013ea GPIO_ResetBits(GPIOB, GPIO_Pin_15); 8002a40: f44f 4100 mov.w r1, #32768 ; 0x8000 8002a44: 4620 mov r0, r4 8002a46: f7fe fcd2 bl 80013ee break; 8002a4a: e7e0 b.n 8002a0e while (1); } G_lapsLeft = lapsLeft; 8002a4c: 4b0a ldr r3, [pc, #40] ; (8002a78 ) 8002a4e: f8a3 8000 strh.w r8, [r3] G_speedLeft = speedLeft; 8002a52: 4b0a ldr r3, [pc, #40] ; (8002a7c ) 8002a54: 801f strh r7, [r3, #0] G_lapsRight = lapsRight; 8002a56: 4b0a ldr r3, [pc, #40] ; (8002a80 ) 8002a58: 801e strh r6, [r3, #0] G_speedRight = speedRight; 8002a5a: 4b0a ldr r3, [pc, #40] ; (8002a84 ) 8002a5c: 801d strh r5, [r3, #0] asservissement = 1; 8002a5e: 2201 movs r2, #1 8002a60: 4b09 ldr r3, [pc, #36] ; (8002a88 ) 8002a62: 801a strh r2, [r3, #0] tourPositionD = 0; 8002a64: 2300 movs r3, #0 8002a66: 4a09 ldr r2, [pc, #36] ; (8002a8c ) 8002a68: 8013 strh r3, [r2, #0] tourPositionG = 0; 8002a6a: 4a09 ldr r2, [pc, #36] ; (8002a90 ) 8002a6c: 8013 strh r3, [r2, #0] 8002a6e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8002a72: bf00 nop 8002a74: 40010c00 .word 0x40010c00 8002a78: 2000031e .word 0x2000031e 8002a7c: 20000014 .word 0x20000014 8002a80: 2000032c .word 0x2000032c 8002a84: 20000016 .word 0x20000016 8002a88: 2000031a .word 0x2000031a 8002a8c: 20000318 .word 0x20000318 8002a90: 20000328 .word 0x20000328 08002a94 : * de tour des deux roues. * * @param None * @retval None */ void TIM1_CC_IRQHandler(void) { 8002a94: b508 push {r3, lr} if (TIM_GetITStatus(TIM1, TIM_IT_CC1) == SET) { 8002a96: 2102 movs r1, #2 8002a98: 4812 ldr r0, [pc, #72] ; (8002ae4 ) 8002a9a: f7ff f802 bl 8001aa2 8002a9e: 2801 cmp r0, #1 8002aa0: d006 beq.n 8002ab0 TIM_ClearITPendingBit(TIM1, TIM_IT_CC1); tourD++; tourPositionD++; } if (TIM_GetITStatus(TIM1, TIM_IT_CC3) == SET) { 8002aa2: 2108 movs r1, #8 8002aa4: 480f ldr r0, [pc, #60] ; (8002ae4 ) 8002aa6: f7fe fffc bl 8001aa2 8002aaa: 2801 cmp r0, #1 8002aac: d00d beq.n 8002aca 8002aae: bd08 pop {r3, pc} TIM_ClearITPendingBit(TIM1, TIM_IT_CC1); 8002ab0: 2102 movs r1, #2 8002ab2: 480c ldr r0, [pc, #48] ; (8002ae4 ) 8002ab4: f7ff f801 bl 8001aba tourD++; 8002ab8: 4a0b ldr r2, [pc, #44] ; (8002ae8 ) 8002aba: 8813 ldrh r3, [r2, #0] 8002abc: 3301 adds r3, #1 8002abe: 8013 strh r3, [r2, #0] tourPositionD++; 8002ac0: 4a0a ldr r2, [pc, #40] ; (8002aec ) 8002ac2: 8813 ldrh r3, [r2, #0] 8002ac4: 3301 adds r3, #1 8002ac6: 8013 strh r3, [r2, #0] 8002ac8: e7eb b.n 8002aa2 TIM_ClearITPendingBit(TIM1, TIM_IT_CC3); 8002aca: 2108 movs r1, #8 8002acc: 4805 ldr r0, [pc, #20] ; (8002ae4 ) 8002ace: f7fe fff4 bl 8001aba tourG++; 8002ad2: 4a07 ldr r2, [pc, #28] ; (8002af0 ) 8002ad4: 8813 ldrh r3, [r2, #0] 8002ad6: 3301 adds r3, #1 8002ad8: 8013 strh r3, [r2, #0] tourPositionG++; 8002ada: 4a06 ldr r2, [pc, #24] ; (8002af4 ) 8002adc: 8813 ldrh r3, [r2, #0] 8002ade: 3301 adds r3, #1 8002ae0: 8013 strh r3, [r2, #0] } } 8002ae2: e7e4 b.n 8002aae 8002ae4: 40012c00 .word 0x40012c00 8002ae8: 20000224 .word 0x20000224 8002aec: 20000318 .word 0x20000318 8002af0: 20000226 .word 0x20000226 8002af4: 20000328 .word 0x20000328 08002af8 : * @brief Gestion de l'asservissement des moteurs * * @param None * @retval None */ void motorManagement(void) { 8002af8: b5f8 push {r3, r4, r5, r6, r7, lr} if (regulation_vitesseD) { 8002afa: 4b68 ldr r3, [pc, #416] ; (8002c9c ) 8002afc: 881b ldrh r3, [r3, #0] 8002afe: 2b00 cmp r3, #0 8002b00: d045 beq.n 8002b8e erreurD = (signed int) G_speedRight - (signed int) tourD; 8002b02: 4b67 ldr r3, [pc, #412] ; (8002ca0 ) 8002b04: 8818 ldrh r0, [r3, #0] 8002b06: 4b67 ldr r3, [pc, #412] ; (8002ca4 ) 8002b08: 881b ldrh r3, [r3, #0] 8002b0a: 1ac0 subs r0, r0, r3 8002b0c: 4b66 ldr r3, [pc, #408] ; (8002ca8 ) 8002b0e: 6018 str r0, [r3, #0] motD = kp * erreurD + integration1; 8002b10: f7fd ffd2 bl 8000ab8 <__aeabi_i2f> 8002b14: 4607 mov r7, r0 8002b16: 4965 ldr r1, [pc, #404] ; (8002cac ) 8002b18: f7fe f822 bl 8000b60 <__aeabi_fmul> 8002b1c: 4d64 ldr r5, [pc, #400] ; (8002cb0 ) 8002b1e: 682e ldr r6, [r5, #0] 8002b20: 4631 mov r1, r6 8002b22: f7fd ff15 bl 8000950 <__addsf3> 8002b26: 4604 mov r4, r0 8002b28: 4b62 ldr r3, [pc, #392] ; (8002cb4 ) 8002b2a: 6018 str r0, [r3, #0] integration1 += ki * erreurD; 8002b2c: f04f 517f mov.w r1, #1069547520 ; 0x3fc00000 8002b30: 4638 mov r0, r7 8002b32: f7fe f815 bl 8000b60 <__aeabi_fmul> 8002b36: 4601 mov r1, r0 8002b38: 4630 mov r0, r6 8002b3a: f7fd ff09 bl 8000950 <__addsf3> 8002b3e: 6028 str r0, [r5, #0] if (motD > 255) motD = 255; 8002b40: 495d ldr r1, [pc, #372] ; (8002cb8 ) 8002b42: 4620 mov r0, r4 8002b44: f7fe f9c8 bl 8000ed8 <__aeabi_fcmpgt> 8002b48: b110 cbz r0, 8002b50 8002b4a: 4a5b ldr r2, [pc, #364] ; (8002cb8 ) 8002b4c: 4b59 ldr r3, [pc, #356] ; (8002cb4 ) 8002b4e: 601a str r2, [r3, #0] if (motD < 0) motD = 0; 8002b50: 2100 movs r1, #0 8002b52: 4b58 ldr r3, [pc, #352] ; (8002cb4 ) 8002b54: 6818 ldr r0, [r3, #0] 8002b56: f7fe f9a1 bl 8000e9c <__aeabi_fcmplt> 8002b5a: 2800 cmp r0, #0 8002b5c: d168 bne.n 8002c30 motD = (uint16_t) motD; 8002b5e: 4d55 ldr r5, [pc, #340] ; (8002cb4 ) 8002b60: 6828 ldr r0, [r5, #0] 8002b62: f7fe f9c3 bl 8000eec <__aeabi_f2uiz> 8002b66: b284 uxth r4, r0 8002b68: 4620 mov r0, r4 8002b6a: f7fd ffa1 bl 8000ab0 <__aeabi_ui2f> 8002b6e: 6028 str r0, [r5, #0] motorSpeedUpdateRight(motD); 8002b70: 4620 mov r0, r4 8002b72: f7ff fee6 bl 8002942 tourD = 0; 8002b76: 2300 movs r3, #0 8002b78: 4a4a ldr r2, [pc, #296] ; (8002ca4 ) 8002b7a: 8013 strh r3, [r2, #0] regulation_vitesseD = 0; 8002b7c: 4a47 ldr r2, [pc, #284] ; (8002c9c ) 8002b7e: 8013 strh r3, [r2, #0] if (G_lapsRight - tourPositionD < 0) { 8002b80: 4b4e ldr r3, [pc, #312] ; (8002cbc ) 8002b82: 881b ldrh r3, [r3, #0] 8002b84: 4a4e ldr r2, [pc, #312] ; (8002cc0 ) 8002b86: 8812 ldrh r2, [r2, #0] 8002b88: 1a9b subs r3, r3, r2 8002b8a: 2b00 cmp r3, #0 8002b8c: db54 blt.n 8002c38 motorCmdRight(BRAKE, 255); } } if (regulation_vitesseG) { 8002b8e: 4b4d ldr r3, [pc, #308] ; (8002cc4 ) 8002b90: 881b ldrh r3, [r3, #0] 8002b92: 2b00 cmp r3, #0 8002b94: d044 beq.n 8002c20 erreurG = (signed int) G_speedLeft - (signed int) tourG; 8002b96: 4b4c ldr r3, [pc, #304] ; (8002cc8 ) 8002b98: 8818 ldrh r0, [r3, #0] 8002b9a: 4b4c ldr r3, [pc, #304] ; (8002ccc ) 8002b9c: 881b ldrh r3, [r3, #0] 8002b9e: 1ac0 subs r0, r0, r3 8002ba0: 4b4b ldr r3, [pc, #300] ; (8002cd0 ) 8002ba2: 6018 str r0, [r3, #0] motG = kp * erreurG + integration2; 8002ba4: f7fd ff88 bl 8000ab8 <__aeabi_i2f> 8002ba8: 4607 mov r7, r0 8002baa: 4940 ldr r1, [pc, #256] ; (8002cac ) 8002bac: f7fd ffd8 bl 8000b60 <__aeabi_fmul> 8002bb0: 4d48 ldr r5, [pc, #288] ; (8002cd4 ) 8002bb2: 682e ldr r6, [r5, #0] 8002bb4: 4631 mov r1, r6 8002bb6: f7fd fecb bl 8000950 <__addsf3> 8002bba: 4604 mov r4, r0 8002bbc: 4b46 ldr r3, [pc, #280] ; (8002cd8 ) 8002bbe: 6018 str r0, [r3, #0] integration2 += ki * erreurG; 8002bc0: f04f 517f mov.w r1, #1069547520 ; 0x3fc00000 8002bc4: 4638 mov r0, r7 8002bc6: f7fd ffcb bl 8000b60 <__aeabi_fmul> 8002bca: 4601 mov r1, r0 8002bcc: 4630 mov r0, r6 8002bce: f7fd febf bl 8000950 <__addsf3> 8002bd2: 6028 str r0, [r5, #0] if (motG > 255) motG = 255; 8002bd4: 4938 ldr r1, [pc, #224] ; (8002cb8 ) 8002bd6: 4620 mov r0, r4 8002bd8: f7fe f97e bl 8000ed8 <__aeabi_fcmpgt> 8002bdc: b110 cbz r0, 8002be4 8002bde: 4a36 ldr r2, [pc, #216] ; (8002cb8 ) 8002be0: 4b3d ldr r3, [pc, #244] ; (8002cd8 ) 8002be2: 601a str r2, [r3, #0] if (motG < 0) motG = 0; 8002be4: 2100 movs r1, #0 8002be6: 4b3c ldr r3, [pc, #240] ; (8002cd8 ) 8002be8: 6818 ldr r0, [r3, #0] 8002bea: f7fe f957 bl 8000e9c <__aeabi_fcmplt> 8002bee: bb40 cbnz r0, 8002c42 motG = (uint16_t) motG; 8002bf0: 4d39 ldr r5, [pc, #228] ; (8002cd8 ) 8002bf2: 6828 ldr r0, [r5, #0] 8002bf4: f7fe f97a bl 8000eec <__aeabi_f2uiz> 8002bf8: b284 uxth r4, r0 8002bfa: 4620 mov r0, r4 8002bfc: f7fd ff58 bl 8000ab0 <__aeabi_ui2f> 8002c00: 6028 str r0, [r5, #0] motorSpeedUpdateLeft(motG); 8002c02: 4620 mov r0, r4 8002c04: f7ff fe94 bl 8002930 tourG = 0; 8002c08: 2300 movs r3, #0 8002c0a: 4a30 ldr r2, [pc, #192] ; (8002ccc ) 8002c0c: 8013 strh r3, [r2, #0] regulation_vitesseG = 0; 8002c0e: 4a2d ldr r2, [pc, #180] ; (8002cc4 ) 8002c10: 8013 strh r3, [r2, #0] if (G_lapsLeft - tourPositionG < 0) { 8002c12: 4b32 ldr r3, [pc, #200] ; (8002cdc ) 8002c14: 881b ldrh r3, [r3, #0] 8002c16: 4a32 ldr r2, [pc, #200] ; (8002ce0 ) 8002c18: 8812 ldrh r2, [r2, #0] 8002c1a: 1a9b subs r3, r3, r2 8002c1c: 2b00 cmp r3, #0 8002c1e: db14 blt.n 8002c4a motorCmdLeft(BRAKE, 255); } } if (G_lapsLeft - tourPositionG < 0 && G_lapsRight - tourPositionD < 0 8002c20: 4b2e ldr r3, [pc, #184] ; (8002cdc ) 8002c22: 881b ldrh r3, [r3, #0] 8002c24: 4a2e ldr r2, [pc, #184] ; (8002ce0 ) 8002c26: 8812 ldrh r2, [r2, #0] 8002c28: 1a9b subs r3, r3, r2 8002c2a: 2b00 cmp r3, #0 8002c2c: db12 blt.n 8002c54 8002c2e: bdf8 pop {r3, r4, r5, r6, r7, pc} if (motD < 0) motD = 0; 8002c30: 2200 movs r2, #0 8002c32: 4b20 ldr r3, [pc, #128] ; (8002cb4 ) 8002c34: 601a str r2, [r3, #0] 8002c36: e792 b.n 8002b5e motorCmdRight(BRAKE, 255); 8002c38: 21ff movs r1, #255 ; 0xff 8002c3a: 200d movs r0, #13 8002c3c: f7ff fdf6 bl 800282c 8002c40: e7a5 b.n 8002b8e if (motG < 0) motG = 0; 8002c42: 2200 movs r2, #0 8002c44: 4b24 ldr r3, [pc, #144] ; (8002cd8 ) 8002c46: 601a str r2, [r3, #0] 8002c48: e7d2 b.n 8002bf0 motorCmdLeft(BRAKE, 255); 8002c4a: 21ff movs r1, #255 ; 0xff 8002c4c: 200d movs r0, #13 8002c4e: f7ff fe2d bl 80028ac 8002c52: e7e5 b.n 8002c20 if (G_lapsLeft - tourPositionG < 0 && G_lapsRight - tourPositionD < 0 8002c54: 4b19 ldr r3, [pc, #100] ; (8002cbc ) 8002c56: 881b ldrh r3, [r3, #0] 8002c58: 4a19 ldr r2, [pc, #100] ; (8002cc0 ) 8002c5a: 8812 ldrh r2, [r2, #0] 8002c5c: 1a9b subs r3, r3, r2 8002c5e: 2b00 cmp r3, #0 8002c60: dae5 bge.n 8002c2e && asservissement == 1) { 8002c62: 4b20 ldr r3, [pc, #128] ; (8002ce4 ) 8002c64: 881b ldrh r3, [r3, #0] 8002c66: 2b01 cmp r3, #1 8002c68: d1e1 bne.n 8002c2e motorCmdLeft(BRAKE, 255); 8002c6a: 21ff movs r1, #255 ; 0xff 8002c6c: 200d movs r0, #13 8002c6e: f7ff fe1d bl 80028ac motorCmdRight(BRAKE, 255); 8002c72: 21ff movs r1, #255 ; 0xff 8002c74: 200d movs r0, #13 8002c76: f7ff fdd9 bl 800282c asservissement = 0; 8002c7a: 2300 movs r3, #0 8002c7c: 4a19 ldr r2, [pc, #100] ; (8002ce4 ) 8002c7e: 8013 strh r3, [r2, #0] erreurD = 0; 8002c80: 4a09 ldr r2, [pc, #36] ; (8002ca8 ) 8002c82: 6013 str r3, [r2, #0] erreurG = 0; 8002c84: 4a12 ldr r2, [pc, #72] ; (8002cd0 ) 8002c86: 6013 str r3, [r2, #0] integration1 = 0; 8002c88: 2200 movs r2, #0 8002c8a: 4909 ldr r1, [pc, #36] ; (8002cb0 ) 8002c8c: 600a str r2, [r1, #0] integration2 = 0; 8002c8e: 4911 ldr r1, [pc, #68] ; (8002cd4 ) 8002c90: 600a str r2, [r1, #0] Dumber.busyState = FALSE; 8002c92: 4a15 ldr r2, [pc, #84] ; (8002ce8 ) 8002c94: 2132 movs r1, #50 ; 0x32 8002c96: 73d1 strb r1, [r2, #15] Dumber.cpt_inactivity = 0; 8002c98: 6113 str r3, [r2, #16] } } 8002c9a: e7c8 b.n 8002c2e 8002c9c: 2000032a .word 0x2000032a 8002ca0: 20000016 .word 0x20000016 8002ca4: 20000224 .word 0x20000224 8002ca8: 20000320 .word 0x20000320 8002cac: 41700000 .word 0x41700000 8002cb0: 20000214 .word 0x20000214 8002cb4: 2000021c .word 0x2000021c 8002cb8: 437f0000 .word 0x437f0000 8002cbc: 2000032c .word 0x2000032c 8002cc0: 20000318 .word 0x20000318 8002cc4: 2000031c .word 0x2000031c 8002cc8: 20000014 .word 0x20000014 8002ccc: 20000226 .word 0x20000226 8002cd0: 20000324 .word 0x20000324 8002cd4: 20000218 .word 0x20000218 8002cd8: 20000220 .word 0x20000220 8002cdc: 2000031e .word 0x2000031e 8002ce0: 20000328 .word 0x20000328 8002ce4: 2000031a .word 0x2000031a 8002ce8: 20000330 .word 0x20000330 08002cec : /******************************************************************************/ /** * @brief This function handles NMI exception. */ void NMI_Handler(void) { 8002cec: b480 push {r7} 8002cee: af00 add r7, sp, #0 } 8002cf0: bf00 nop 8002cf2: 46bd mov sp, r7 8002cf4: bc80 pop {r7} 8002cf6: 4770 bx lr 08002cf8 : /** * @brief This function handles Hard Fault exception. */ void HardFault_Handler(void) { 8002cf8: b480 push {r7} 8002cfa: af00 add r7, sp, #0 /* Go to infinite loop when Hard Fault exception occurs */ while (1) { 8002cfc: e7fe b.n 8002cfc 08002cfe : } /** * @brief This function handles Memory Manage exception. */ void MemManage_Handler(void) { 8002cfe: b480 push {r7} 8002d00: af00 add r7, sp, #0 /* Go to infinite loop when Memory Manage exception occurs */ while (1) { 8002d02: e7fe b.n 8002d02 08002d04 : /** * @brief This function handles Bus Fault exception. */ void BusFault_Handler(void) { 8002d04: b480 push {r7} 8002d06: af00 add r7, sp, #0 /* Go to infinite loop when Bus Fault exception occurs */ while (1) { 8002d08: e7fe b.n 8002d08 08002d0a : } /** * @brief This function handles Usage Fault exception. */ void UsageFault_Handler(void) { 8002d0a: b480 push {r7} 8002d0c: af00 add r7, sp, #0 /* Go to infinite loop when Usage Fault exception occurs */ while (1) { 8002d0e: e7fe b.n 8002d0e 08002d10 : } /** * @brief This function handles SVCall exception. */ void SVC_Handler(void) { 8002d10: b480 push {r7} 8002d12: af00 add r7, sp, #0 } 8002d14: bf00 nop 8002d16: 46bd mov sp, r7 8002d18: bc80 pop {r7} 8002d1a: 4770 bx lr 08002d1c : /** * @brief This function handles Debug Monitor exception. */ void DebugMon_Handler(void) { 8002d1c: b480 push {r7} 8002d1e: af00 add r7, sp, #0 } 8002d20: bf00 nop 8002d22: 46bd mov sp, r7 8002d24: bc80 pop {r7} 8002d26: 4770 bx lr 08002d28 : /** * @brief This function handles PendSVC exception. */ void PendSV_Handler(void) { 8002d28: b480 push {r7} 8002d2a: af00 add r7, sp, #0 } 8002d2c: bf00 nop 8002d2e: 46bd mov sp, r7 8002d30: bc80 pop {r7} 8002d32: 4770 bx lr 08002d34 <_sbrk>: errno = ENOSYS; return -1; } void * _sbrk(int32_t incr) { 8002d34: 4603 mov r3, r0 extern char end; /* Set by linker. */ static char * heap_end; char * prev_heap_end; if (heap_end == 0) { 8002d36: 4a06 ldr r2, [pc, #24] ; (8002d50 <_sbrk+0x1c>) 8002d38: 6812 ldr r2, [r2, #0] 8002d3a: b122 cbz r2, 8002d46 <_sbrk+0x12> heap_end = & end; } prev_heap_end = heap_end; 8002d3c: 4a04 ldr r2, [pc, #16] ; (8002d50 <_sbrk+0x1c>) 8002d3e: 6810 ldr r0, [r2, #0] heap_end += incr; 8002d40: 4403 add r3, r0 8002d42: 6013 str r3, [r2, #0] return (void *) prev_heap_end; } 8002d44: 4770 bx lr heap_end = & end; 8002d46: 4903 ldr r1, [pc, #12] ; (8002d54 <_sbrk+0x20>) 8002d48: 4a01 ldr r2, [pc, #4] ; (8002d50 <_sbrk+0x1c>) 8002d4a: 6011 str r1, [r2, #0] 8002d4c: e7f6 b.n 8002d3c <_sbrk+0x8> 8002d4e: bf00 nop 8002d50: 20000228 .word 0x20000228 8002d54: 20000394 .word 0x20000394 08002d58 : * Liaison série : USART *@param None *@retval None */ void systemConfigure(void) { 8002d58: b510 push {r4, lr} 8002d5a: b082 sub sp, #8 GPIO_InitTypeDef Init_Structure; // Configure le systick pour générer des interruptions toutes les 10ms. SysTick_Config(SystemCoreClock / 100); //configuration du systick à 10ms 8002d5c: 4b1d ldr r3, [pc, #116] ; (8002dd4 ) 8002d5e: 681b ldr r3, [r3, #0] 8002d60: 4a1d ldr r2, [pc, #116] ; (8002dd8 ) 8002d62: fba2 2303 umull r2, r3, r2, r3 8002d66: 095b lsrs r3, r3, #5 \return 0 Function succeeded \return 1 Function failed */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 8002d68: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8002d6c: d20c bcs.n 8002d88 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 8002d6e: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8002d72: 3b01 subs r3, #1 8002d74: 4a19 ldr r2, [pc, #100] ; (8002ddc ) 8002d76: 6053 str r3, [r2, #4] SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 8002d78: 21f0 movs r1, #240 ; 0xf0 8002d7a: 4b19 ldr r3, [pc, #100] ; (8002de0 ) 8002d7c: f883 1023 strb.w r1, [r3, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ 8002d80: 2300 movs r3, #0 8002d82: 6093 str r3, [r2, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002d84: 2307 movs r3, #7 8002d86: 6013 str r3, [r2, #0] // Assigne et défini le GPIO necessaire pour la gestion du shutdown. Init_Structure.GPIO_Pin = GPIO_Pin_5; 8002d88: 2120 movs r1, #32 8002d8a: f8ad 1004 strh.w r1, [sp, #4] Init_Structure.GPIO_Mode = GPIO_Mode_Out_PP; 8002d8e: 2310 movs r3, #16 8002d90: f88d 3007 strb.w r3, [sp, #7] Init_Structure.GPIO_Speed = GPIO_Speed_50MHz; 8002d94: 2303 movs r3, #3 8002d96: f88d 3006 strb.w r3, [sp, #6] GPIO_SetBits(GPIOB, GPIO_Pin_5); 8002d9a: 4c12 ldr r4, [pc, #72] ; (8002de4 ) 8002d9c: 4620 mov r0, r4 8002d9e: f7fe fb24 bl 80013ea GPIO_Init(GPIOB, &Init_Structure); 8002da2: a901 add r1, sp, #4 8002da4: 4620 mov r0, r4 8002da6: f7fe fad1 bl 800134c // Initialise la structure system Dumber Dumber.BatteryPercentage = UNDEFINED; 8002daa: 4b0f ldr r3, [pc, #60] ; (8002de8 ) 8002dac: 2265 movs r2, #101 ; 0x65 8002dae: 801a strh r2, [r3, #0] Dumber.BatteryCurrent = UNDEFINED; 8002db0: 805a strh r2, [r3, #2] // Retourne le pourcentage de charge de la batterie Dumber.StateSystem = STATE_IDLE; // État de la MAE 8002db2: 2100 movs r1, #0 8002db4: 7119 strb r1, [r3, #4] Dumber.AddOn = FALSE; // Un AddOn a été détecté 8002db6: 2232 movs r2, #50 ; 0x32 8002db8: 715a strb r2, [r3, #5] Dumber.BatterieChecking = FALSE; // On doit vérifier la valeur de la batterie 8002dba: 719a strb r2, [r3, #6] Dumber.WatchDogStartEnable = FALSE; // Le Robot a été lancé en mode WithWatchDog ou WithoutWatchDog 8002dbc: 729a strb r2, [r3, #10] Dumber.InvalidWatchdogResetCpt=0; 8002dbe: 7399 strb r1, [r3, #14] Dumber.cpt_watchdog = 0; 8002dc0: 8199 strh r1, [r3, #12] Dumber.cpt_systick = 0; 8002dc2: 8119 strh r1, [r3, #8] Dumber.cpt_inactivity = 0; 8002dc4: 6119 str r1, [r3, #16] Dumber.acquisition = FALSE; 8002dc6: 751a strb r2, [r3, #20] Dumber.busyState = FALSE; 8002dc8: 73da strb r2, [r3, #15] Dumber.stateBattery = 2; 8002dca: 2202 movs r2, #2 8002dcc: 755a strb r2, [r3, #21] } 8002dce: b002 add sp, #8 8002dd0: bd10 pop {r4, pc} 8002dd2: bf00 nop 8002dd4: 20000018 .word 0x20000018 8002dd8: 51eb851f .word 0x51eb851f 8002ddc: e000e010 .word 0xe000e010 8002de0: e000ed00 .word 0xe000ed00 8002de4: 40010c00 .word 0x40010c00 8002de8: 20000330 .word 0x20000330 08002dec : /** * @brief Désactive les interruptions et entre dans une boucle while (1) en attendant l'extinction du CPU. * @param None */ void systemShutDown(void) { 8002dec: b508 push {r3, lr} This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); 8002dee: b672 cpsid i __disable_irq(); GPIO_ResetBits(GPIOB, GPIO_Pin_5); 8002df0: 2120 movs r1, #32 8002df2: 4802 ldr r0, [pc, #8] ; (8002dfc ) 8002df4: f7fe fafb bl 80013ee 8002df8: e7fe b.n 8002df8 8002dfa: bf00 nop 8002dfc: 40010c00 .word 0x40010c00 08002e00 : * @brief Bascule le système dans un état. * * @param state: Nouvel état * @retval None */ void systemChangeState(States state) { 8002e00: b510 push {r4, lr} switch (state) 8002e02: 2804 cmp r0, #4 8002e04: d85e bhi.n 8002ec4 8002e06: e8df f000 tbb [pc, r0] 8002e0a: 1903 .short 0x1903 8002e0c: 2f24 .short 0x2f24 8002e0e: 4a .byte 0x4a 8002e0f: 00 .byte 0x00 { case STATE_IDLE: Dumber.StateSystem = STATE_IDLE; 8002e10: 4b2e ldr r3, [pc, #184] ; (8002ecc ) 8002e12: 2400 movs r4, #0 8002e14: 711c strb r4, [r3, #4] Dumber.WatchDogStartEnable = FALSE; 8002e16: 2232 movs r2, #50 ; 0x32 8002e18: 729a strb r2, [r3, #10] Dumber.cpt_watchdog = 0; 8002e1a: 819c strh r4, [r3, #12] Dumber.InvalidWatchdogResetCpt=0; 8002e1c: 739c strb r4, [r3, #14] Dumber.cpt_systick = 0; 8002e1e: 811c strh r4, [r3, #8] GPIO_SetBits(GPIOA,GPIO_Pin_12); // Désactive les encodeurs 8002e20: f44f 5180 mov.w r1, #4096 ; 0x1000 8002e24: 482a ldr r0, [pc, #168] ; (8002ed0 ) 8002e26: f7fe fae0 bl 80013ea motorCmdLeft(BRAKE, 0); 8002e2a: 4621 mov r1, r4 8002e2c: 200d movs r0, #13 8002e2e: f7ff fd3d bl 80028ac motorCmdRight(BRAKE, 0); 8002e32: 4621 mov r1, r4 8002e34: 200d movs r0, #13 8002e36: f7ff fcf9 bl 800282c break; 8002e3a: bd10 pop {r4, pc} case STATE_RUN: Dumber.StateSystem=STATE_RUN; 8002e3c: 4c23 ldr r4, [pc, #140] ; (8002ecc ) 8002e3e: 2301 movs r3, #1 8002e40: 7123 strb r3, [r4, #4] GPIO_ResetBits(GPIOA,GPIO_Pin_12); // Active les encodeurs 8002e42: f44f 5180 mov.w r1, #4096 ; 0x1000 8002e46: 4822 ldr r0, [pc, #136] ; (8002ed0 ) 8002e48: f7fe fad1 bl 80013ee Dumber.cpt_watchdog=0; 8002e4c: 2300 movs r3, #0 8002e4e: 81a3 strh r3, [r4, #12] break; 8002e50: bd10 pop {r4, pc} case STATE_LOW: Dumber.StateSystem=STATE_LOW; 8002e52: 4c1e ldr r4, [pc, #120] ; (8002ecc ) 8002e54: 2302 movs r3, #2 8002e56: 7123 strb r3, [r4, #4] GPIO_ResetBits(GPIOA,GPIO_Pin_12); // Active les encodeurs 8002e58: f44f 5180 mov.w r1, #4096 ; 0x1000 8002e5c: 481c ldr r0, [pc, #112] ; (8002ed0 ) 8002e5e: f7fe fac6 bl 80013ee Dumber.cpt_watchdog=0; 8002e62: 2300 movs r3, #0 8002e64: 81a3 strh r3, [r4, #12] break; 8002e66: bd10 pop {r4, pc} case STATE_DISABLE: Dumber.StateSystem=STATE_DISABLE; 8002e68: 4c18 ldr r4, [pc, #96] ; (8002ecc ) 8002e6a: 2303 movs r3, #3 8002e6c: 7123 strb r3, [r4, #4] GPIO_SetBits(GPIOA,GPIO_Pin_12); // Désactive les encodeurs 8002e6e: f44f 5180 mov.w r1, #4096 ; 0x1000 8002e72: 4817 ldr r0, [pc, #92] ; (8002ed0 ) 8002e74: f7fe fab9 bl 80013ea motorCmdRight(BRAKE,0); 8002e78: 2100 movs r1, #0 8002e7a: 200d movs r0, #13 8002e7c: f7ff fcd6 bl 800282c motorCmdLeft(BRAKE,0); 8002e80: 2100 movs r1, #0 8002e82: 200d movs r0, #13 8002e84: f7ff fd12 bl 80028ac Dumber.WatchDogStartEnable = FALSE; 8002e88: 2332 movs r3, #50 ; 0x32 8002e8a: 72a3 strb r3, [r4, #10] cptMesureHigh=0; 8002e8c: 2300 movs r3, #0 8002e8e: 4a11 ldr r2, [pc, #68] ; (8002ed4 ) 8002e90: 7013 strb r3, [r2, #0] cptMesureLow=0; 8002e92: 4a11 ldr r2, [pc, #68] ; (8002ed8 ) 8002e94: 7013 strb r3, [r2, #0] cptMesureDisable=0; 8002e96: 4a11 ldr r2, [pc, #68] ; (8002edc ) 8002e98: 7013 strb r3, [r2, #0] Dumber.stateBattery= 0; 8002e9a: 7563 strb r3, [r4, #21] break; 8002e9c: bd10 pop {r4, pc} case STATE_WATCHDOG_DISABLE: Dumber.StateSystem=STATE_WATCHDOG_DISABLE; 8002e9e: 4c0b ldr r4, [pc, #44] ; (8002ecc ) 8002ea0: 2304 movs r3, #4 8002ea2: 7123 strb r3, [r4, #4] GPIO_SetBits(GPIOA,GPIO_Pin_12); // Désactive les encodeurs 8002ea4: f44f 5180 mov.w r1, #4096 ; 0x1000 8002ea8: 4809 ldr r0, [pc, #36] ; (8002ed0 ) 8002eaa: f7fe fa9e bl 80013ea motorCmdRight(BRAKE,0); 8002eae: 2100 movs r1, #0 8002eb0: 200d movs r0, #13 8002eb2: f7ff fcbb bl 800282c motorCmdLeft(BRAKE,0); 8002eb6: 2100 movs r1, #0 8002eb8: 200d movs r0, #13 8002eba: f7ff fcf7 bl 80028ac Dumber.WatchDogStartEnable = FALSE; 8002ebe: 2332 movs r3, #50 ; 0x32 8002ec0: 72a3 strb r3, [r4, #10] break; 8002ec2: bd10 pop {r4, pc} default: /* Unknown state -> go into DISABLE */ systemChangeState(STATE_DISABLE); 8002ec4: 2003 movs r0, #3 8002ec6: f7ff ff9b bl 8002e00 8002eca: bd10 pop {r4, pc} 8002ecc: 20000330 .word 0x20000330 8002ed0: 40010800 .word 0x40010800 8002ed4: 20000210 .word 0x20000210 8002ed8: 20000211 .word 0x20000211 8002edc: 20000208 .word 0x20000208 08002ee0 : * @brief Remise à zéro du watchdog, en fonction de l'état en cours. * * @param None * @retval None */ char systemResetWatchdog(void) { 8002ee0: b508 push {r3, lr} char resultat =0; if ((Dumber.StateSystem == STATE_RUN) || (Dumber.StateSystem == STATE_LOW)) { // si on est actif 8002ee2: 4b14 ldr r3, [pc, #80] ; (8002f34 ) 8002ee4: 791b ldrb r3, [r3, #4] 8002ee6: 3b01 subs r3, #1 8002ee8: b2db uxtb r3, r3 8002eea: 2b01 cmp r3, #1 8002eec: d901 bls.n 8002ef2 char resultat =0; 8002eee: 2000 movs r0, #0 8002ef0: bd08 pop {r3, pc} if (Dumber.WatchDogStartEnable == TRUE) { // si le watchdog est lancé 8002ef2: 4b10 ldr r3, [pc, #64] ; (8002f34 ) 8002ef4: 7a9b ldrb r3, [r3, #10] 8002ef6: 2b28 cmp r3, #40 ; 0x28 8002ef8: d001 beq.n 8002efe char resultat =0; 8002efa: 2000 movs r0, #0 resultat=1; } } return resultat; } 8002efc: bd08 pop {r3, pc} if ((Dumber.cpt_watchdog >= WATCHDOG_MIN) && (Dumber.cpt_watchdog <= WATCHDOG_MAX)) { // si le watchdog est dans sa plage réarmable 8002efe: 4b0d ldr r3, [pc, #52] ; (8002f34 ) 8002f00: 899b ldrh r3, [r3, #12] 8002f02: f2a3 33ca subw r3, r3, #970 ; 0x3ca 8002f06: b29b uxth r3, r3 8002f08: 2b3c cmp r3, #60 ; 0x3c 8002f0a: d807 bhi.n 8002f1c Dumber.InvalidWatchdogResetCpt=0; // on remet le compteur d'erreur à zéro 8002f0c: 2200 movs r2, #0 8002f0e: 4b09 ldr r3, [pc, #36] ; (8002f34 ) 8002f10: 739a strb r2, [r3, #14] Dumber.cpt_watchdog = 0; // on remet le watchdog à zéro 8002f12: 2200 movs r2, #0 8002f14: 4b07 ldr r3, [pc, #28] ; (8002f34 ) 8002f16: 819a strh r2, [r3, #12] resultat=1; 8002f18: 2001 movs r0, #1 8002f1a: bd08 pop {r3, pc} Dumber.InvalidWatchdogResetCpt++; // on incrémente le compteur d'erreur 8002f1c: 4a05 ldr r2, [pc, #20] ; (8002f34 ) 8002f1e: 7b93 ldrb r3, [r2, #14] 8002f20: 3301 adds r3, #1 8002f22: b2db uxtb r3, r3 8002f24: 7393 strb r3, [r2, #14] if (Dumber.InvalidWatchdogResetCpt>WATCHDOG_INVALID_COUNTER_MAX) // on a atteint le max d'erreur possible 8002f26: 2b03 cmp r3, #3 8002f28: d9f3 bls.n 8002f12 systemChangeState(STATE_WATCHDOG_DISABLE); // le système est désactivé 8002f2a: 2004 movs r0, #4 8002f2c: f7ff ff68 bl 8002e00 8002f30: e7ef b.n 8002f12 8002f32: bf00 nop 8002f34: 20000330 .word 0x20000330 08002f38 : * Défini les valeurs d'inactivités. * Défini la valeur de clignotement de la LED. * * @note Tout ces temps sont calculés sous base du systick. */ void SysTick_Handler(void){ 8002f38: b508 push {r3, lr} Dumber.cpt_systick+=10; 8002f3a: 492f ldr r1, [pc, #188] ; (8002ff8 ) 8002f3c: 890b ldrh r3, [r1, #8] 8002f3e: 330a adds r3, #10 8002f40: b29a uxth r2, r3 8002f42: 810a strh r2, [r1, #8] Dumber.cpt_inactivity+=10; 8002f44: 690b ldr r3, [r1, #16] 8002f46: 330a adds r3, #10 8002f48: 610b str r3, [r1, #16] if(asservissement == 1){ 8002f4a: 4b2c ldr r3, [pc, #176] ; (8002ffc ) 8002f4c: 881b ldrh r3, [r3, #0] 8002f4e: 2b01 cmp r3, #1 8002f50: d038 beq.n 8002fc4 regulation_vitesseD =1; regulation_vitesseG =1; } if(Dumber.cpt_systick % TIMER_1s==0) Dumber.cpt_systick=0; 8002f52: 4b2b ldr r3, [pc, #172] ; (8003000 ) 8002f54: fba3 1302 umull r1, r3, r3, r2 8002f58: 099b lsrs r3, r3, #6 8002f5a: f44f 717a mov.w r1, #1000 ; 0x3e8 8002f5e: fb01 2313 mls r3, r1, r3, r2 8002f62: b29b uxth r3, r3 8002f64: b913 cbnz r3, 8002f6c 8002f66: 2200 movs r2, #0 8002f68: 4b23 ldr r3, [pc, #140] ; (8002ff8 ) 8002f6a: 811a strh r2, [r3, #8] /* Gestion du watchdog */ if((Dumber.WatchDogStartEnable == TRUE) && (Dumber.StateSystem != STATE_IDLE)) 8002f6c: 4b22 ldr r3, [pc, #136] ; (8002ff8 ) 8002f6e: 7a9b ldrb r3, [r3, #10] 8002f70: 2b28 cmp r3, #40 ; 0x28 8002f72: d02c beq.n 8002fce Dumber.cpt_watchdog+=10; else Dumber.cpt_watchdog=0; 8002f74: 2200 movs r2, #0 8002f76: 4b20 ldr r3, [pc, #128] ; (8002ff8 ) 8002f78: 819a strh r2, [r3, #12] if (Dumber.cpt_watchdog > WATCHDOG_MAX) { 8002f7a: 4b1f ldr r3, [pc, #124] ; (8002ff8 ) 8002f7c: 899a ldrh r2, [r3, #12] 8002f7e: f240 4306 movw r3, #1030 ; 0x406 8002f82: 429a cmp r2, r3 8002f84: d905 bls.n 8002f92 Dumber.cpt_watchdog=30; // pour avoir toujours un watchdog cadancé à 1000 ms, et pas 1030ms 8002f86: 4b1c ldr r3, [pc, #112] ; (8002ff8 ) 8002f88: 221e movs r2, #30 8002f8a: 819a strh r2, [r3, #12] Dumber.InvalidWatchdogResetCpt++; 8002f8c: 7b9a ldrb r2, [r3, #14] 8002f8e: 3201 adds r2, #1 8002f90: 739a strb r2, [r3, #14] } if (Dumber.InvalidWatchdogResetCpt > WATCHDOG_INVALID_COUNTER_MAX) { 8002f92: 4b19 ldr r3, [pc, #100] ; (8002ff8 ) 8002f94: 7b9b ldrb r3, [r3, #14] 8002f96: 2b03 cmp r3, #3 8002f98: d822 bhi.n 8002fe0 systemChangeState(STATE_WATCHDOG_DISABLE); } if(Dumber.cpt_systick % 500 == 0){ 8002f9a: 4b17 ldr r3, [pc, #92] ; (8002ff8 ) 8002f9c: 891a ldrh r2, [r3, #8] 8002f9e: 4b18 ldr r3, [pc, #96] ; (8003000 ) 8002fa0: fba3 1302 umull r1, r3, r3, r2 8002fa4: 095b lsrs r3, r3, #5 8002fa6: f44f 71fa mov.w r1, #500 ; 0x1f4 8002faa: fb01 2313 mls r3, r1, r3, r2 8002fae: b29b uxth r3, r3 8002fb0: b1d3 cbz r3, 8002fe8 if (etatLED ==12) etatLED = 0; }*/ #if !defined (__NO_INACTIVITY_SHUTDOWN__) if(Dumber.cpt_inactivity>=120000){ 8002fb2: 4b11 ldr r3, [pc, #68] ; (8002ff8 ) 8002fb4: 691a ldr r2, [r3, #16] 8002fb6: 4b13 ldr r3, [pc, #76] ; (8003004 ) 8002fb8: 429a cmp r2, r3 8002fba: dc1b bgt.n 8002ff4 } #else #warning "Shutdown after inactivity period disabled! Not for production !!!" #endif /* __NO_INACTIVITY_SHUTDOWN__ */ Dumber.flagSystick=1; 8002fbc: 2201 movs r2, #1 8002fbe: 4b0e ldr r3, [pc, #56] ; (8002ff8 ) 8002fc0: 759a strb r2, [r3, #22] 8002fc2: bd08 pop {r3, pc} regulation_vitesseD =1; 8002fc4: 4910 ldr r1, [pc, #64] ; (8003008 ) 8002fc6: 800b strh r3, [r1, #0] regulation_vitesseG =1; 8002fc8: 4910 ldr r1, [pc, #64] ; (800300c ) 8002fca: 800b strh r3, [r1, #0] 8002fcc: e7c1 b.n 8002f52 if((Dumber.WatchDogStartEnable == TRUE) && (Dumber.StateSystem != STATE_IDLE)) 8002fce: 4b0a ldr r3, [pc, #40] ; (8002ff8 ) 8002fd0: 791b ldrb r3, [r3, #4] 8002fd2: 2b00 cmp r3, #0 8002fd4: d0ce beq.n 8002f74 Dumber.cpt_watchdog+=10; 8002fd6: 4a08 ldr r2, [pc, #32] ; (8002ff8 ) 8002fd8: 8993 ldrh r3, [r2, #12] 8002fda: 330a adds r3, #10 8002fdc: 8193 strh r3, [r2, #12] 8002fde: e7cc b.n 8002f7a systemChangeState(STATE_WATCHDOG_DISABLE); 8002fe0: 2004 movs r0, #4 8002fe2: f7ff ff0d bl 8002e00 8002fe6: e7d8 b.n 8002f9a Dumber.acquisition=VOLTAGE; 8002fe8: 2262 movs r2, #98 ; 0x62 8002fea: 4b03 ldr r3, [pc, #12] ; (8002ff8 ) 8002fec: 751a strb r2, [r3, #20] batteryRefreshData(); 8002fee: f7fe fefb bl 8001de8 8002ff2: e7de b.n 8002fb2 systemShutDown(); 8002ff4: f7ff fefa bl 8002dec 8002ff8: 20000330 .word 0x20000330 8002ffc: 2000031a .word 0x2000031a 8003000: 10624dd3 .word 0x10624dd3 8003004: 0001d4bf .word 0x0001d4bf 8003008: 2000032a .word 0x2000032a 800300c: 2000031c .word 0x2000031c 08003010 : ** Abstract: Convert integer to ascii ** Returns: void **--------------------------------------------------------------------------- */ void ts_itoa(char **buf, unsigned int d, int base) { 8003010: b470 push {r4, r5, r6} int div = 1; 8003012: 2301 movs r3, #1 while (d/div >= base) 8003014: e001 b.n 800301a div *= base; 8003016: fb02 f303 mul.w r3, r2, r3 while (d/div >= base) 800301a: fbb1 f4f3 udiv r4, r1, r3 800301e: 4294 cmp r4, r2 8003020: d2f9 bcs.n 8003016 8003022: e004 b.n 800302e d = d%div; div /= base; if (num > 9) *((*buf)++) = (num-10) + 'A'; else *((*buf)++) = num + '0'; 8003024: 6805 ldr r5, [r0, #0] 8003026: 1c6e adds r6, r5, #1 8003028: 6006 str r6, [r0, #0] 800302a: 3430 adds r4, #48 ; 0x30 800302c: 702c strb r4, [r5, #0] while (div != 0) 800302e: b16b cbz r3, 800304c int num = d/div; 8003030: fbb1 f4f3 udiv r4, r1, r3 d = d%div; 8003034: fb03 1114 mls r1, r3, r4, r1 div /= base; 8003038: fb93 f3f2 sdiv r3, r3, r2 if (num > 9) 800303c: 2c09 cmp r4, #9 800303e: ddf1 ble.n 8003024 *((*buf)++) = (num-10) + 'A'; 8003040: 6805 ldr r5, [r0, #0] 8003042: 1c6e adds r6, r5, #1 8003044: 6006 str r6, [r0, #0] 8003046: 3437 adds r4, #55 ; 0x37 8003048: 702c strb r4, [r5, #0] 800304a: e7f0 b.n 800302e } } 800304c: bc70 pop {r4, r5, r6} 800304e: 4770 bx lr 08003050 : ** Abstract: Writes arguments va to buffer buf according to format fmt ** Returns: Length of string **--------------------------------------------------------------------------- */ int ts_formatstring(char *buf, const char *fmt, va_list va) { 8003050: b530 push {r4, r5, lr} 8003052: b083 sub sp, #12 8003054: 9001 str r0, [sp, #4] 8003056: 460c mov r4, r1 8003058: 9200 str r2, [sp, #0] char *start_buf = buf; 800305a: 4605 mov r5, r0 while(*fmt) 800305c: e03e b.n 80030dc { /* Character needs formating? */ if (*fmt == '%') { switch (*(++fmt)) 800305e: 7863 ldrb r3, [r4, #1] 8003060: 2b64 cmp r3, #100 ; 0x64 8003062: d01c beq.n 800309e 8003064: d90d bls.n 8003082 8003066: 2b73 cmp r3, #115 ; 0x73 8003068: d04a beq.n 8003100 800306a: d916 bls.n 800309a 800306c: 2b75 cmp r3, #117 ; 0x75 800306e: d121 bne.n 80030b4 *buf++ = *arg++; } } break; case 'u': ts_itoa(&buf, va_arg(va, unsigned int), 10); 8003070: 9b00 ldr r3, [sp, #0] 8003072: 1d1a adds r2, r3, #4 8003074: 9200 str r2, [sp, #0] 8003076: 220a movs r2, #10 8003078: 6819 ldr r1, [r3, #0] 800307a: a801 add r0, sp, #4 800307c: f7ff ffc8 bl 8003010 break; 8003080: e02b b.n 80030da switch (*(++fmt)) 8003082: 2b58 cmp r3, #88 ; 0x58 8003084: d018 beq.n 80030b8 8003086: 2b63 cmp r3, #99 ; 0x63 8003088: d01f beq.n 80030ca 800308a: 2b25 cmp r3, #37 ; 0x25 800308c: d125 bne.n 80030da case 'x': case 'X': ts_itoa(&buf, va_arg(va, int), 16); break; case '%': *buf++ = '%'; 800308e: 9b01 ldr r3, [sp, #4] 8003090: 1c5a adds r2, r3, #1 8003092: 9201 str r2, [sp, #4] 8003094: 2225 movs r2, #37 ; 0x25 8003096: 701a strb r2, [r3, #0] break; 8003098: e01f b.n 80030da switch (*(++fmt)) 800309a: 2b69 cmp r3, #105 ; 0x69 800309c: d11d bne.n 80030da signed int val = va_arg(va, signed int); 800309e: 9b00 ldr r3, [sp, #0] 80030a0: 1d1a adds r2, r3, #4 80030a2: 9200 str r2, [sp, #0] 80030a4: 6819 ldr r1, [r3, #0] if (val < 0) 80030a6: 2900 cmp r1, #0 80030a8: db23 blt.n 80030f2 ts_itoa(&buf, val, 10); 80030aa: 220a movs r2, #10 80030ac: a801 add r0, sp, #4 80030ae: f7ff ffaf bl 8003010 break; 80030b2: e012 b.n 80030da switch (*(++fmt)) 80030b4: 2b78 cmp r3, #120 ; 0x78 80030b6: d110 bne.n 80030da ts_itoa(&buf, va_arg(va, int), 16); 80030b8: 9b00 ldr r3, [sp, #0] 80030ba: 1d1a adds r2, r3, #4 80030bc: 9200 str r2, [sp, #0] 80030be: 2210 movs r2, #16 80030c0: 6819 ldr r1, [r3, #0] 80030c2: a801 add r0, sp, #4 80030c4: f7ff ffa4 bl 8003010 break; 80030c8: e007 b.n 80030da *buf++ = va_arg(va, int); 80030ca: 9b01 ldr r3, [sp, #4] 80030cc: 1c5a adds r2, r3, #1 80030ce: 9201 str r2, [sp, #4] 80030d0: 9a00 ldr r2, [sp, #0] 80030d2: 1d11 adds r1, r2, #4 80030d4: 9100 str r1, [sp, #0] 80030d6: 6812 ldr r2, [r2, #0] 80030d8: 701a strb r2, [r3, #0] } fmt++; 80030da: 3402 adds r4, #2 while(*fmt) 80030dc: 7823 ldrb r3, [r4, #0] 80030de: b1f3 cbz r3, 800311e if (*fmt == '%') 80030e0: 2b25 cmp r3, #37 ; 0x25 80030e2: d0bc beq.n 800305e } /* Else just copy */ else { *buf++ = *fmt++; 80030e4: 9b01 ldr r3, [sp, #4] 80030e6: 1c5a adds r2, r3, #1 80030e8: 9201 str r2, [sp, #4] 80030ea: 7822 ldrb r2, [r4, #0] 80030ec: 701a strb r2, [r3, #0] 80030ee: 3401 adds r4, #1 80030f0: e7f4 b.n 80030dc val *= -1; 80030f2: 4249 negs r1, r1 *buf++ = '-'; 80030f4: 9b01 ldr r3, [sp, #4] 80030f6: 1c5a adds r2, r3, #1 80030f8: 9201 str r2, [sp, #4] 80030fa: 222d movs r2, #45 ; 0x2d 80030fc: 701a strb r2, [r3, #0] 80030fe: e7d4 b.n 80030aa char * arg = va_arg(va, char *); 8003100: 9b00 ldr r3, [sp, #0] 8003102: 1d1a adds r2, r3, #4 8003104: 9200 str r2, [sp, #0] 8003106: 681b ldr r3, [r3, #0] while (*arg) 8003108: e005 b.n 8003116 *buf++ = *arg++; 800310a: 9a01 ldr r2, [sp, #4] 800310c: 1c51 adds r1, r2, #1 800310e: 9101 str r1, [sp, #4] 8003110: 7819 ldrb r1, [r3, #0] 8003112: 7011 strb r1, [r2, #0] 8003114: 3301 adds r3, #1 while (*arg) 8003116: 781a ldrb r2, [r3, #0] 8003118: 2a00 cmp r2, #0 800311a: d1f6 bne.n 800310a 800311c: e7dd b.n 80030da } } *buf = 0; 800311e: 2200 movs r2, #0 8003120: 9b01 ldr r3, [sp, #4] 8003122: 701a strb r2, [r3, #0] return (int)(buf - start_buf); } 8003124: 9801 ldr r0, [sp, #4] 8003126: 1b40 subs r0, r0, r5 8003128: b003 add sp, #12 800312a: bd30 pop {r4, r5, pc} 0800312c : ** given character string according to the format parameter. ** Returns: Number of bytes written **=========================================================================== */ int siprintf(char *buf, const char *fmt, ...) { 800312c: b40e push {r1, r2, r3} 800312e: b500 push {lr} 8003130: b082 sub sp, #8 8003132: aa03 add r2, sp, #12 8003134: f852 1b04 ldr.w r1, [r2], #4 int length; va_list va; va_start(va, fmt); 8003138: 9201 str r2, [sp, #4] length = ts_formatstring(buf, fmt, va); 800313a: f7ff ff89 bl 8003050 va_end(va); return length; } 800313e: b002 add sp, #8 8003140: f85d eb04 ldr.w lr, [sp], #4 8003144: b003 add sp, #12 8003146: 4770 bx lr 08003148 : * @param Aucun * @retval Aucun */ void usartConfigure(void) { 8003148: b5f0 push {r4, r5, r6, r7, lr} 800314a: b087 sub sp, #28 GPIO_InitTypeDef Init_Structure; NVIC_InitTypeDef NVIC_InitStructure; // Configure les lignes d'E/S // Configure Output ALTERNATE FONCTION PPULL PORT B6 Tx Init_Structure.GPIO_Pin = GPIO_Pin_6; 800314c: 2340 movs r3, #64 ; 0x40 800314e: f8ad 3004 strh.w r3, [sp, #4] Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP; 8003152: 2318 movs r3, #24 8003154: f88d 3007 strb.w r3, [sp, #7] Init_Structure.GPIO_Speed=GPIO_Speed_50MHz; 8003158: 2303 movs r3, #3 800315a: f88d 3006 strb.w r3, [sp, #6] GPIO_Init(GPIOB, &Init_Structure); 800315e: 4c23 ldr r4, [pc, #140] ; (80031ec ) 8003160: a901 add r1, sp, #4 8003162: 4620 mov r0, r4 8003164: f7fe f8f2 bl 800134c // Configure B7 Rx Init_Structure.GPIO_Pin = GPIO_Pin_7; 8003168: 2780 movs r7, #128 ; 0x80 800316a: f8ad 7004 strh.w r7, [sp, #4] Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 800316e: 2604 movs r6, #4 8003170: f88d 6007 strb.w r6, [sp, #7] GPIO_Init(GPIOB, &Init_Structure); 8003174: eb0d 0106 add.w r1, sp, r6 8003178: 4620 mov r0, r4 800317a: f7fe f8e7 bl 800134c // Configure l'USART USART_InitStructure.USART_BaudRate = 9600; 800317e: f44f 5316 mov.w r3, #9600 ; 0x2580 8003182: 9302 str r3, [sp, #8] USART_InitStructure.USART_WordLength = USART_WordLength_8b; 8003184: 2400 movs r4, #0 8003186: f8ad 400c strh.w r4, [sp, #12] USART_InitStructure.USART_StopBits = USART_StopBits_1; 800318a: f8ad 400e strh.w r4, [sp, #14] USART_InitStructure.USART_Parity = USART_Parity_No; 800318e: f8ad 4010 strh.w r4, [sp, #16] USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 8003192: f8ad 4014 strh.w r4, [sp, #20] USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 8003196: 230c movs r3, #12 8003198: f8ad 3012 strh.w r3, [sp, #18] USART_Init(USART1, &USART_InitStructure); 800319c: 4d14 ldr r5, [pc, #80] ; (80031f0 ) 800319e: a902 add r1, sp, #8 80031a0: 4628 mov r0, r5 80031a2: f7fe fc8f bl 8001ac4 USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); 80031a6: 2201 movs r2, #1 80031a8: 4639 mov r1, r7 80031aa: 4628 mov r0, r5 80031ac: f7fe fd18 bl 8001be0 USART_Cmd(USART1, ENABLE); 80031b0: 2101 movs r1, #1 80031b2: 4628 mov r0, r5 80031b4: f7fe fcea bl 8001b8c GPIO_PinRemapConfig(GPIO_Remap_USART1,ENABLE); 80031b8: 2101 movs r1, #1 80031ba: 4630 mov r0, r6 80031bc: f7fe f91a bl 80013f4 USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); 80031c0: 2201 movs r2, #1 80031c2: f240 5125 movw r1, #1317 ; 0x525 80031c6: 4628 mov r0, r5 80031c8: f7fe fcee bl 8001ba8 // configure les interruptions de l'USART NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; 80031cc: 2325 movs r3, #37 ; 0x25 80031ce: f88d 3000 strb.w r3, [sp] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; 80031d2: f88d 4001 strb.w r4, [sp, #1] NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 80031d6: f88d 4002 strb.w r4, [sp, #2] NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 80031da: 2301 movs r3, #1 80031dc: f88d 3003 strb.w r3, [sp, #3] NVIC_Init(&NVIC_InitStructure); 80031e0: 4668 mov r0, sp 80031e2: f7fd fea3 bl 8000f2c } 80031e6: b007 add sp, #28 80031e8: bdf0 pop {r4, r5, r6, r7, pc} 80031ea: bf00 nop 80031ec: 40010c00 .word 0x40010c00 80031f0: 40013800 .word 0x40013800 080031f4 : * * @param Aucun * @retval Aucun */ void usartInitDMA(uint16_t bufferSize) { 80031f4: b530 push {r4, r5, lr} 80031f6: b08d sub sp, #52 ; 0x34 80031f8: 4605 mov r5, r0 DMA_InitTypeDef DMA_InitStructure; DMA_DeInit(DMA1_Channel4); 80031fa: 4c0e ldr r4, [pc, #56] ; (8003234 ) 80031fc: 4620 mov r0, r4 80031fe: f7fd ff63 bl 80010c8 DMA_InitStructure.DMA_PeripheralBaseAddr = 0x40013804; 8003202: 4b0d ldr r3, [pc, #52] ; (8003238 ) 8003204: 9301 str r3, [sp, #4] DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)sendString; 8003206: 4b0d ldr r3, [pc, #52] ; (800323c ) 8003208: 9302 str r3, [sp, #8] DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; 800320a: 2310 movs r3, #16 800320c: 9303 str r3, [sp, #12] DMA_InitStructure.DMA_BufferSize = bufferSize; 800320e: 9504 str r5, [sp, #16] DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 8003210: 2300 movs r3, #0 8003212: 9305 str r3, [sp, #20] DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 8003214: 2280 movs r2, #128 ; 0x80 8003216: 9206 str r2, [sp, #24] DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; 8003218: 9307 str r3, [sp, #28] DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 800321a: 9308 str r3, [sp, #32] DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; 800321c: 9309 str r3, [sp, #36] ; 0x24 DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; 800321e: f44f 5240 mov.w r2, #12288 ; 0x3000 8003222: 920a str r2, [sp, #40] ; 0x28 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 8003224: 930b str r3, [sp, #44] ; 0x2c DMA_Init(DMA1_Channel4, &DMA_InitStructure); 8003226: a901 add r1, sp, #4 8003228: 4620 mov r0, r4 800322a: f7fd ffe1 bl 80011f0 } 800322e: b00d add sp, #52 ; 0x34 8003230: bd30 pop {r4, r5, pc} 8003232: bf00 nop 8003234: 40020044 .word 0x40020044 8003238: 40013804 .word 0x40013804 800323c: 20000370 .word 0x20000370 08003240 : * @brief Chargement du buffer Tx dans la DMA et envoi via l'UART * * @param Aucun * @retval Aucun */ void usartSendData(void){ 8003240: b508 push {r3, lr} int taille; for(taille = 0; sendString[taille]!= '\r'; taille++); 8003242: 2000 movs r0, #0 8003244: e000 b.n 8003248 8003246: 3001 adds r0, #1 8003248: 4b10 ldr r3, [pc, #64] ; (800328c ) 800324a: 5c1b ldrb r3, [r3, r0] 800324c: 2b0d cmp r3, #13 800324e: d1fa bne.n 8003246 usartInitDMA(taille+1); 8003250: 3001 adds r0, #1 8003252: b280 uxth r0, r0 8003254: f7ff ffce bl 80031f4 DMA_Cmd(DMA1_Channel4, ENABLE); 8003258: 2101 movs r1, #1 800325a: 480d ldr r0, [pc, #52] ; (8003290 ) 800325c: f7fd ffe7 bl 800122e while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET); 8003260: f44f 5000 mov.w r0, #8192 ; 0x2000 8003264: f7fd fffa bl 800125c 8003268: 2800 cmp r0, #0 800326a: d0f9 beq.n 8003260 for(i=0; i) 8003270: 801a strh r2, [r3, #0] 8003272: e005 b.n 8003280 sendString[i]=0; 8003274: 2100 movs r1, #0 8003276: 4a05 ldr r2, [pc, #20] ; (800328c ) 8003278: 54d1 strb r1, [r2, r3] for(i=0; i) 800327e: 8013 strh r3, [r2, #0] 8003280: 4b04 ldr r3, [pc, #16] ; (8003294 ) 8003282: 881b ldrh r3, [r3, #0] 8003284: 2b1d cmp r3, #29 8003286: d9f5 bls.n 8003274 } 8003288: bd08 pop {r3, pc} 800328a: bf00 nop 800328c: 20000370 .word 0x20000370 8003290: 40020044 .word 0x40020044 8003294: 2000036a .word 0x2000036a 08003298 : { 8003298: b538 push {r3, r4, r5, lr} if (USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) { 800329a: f240 5125 movw r1, #1317 ; 0x525 800329e: 4829 ldr r0, [pc, #164] ; (8003344 ) 80032a0: f7fe fcb2 bl 8001c08 80032a4: b9d0 cbnz r0, 80032dc tmp = USART1->SR; 80032a6: 4827 ldr r0, [pc, #156] ; (8003344 ) 80032a8: 8802 ldrh r2, [r0, #0] 80032aa: b292 uxth r2, r2 80032ac: 4b26 ldr r3, [pc, #152] ; (8003348 ) 80032ae: 801a strh r2, [r3, #0] tmp = USART1->CR1; 80032b0: 8982 ldrh r2, [r0, #12] 80032b2: b292 uxth r2, r2 80032b4: 801a strh r2, [r3, #0] tmp = USART1->CR2; 80032b6: 8a02 ldrh r2, [r0, #16] 80032b8: b292 uxth r2, r2 80032ba: 801a strh r2, [r3, #0] tmp = USART1->CR3; 80032bc: 8a82 ldrh r2, [r0, #20] 80032be: b292 uxth r2, r2 80032c0: 801a strh r2, [r3, #0] tmp = USART1->BRR; 80032c2: 8902 ldrh r2, [r0, #8] 80032c4: b292 uxth r2, r2 80032c6: 801a strh r2, [r3, #0] tmp = USART1->GTPR; 80032c8: 8b02 ldrh r2, [r0, #24] 80032ca: b292 uxth r2, r2 80032cc: 801a strh r2, [r3, #0] tmp = USART1->SR; 80032ce: 8802 ldrh r2, [r0, #0] 80032d0: b292 uxth r2, r2 80032d2: 801a strh r2, [r3, #0] USART_ClearFlag(USART1, USART_FLAG_RXNE); 80032d4: 2120 movs r1, #32 80032d6: f7fe fc93 bl 8001c00 80032da: bd38 pop {r3, r4, r5, pc} receiptString[cpt_Rx] = USART_ReceiveData(USART1); 80032dc: 4c1b ldr r4, [pc, #108] ; (800334c ) 80032de: 8825 ldrh r5, [r4, #0] 80032e0: 4818 ldr r0, [pc, #96] ; (8003344 ) 80032e2: f7fe fc89 bl 8001bf8 80032e6: 4b1a ldr r3, [pc, #104] ; (8003350 ) 80032e8: 5558 strb r0, [r3, r5] if (cpt_Rx < 16) 80032ea: 8823 ldrh r3, [r4, #0] 80032ec: 2b0f cmp r3, #15 80032ee: d801 bhi.n 80032f4 cpt_Rx++; 80032f0: 3301 adds r3, #1 80032f2: 8023 strh r3, [r4, #0] if (receiptString[cpt_Rx - 1] == '\r') { 80032f4: 4b15 ldr r3, [pc, #84] ; (800334c ) 80032f6: 881b ldrh r3, [r3, #0] 80032f8: 3b01 subs r3, #1 80032fa: 4a15 ldr r2, [pc, #84] ; (8003350 ) 80032fc: 5cd3 ldrb r3, [r2, r3] 80032fe: 2b0d cmp r3, #13 8003300: d1d1 bne.n 80032a6 cmdManage(); 8003302: f7ff f861 bl 80023c8 if (Dumber.AddOn == FALSE) { 8003306: 4b13 ldr r3, [pc, #76] ; (8003354 ) 8003308: 795b ldrb r3, [r3, #5] 800330a: 2b32 cmp r3, #50 ; 0x32 800330c: d003 beq.n 8003316 for (i = 0; i < cpt_Rx + 1; i++) 800330e: 2200 movs r2, #0 8003310: 4b11 ldr r3, [pc, #68] ; (8003358 ) 8003312: 801a strh r2, [r3, #0] 8003314: e00a b.n 800332c cmdAddChecksum(); 8003316: f7fe fe2d bl 8001f74 usartSendData(); // Fonction bloquante 800331a: f7ff ff91 bl 8003240 800331e: e7f6 b.n 800330e receiptString[i] = 0; 8003320: 2100 movs r1, #0 8003322: 4a0b ldr r2, [pc, #44] ; (8003350 ) 8003324: 54d1 strb r1, [r2, r3] for (i = 0; i < cpt_Rx + 1; i++) 8003326: 3301 adds r3, #1 8003328: 4a0b ldr r2, [pc, #44] ; (8003358 ) 800332a: 8013 strh r3, [r2, #0] 800332c: 4b0a ldr r3, [pc, #40] ; (8003358 ) 800332e: 881b ldrh r3, [r3, #0] 8003330: 4a06 ldr r2, [pc, #24] ; (800334c ) 8003332: 8812 ldrh r2, [r2, #0] 8003334: 3201 adds r2, #1 8003336: 4293 cmp r3, r2 8003338: dbf2 blt.n 8003320 cpt_Rx = 0; 800333a: 2200 movs r2, #0 800333c: 4b03 ldr r3, [pc, #12] ; (800334c ) 800333e: 801a strh r2, [r3, #0] 8003340: e7b1 b.n 80032a6 8003342: bf00 nop 8003344: 40013800 .word 0x40013800 8003348: 20000348 .word 0x20000348 800334c: 2000022c .word 0x2000022c 8003350: 2000034c .word 0x2000034c 8003354: 20000330 .word 0x20000330 8003358: 2000036a .word 0x2000036a 0800335c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 800335c: f8df d034 ldr.w sp, [pc, #52] ; 8003394 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8003360: 2100 movs r1, #0 b LoopCopyDataInit 8003362: e003 b.n 800336c 08003364 : CopyDataInit: ldr r3, =_sidata 8003364: 4b0c ldr r3, [pc, #48] ; (8003398 ) ldr r3, [r3, r1] 8003366: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8003368: 5043 str r3, [r0, r1] adds r1, r1, #4 800336a: 3104 adds r1, #4 0800336c : LoopCopyDataInit: ldr r0, =_sdata 800336c: 480b ldr r0, [pc, #44] ; (800339c ) ldr r3, =_edata 800336e: 4b0c ldr r3, [pc, #48] ; (80033a0 ) adds r2, r0, r1 8003370: 1842 adds r2, r0, r1 cmp r2, r3 8003372: 429a cmp r2, r3 bcc CopyDataInit 8003374: d3f6 bcc.n 8003364 ldr r2, =_sbss 8003376: 4a0b ldr r2, [pc, #44] ; (80033a4 ) b LoopFillZerobss 8003378: e002 b.n 8003380 0800337a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800337a: 2300 movs r3, #0 str r3, [r2], #4 800337c: f842 3b04 str.w r3, [r2], #4 08003380 : LoopFillZerobss: ldr r3, = _ebss 8003380: 4b09 ldr r3, [pc, #36] ; (80033a8 ) cmp r2, r3 8003382: 429a cmp r2, r3 bcc FillZerobss 8003384: d3f9 bcc.n 800337a /* Call the clock system intitialization function.*/ bl SystemInit 8003386: f000 f813 bl 80033b0 /* Call static constructors */ bl __libc_init_array 800338a: f000 f837 bl 80033fc <__libc_init_array> /* Call the application's entry point.*/ bl main 800338e: f7ff f933 bl 80025f8
bx lr 8003392: 4770 bx lr ldr sp, =_estack /* Atollic update: set stack pointer */ 8003394: 20002800 .word 0x20002800 ldr r3, =_sidata 8003398: 08004248 .word 0x08004248 ldr r0, =_sdata 800339c: 20000000 .word 0x20000000 ldr r3, =_edata 80033a0: 200001ec .word 0x200001ec ldr r2, =_sbss 80033a4: 200001ec .word 0x200001ec ldr r3, = _ebss 80033a8: 20000394 .word 0x20000394 080033ac : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80033ac: e7fe b.n 80033ac ... 080033b0 : */ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 80033b0: 4b0f ldr r3, [pc, #60] ; (80033f0 ) 80033b2: 681a ldr r2, [r3, #0] 80033b4: f042 0201 orr.w r2, r2, #1 80033b8: 601a str r2, [r3, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 80033ba: 6859 ldr r1, [r3, #4] 80033bc: 4a0d ldr r2, [pc, #52] ; (80033f4 ) 80033be: 400a ands r2, r1 80033c0: 605a str r2, [r3, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 80033c2: 681a ldr r2, [r3, #0] 80033c4: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000 80033c8: f422 3280 bic.w r2, r2, #65536 ; 0x10000 80033cc: 601a str r2, [r3, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 80033ce: 681a ldr r2, [r3, #0] 80033d0: f422 2280 bic.w r2, r2, #262144 ; 0x40000 80033d4: 601a str r2, [r3, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 80033d6: 685a ldr r2, [r3, #4] 80033d8: f422 02fe bic.w r2, r2, #8323072 ; 0x7f0000 80033dc: 605a str r2, [r3, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 80033de: f44f 021f mov.w r2, #10420224 ; 0x9f0000 80033e2: 609a str r2, [r3, #8] SetSysClock(); #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 80033e4: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80033e8: 4b03 ldr r3, [pc, #12] ; (80033f8 ) 80033ea: 609a str r2, [r3, #8] 80033ec: 4770 bx lr 80033ee: bf00 nop 80033f0: 40021000 .word 0x40021000 80033f4: f8ff0000 .word 0xf8ff0000 80033f8: e000ed00 .word 0xe000ed00 080033fc <__libc_init_array>: 80033fc: b570 push {r4, r5, r6, lr} 80033fe: 2500 movs r5, #0 8003400: 4e0c ldr r6, [pc, #48] ; (8003434 <__libc_init_array+0x38>) 8003402: 4c0d ldr r4, [pc, #52] ; (8003438 <__libc_init_array+0x3c>) 8003404: 1ba4 subs r4, r4, r6 8003406: 10a4 asrs r4, r4, #2 8003408: 42a5 cmp r5, r4 800340a: d109 bne.n 8003420 <__libc_init_array+0x24> 800340c: f000 fe16 bl 800403c <_init> 8003410: 2500 movs r5, #0 8003412: 4e0a ldr r6, [pc, #40] ; (800343c <__libc_init_array+0x40>) 8003414: 4c0a ldr r4, [pc, #40] ; (8003440 <__libc_init_array+0x44>) 8003416: 1ba4 subs r4, r4, r6 8003418: 10a4 asrs r4, r4, #2 800341a: 42a5 cmp r5, r4 800341c: d105 bne.n 800342a <__libc_init_array+0x2e> 800341e: bd70 pop {r4, r5, r6, pc} 8003420: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8003424: 4798 blx r3 8003426: 3501 adds r5, #1 8003428: e7ee b.n 8003408 <__libc_init_array+0xc> 800342a: f856 3025 ldr.w r3, [r6, r5, lsl #2] 800342e: 4798 blx r3 8003430: 3501 adds r5, #1 8003432: e7f2 b.n 800341a <__libc_init_array+0x1e> 8003434: 08004240 .word 0x08004240 8003438: 08004240 .word 0x08004240 800343c: 08004240 .word 0x08004240 8003440: 08004244 .word 0x08004244 08003444 : 8003444: b40e push {r1, r2, r3} 8003446: f44f 7201 mov.w r2, #516 ; 0x204 800344a: b530 push {r4, r5, lr} 800344c: b09c sub sp, #112 ; 0x70 800344e: ac1f add r4, sp, #124 ; 0x7c 8003450: f854 5b04 ldr.w r5, [r4], #4 8003454: f8ad 2014 strh.w r2, [sp, #20] 8003458: 9002 str r0, [sp, #8] 800345a: 9006 str r0, [sp, #24] 800345c: f7fc fe78 bl 8000150 8003460: 4b0b ldr r3, [pc, #44] ; (8003490 ) 8003462: 9003 str r0, [sp, #12] 8003464: 930b str r3, [sp, #44] ; 0x2c 8003466: 2300 movs r3, #0 8003468: 930f str r3, [sp, #60] ; 0x3c 800346a: 9314 str r3, [sp, #80] ; 0x50 800346c: f64f 73ff movw r3, #65535 ; 0xffff 8003470: 9007 str r0, [sp, #28] 8003472: 4808 ldr r0, [pc, #32] ; (8003494 ) 8003474: f8ad 3016 strh.w r3, [sp, #22] 8003478: 462a mov r2, r5 800347a: 4623 mov r3, r4 800347c: a902 add r1, sp, #8 800347e: 6800 ldr r0, [r0, #0] 8003480: 9401 str r4, [sp, #4] 8003482: f000 f917 bl 80036b4 <__ssvfiscanf_r> 8003486: b01c add sp, #112 ; 0x70 8003488: e8bd 4030 ldmia.w sp!, {r4, r5, lr} 800348c: b003 add sp, #12 800348e: 4770 bx lr 8003490: 08003499 .word 0x08003499 8003494: 2000001c .word 0x2000001c 08003498 <__seofread>: 8003498: 2000 movs r0, #0 800349a: 4770 bx lr 0800349c : 800349c: 4603 mov r3, r0 800349e: f811 2b01 ldrb.w r2, [r1], #1 80034a2: f803 2b01 strb.w r2, [r3], #1 80034a6: 2a00 cmp r2, #0 80034a8: d1f9 bne.n 800349e 80034aa: 4770 bx lr 080034ac <_free_r>: 80034ac: b538 push {r3, r4, r5, lr} 80034ae: 4605 mov r5, r0 80034b0: 2900 cmp r1, #0 80034b2: d043 beq.n 800353c <_free_r+0x90> 80034b4: f851 3c04 ldr.w r3, [r1, #-4] 80034b8: 1f0c subs r4, r1, #4 80034ba: 2b00 cmp r3, #0 80034bc: bfb8 it lt 80034be: 18e4 addlt r4, r4, r3 80034c0: f000 fd7d bl 8003fbe <__malloc_lock> 80034c4: 4a1e ldr r2, [pc, #120] ; (8003540 <_free_r+0x94>) 80034c6: 6813 ldr r3, [r2, #0] 80034c8: 4610 mov r0, r2 80034ca: b933 cbnz r3, 80034da <_free_r+0x2e> 80034cc: 6063 str r3, [r4, #4] 80034ce: 6014 str r4, [r2, #0] 80034d0: 4628 mov r0, r5 80034d2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80034d6: f000 bd73 b.w 8003fc0 <__malloc_unlock> 80034da: 42a3 cmp r3, r4 80034dc: d90b bls.n 80034f6 <_free_r+0x4a> 80034de: 6821 ldr r1, [r4, #0] 80034e0: 1862 adds r2, r4, r1 80034e2: 4293 cmp r3, r2 80034e4: bf01 itttt eq 80034e6: 681a ldreq r2, [r3, #0] 80034e8: 685b ldreq r3, [r3, #4] 80034ea: 1852 addeq r2, r2, r1 80034ec: 6022 streq r2, [r4, #0] 80034ee: 6063 str r3, [r4, #4] 80034f0: 6004 str r4, [r0, #0] 80034f2: e7ed b.n 80034d0 <_free_r+0x24> 80034f4: 4613 mov r3, r2 80034f6: 685a ldr r2, [r3, #4] 80034f8: b10a cbz r2, 80034fe <_free_r+0x52> 80034fa: 42a2 cmp r2, r4 80034fc: d9fa bls.n 80034f4 <_free_r+0x48> 80034fe: 6819 ldr r1, [r3, #0] 8003500: 1858 adds r0, r3, r1 8003502: 42a0 cmp r0, r4 8003504: d10b bne.n 800351e <_free_r+0x72> 8003506: 6820 ldr r0, [r4, #0] 8003508: 4401 add r1, r0 800350a: 1858 adds r0, r3, r1 800350c: 4282 cmp r2, r0 800350e: 6019 str r1, [r3, #0] 8003510: d1de bne.n 80034d0 <_free_r+0x24> 8003512: 6810 ldr r0, [r2, #0] 8003514: 6852 ldr r2, [r2, #4] 8003516: 4401 add r1, r0 8003518: 6019 str r1, [r3, #0] 800351a: 605a str r2, [r3, #4] 800351c: e7d8 b.n 80034d0 <_free_r+0x24> 800351e: d902 bls.n 8003526 <_free_r+0x7a> 8003520: 230c movs r3, #12 8003522: 602b str r3, [r5, #0] 8003524: e7d4 b.n 80034d0 <_free_r+0x24> 8003526: 6820 ldr r0, [r4, #0] 8003528: 1821 adds r1, r4, r0 800352a: 428a cmp r2, r1 800352c: bf01 itttt eq 800352e: 6811 ldreq r1, [r2, #0] 8003530: 6852 ldreq r2, [r2, #4] 8003532: 1809 addeq r1, r1, r0 8003534: 6021 streq r1, [r4, #0] 8003536: 6062 str r2, [r4, #4] 8003538: 605c str r4, [r3, #4] 800353a: e7c9 b.n 80034d0 <_free_r+0x24> 800353c: bd38 pop {r3, r4, r5, pc} 800353e: bf00 nop 8003540: 20000230 .word 0x20000230 08003544 <_malloc_r>: 8003544: b570 push {r4, r5, r6, lr} 8003546: 1ccd adds r5, r1, #3 8003548: f025 0503 bic.w r5, r5, #3 800354c: 3508 adds r5, #8 800354e: 2d0c cmp r5, #12 8003550: bf38 it cc 8003552: 250c movcc r5, #12 8003554: 2d00 cmp r5, #0 8003556: 4606 mov r6, r0 8003558: db01 blt.n 800355e <_malloc_r+0x1a> 800355a: 42a9 cmp r1, r5 800355c: d903 bls.n 8003566 <_malloc_r+0x22> 800355e: 230c movs r3, #12 8003560: 6033 str r3, [r6, #0] 8003562: 2000 movs r0, #0 8003564: bd70 pop {r4, r5, r6, pc} 8003566: f000 fd2a bl 8003fbe <__malloc_lock> 800356a: 4a23 ldr r2, [pc, #140] ; (80035f8 <_malloc_r+0xb4>) 800356c: 6814 ldr r4, [r2, #0] 800356e: 4621 mov r1, r4 8003570: b991 cbnz r1, 8003598 <_malloc_r+0x54> 8003572: 4c22 ldr r4, [pc, #136] ; (80035fc <_malloc_r+0xb8>) 8003574: 6823 ldr r3, [r4, #0] 8003576: b91b cbnz r3, 8003580 <_malloc_r+0x3c> 8003578: 4630 mov r0, r6 800357a: f000 fb49 bl 8003c10 <_sbrk_r> 800357e: 6020 str r0, [r4, #0] 8003580: 4629 mov r1, r5 8003582: 4630 mov r0, r6 8003584: f000 fb44 bl 8003c10 <_sbrk_r> 8003588: 1c43 adds r3, r0, #1 800358a: d126 bne.n 80035da <_malloc_r+0x96> 800358c: 230c movs r3, #12 800358e: 4630 mov r0, r6 8003590: 6033 str r3, [r6, #0] 8003592: f000 fd15 bl 8003fc0 <__malloc_unlock> 8003596: e7e4 b.n 8003562 <_malloc_r+0x1e> 8003598: 680b ldr r3, [r1, #0] 800359a: 1b5b subs r3, r3, r5 800359c: d41a bmi.n 80035d4 <_malloc_r+0x90> 800359e: 2b0b cmp r3, #11 80035a0: d90f bls.n 80035c2 <_malloc_r+0x7e> 80035a2: 600b str r3, [r1, #0] 80035a4: 18cc adds r4, r1, r3 80035a6: 50cd str r5, [r1, r3] 80035a8: 4630 mov r0, r6 80035aa: f000 fd09 bl 8003fc0 <__malloc_unlock> 80035ae: f104 000b add.w r0, r4, #11 80035b2: 1d23 adds r3, r4, #4 80035b4: f020 0007 bic.w r0, r0, #7 80035b8: 1ac3 subs r3, r0, r3 80035ba: d01b beq.n 80035f4 <_malloc_r+0xb0> 80035bc: 425a negs r2, r3 80035be: 50e2 str r2, [r4, r3] 80035c0: bd70 pop {r4, r5, r6, pc} 80035c2: 428c cmp r4, r1 80035c4: bf0b itete eq 80035c6: 6863 ldreq r3, [r4, #4] 80035c8: 684b ldrne r3, [r1, #4] 80035ca: 6013 streq r3, [r2, #0] 80035cc: 6063 strne r3, [r4, #4] 80035ce: bf18 it ne 80035d0: 460c movne r4, r1 80035d2: e7e9 b.n 80035a8 <_malloc_r+0x64> 80035d4: 460c mov r4, r1 80035d6: 6849 ldr r1, [r1, #4] 80035d8: e7ca b.n 8003570 <_malloc_r+0x2c> 80035da: 1cc4 adds r4, r0, #3 80035dc: f024 0403 bic.w r4, r4, #3 80035e0: 42a0 cmp r0, r4 80035e2: d005 beq.n 80035f0 <_malloc_r+0xac> 80035e4: 1a21 subs r1, r4, r0 80035e6: 4630 mov r0, r6 80035e8: f000 fb12 bl 8003c10 <_sbrk_r> 80035ec: 3001 adds r0, #1 80035ee: d0cd beq.n 800358c <_malloc_r+0x48> 80035f0: 6025 str r5, [r4, #0] 80035f2: e7d9 b.n 80035a8 <_malloc_r+0x64> 80035f4: bd70 pop {r4, r5, r6, pc} 80035f6: bf00 nop 80035f8: 20000230 .word 0x20000230 80035fc: 20000234 .word 0x20000234 08003600 <_sungetc_r>: 8003600: b538 push {r3, r4, r5, lr} 8003602: 1c4b adds r3, r1, #1 8003604: 4614 mov r4, r2 8003606: d103 bne.n 8003610 <_sungetc_r+0x10> 8003608: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff 800360c: 4628 mov r0, r5 800360e: bd38 pop {r3, r4, r5, pc} 8003610: 8993 ldrh r3, [r2, #12] 8003612: b2cd uxtb r5, r1 8003614: f023 0320 bic.w r3, r3, #32 8003618: 8193 strh r3, [r2, #12] 800361a: 6b53 ldr r3, [r2, #52] ; 0x34 800361c: 6852 ldr r2, [r2, #4] 800361e: b18b cbz r3, 8003644 <_sungetc_r+0x44> 8003620: 6ba3 ldr r3, [r4, #56] ; 0x38 8003622: 429a cmp r2, r3 8003624: da08 bge.n 8003638 <_sungetc_r+0x38> 8003626: 6823 ldr r3, [r4, #0] 8003628: 1e5a subs r2, r3, #1 800362a: 6022 str r2, [r4, #0] 800362c: f803 5c01 strb.w r5, [r3, #-1] 8003630: 6863 ldr r3, [r4, #4] 8003632: 3301 adds r3, #1 8003634: 6063 str r3, [r4, #4] 8003636: e7e9 b.n 800360c <_sungetc_r+0xc> 8003638: 4621 mov r1, r4 800363a: f000 fc4b bl 8003ed4 <__submore> 800363e: 2800 cmp r0, #0 8003640: d0f1 beq.n 8003626 <_sungetc_r+0x26> 8003642: e7e1 b.n 8003608 <_sungetc_r+0x8> 8003644: 6921 ldr r1, [r4, #16] 8003646: 6823 ldr r3, [r4, #0] 8003648: b151 cbz r1, 8003660 <_sungetc_r+0x60> 800364a: 4299 cmp r1, r3 800364c: d208 bcs.n 8003660 <_sungetc_r+0x60> 800364e: f813 1c01 ldrb.w r1, [r3, #-1] 8003652: 428d cmp r5, r1 8003654: d104 bne.n 8003660 <_sungetc_r+0x60> 8003656: 3b01 subs r3, #1 8003658: 3201 adds r2, #1 800365a: 6023 str r3, [r4, #0] 800365c: 6062 str r2, [r4, #4] 800365e: e7d5 b.n 800360c <_sungetc_r+0xc> 8003660: 63e3 str r3, [r4, #60] ; 0x3c 8003662: f104 0344 add.w r3, r4, #68 ; 0x44 8003666: 6363 str r3, [r4, #52] ; 0x34 8003668: 2303 movs r3, #3 800366a: 63a3 str r3, [r4, #56] ; 0x38 800366c: 4623 mov r3, r4 800366e: 6422 str r2, [r4, #64] ; 0x40 8003670: f803 5f46 strb.w r5, [r3, #70]! 8003674: 6023 str r3, [r4, #0] 8003676: 2301 movs r3, #1 8003678: e7dc b.n 8003634 <_sungetc_r+0x34> 0800367a <__ssrefill_r>: 800367a: b510 push {r4, lr} 800367c: 460c mov r4, r1 800367e: 6b49 ldr r1, [r1, #52] ; 0x34 8003680: b169 cbz r1, 800369e <__ssrefill_r+0x24> 8003682: f104 0344 add.w r3, r4, #68 ; 0x44 8003686: 4299 cmp r1, r3 8003688: d001 beq.n 800368e <__ssrefill_r+0x14> 800368a: f7ff ff0f bl 80034ac <_free_r> 800368e: 2000 movs r0, #0 8003690: 6c23 ldr r3, [r4, #64] ; 0x40 8003692: 6360 str r0, [r4, #52] ; 0x34 8003694: 6063 str r3, [r4, #4] 8003696: b113 cbz r3, 800369e <__ssrefill_r+0x24> 8003698: 6be3 ldr r3, [r4, #60] ; 0x3c 800369a: 6023 str r3, [r4, #0] 800369c: bd10 pop {r4, pc} 800369e: 6923 ldr r3, [r4, #16] 80036a0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80036a4: 6023 str r3, [r4, #0] 80036a6: 2300 movs r3, #0 80036a8: 6063 str r3, [r4, #4] 80036aa: 89a3 ldrh r3, [r4, #12] 80036ac: f043 0320 orr.w r3, r3, #32 80036b0: 81a3 strh r3, [r4, #12] 80036b2: bd10 pop {r4, pc} 080036b4 <__ssvfiscanf_r>: 80036b4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80036b8: f5ad 7d25 sub.w sp, sp, #660 ; 0x294 80036bc: 9301 str r3, [sp, #4] 80036be: 2300 movs r3, #0 80036c0: 4606 mov r6, r0 80036c2: 460c mov r4, r1 80036c4: 4692 mov sl, r2 80036c6: 270a movs r7, #10 80036c8: 9346 str r3, [sp, #280] ; 0x118 80036ca: 9347 str r3, [sp, #284] ; 0x11c 80036cc: 4b9f ldr r3, [pc, #636] ; (800394c <__ssvfiscanf_r+0x298>) 80036ce: f10d 080c add.w r8, sp, #12 80036d2: 93a2 str r3, [sp, #648] ; 0x288 80036d4: 4b9e ldr r3, [pc, #632] ; (8003950 <__ssvfiscanf_r+0x29c>) 80036d6: f8df 927c ldr.w r9, [pc, #636] ; 8003954 <__ssvfiscanf_r+0x2a0> 80036da: f8cd 8120 str.w r8, [sp, #288] ; 0x120 80036de: 93a3 str r3, [sp, #652] ; 0x28c 80036e0: f89a 3000 ldrb.w r3, [sl] 80036e4: 2b00 cmp r3, #0 80036e6: f000 812f beq.w 8003948 <__ssvfiscanf_r+0x294> 80036ea: f000 fc2f bl 8003f4c <__locale_ctype_ptr> 80036ee: f89a b000 ldrb.w fp, [sl] 80036f2: 4458 add r0, fp 80036f4: 7843 ldrb r3, [r0, #1] 80036f6: f013 0308 ands.w r3, r3, #8 80036fa: d143 bne.n 8003784 <__ssvfiscanf_r+0xd0> 80036fc: f1bb 0f25 cmp.w fp, #37 ; 0x25 8003700: f10a 0501 add.w r5, sl, #1 8003704: f040 8099 bne.w 800383a <__ssvfiscanf_r+0x186> 8003708: 9345 str r3, [sp, #276] ; 0x114 800370a: 9343 str r3, [sp, #268] ; 0x10c 800370c: f89a 3001 ldrb.w r3, [sl, #1] 8003710: 2b2a cmp r3, #42 ; 0x2a 8003712: d103 bne.n 800371c <__ssvfiscanf_r+0x68> 8003714: 2310 movs r3, #16 8003716: f10a 0502 add.w r5, sl, #2 800371a: 9343 str r3, [sp, #268] ; 0x10c 800371c: 7829 ldrb r1, [r5, #0] 800371e: 46aa mov sl, r5 8003720: f1a1 0230 sub.w r2, r1, #48 ; 0x30 8003724: 2a09 cmp r2, #9 8003726: f105 0501 add.w r5, r5, #1 800372a: d941 bls.n 80037b0 <__ssvfiscanf_r+0xfc> 800372c: 2203 movs r2, #3 800372e: 4889 ldr r0, [pc, #548] ; (8003954 <__ssvfiscanf_r+0x2a0>) 8003730: f000 fc2c bl 8003f8c 8003734: b138 cbz r0, 8003746 <__ssvfiscanf_r+0x92> 8003736: eba0 0309 sub.w r3, r0, r9 800373a: 2001 movs r0, #1 800373c: 46aa mov sl, r5 800373e: 4098 lsls r0, r3 8003740: 9b43 ldr r3, [sp, #268] ; 0x10c 8003742: 4318 orrs r0, r3 8003744: 9043 str r0, [sp, #268] ; 0x10c 8003746: f89a 3000 ldrb.w r3, [sl] 800374a: f10a 0501 add.w r5, sl, #1 800374e: 2b67 cmp r3, #103 ; 0x67 8003750: d84a bhi.n 80037e8 <__ssvfiscanf_r+0x134> 8003752: 2b65 cmp r3, #101 ; 0x65 8003754: f080 80b7 bcs.w 80038c6 <__ssvfiscanf_r+0x212> 8003758: 2b47 cmp r3, #71 ; 0x47 800375a: d82f bhi.n 80037bc <__ssvfiscanf_r+0x108> 800375c: 2b45 cmp r3, #69 ; 0x45 800375e: f080 80b2 bcs.w 80038c6 <__ssvfiscanf_r+0x212> 8003762: 2b00 cmp r3, #0 8003764: f000 8082 beq.w 800386c <__ssvfiscanf_r+0x1b8> 8003768: 2b25 cmp r3, #37 ; 0x25 800376a: d066 beq.n 800383a <__ssvfiscanf_r+0x186> 800376c: 2303 movs r3, #3 800376e: 9744 str r7, [sp, #272] ; 0x110 8003770: 9349 str r3, [sp, #292] ; 0x124 8003772: e045 b.n 8003800 <__ssvfiscanf_r+0x14c> 8003774: 9947 ldr r1, [sp, #284] ; 0x11c 8003776: 3301 adds r3, #1 8003778: 3101 adds r1, #1 800377a: 9147 str r1, [sp, #284] ; 0x11c 800377c: 6861 ldr r1, [r4, #4] 800377e: 6023 str r3, [r4, #0] 8003780: 3901 subs r1, #1 8003782: 6061 str r1, [r4, #4] 8003784: 6863 ldr r3, [r4, #4] 8003786: 2b00 cmp r3, #0 8003788: dd0b ble.n 80037a2 <__ssvfiscanf_r+0xee> 800378a: f000 fbdf bl 8003f4c <__locale_ctype_ptr> 800378e: 6823 ldr r3, [r4, #0] 8003790: 7819 ldrb r1, [r3, #0] 8003792: 4408 add r0, r1 8003794: 7841 ldrb r1, [r0, #1] 8003796: 070d lsls r5, r1, #28 8003798: d4ec bmi.n 8003774 <__ssvfiscanf_r+0xc0> 800379a: f10a 0501 add.w r5, sl, #1 800379e: 46aa mov sl, r5 80037a0: e79e b.n 80036e0 <__ssvfiscanf_r+0x2c> 80037a2: 9ba3 ldr r3, [sp, #652] ; 0x28c 80037a4: 4621 mov r1, r4 80037a6: 4630 mov r0, r6 80037a8: 4798 blx r3 80037aa: 2800 cmp r0, #0 80037ac: d0ed beq.n 800378a <__ssvfiscanf_r+0xd6> 80037ae: e7f4 b.n 800379a <__ssvfiscanf_r+0xe6> 80037b0: 9b45 ldr r3, [sp, #276] ; 0x114 80037b2: fb07 1303 mla r3, r7, r3, r1 80037b6: 3b30 subs r3, #48 ; 0x30 80037b8: 9345 str r3, [sp, #276] ; 0x114 80037ba: e7af b.n 800371c <__ssvfiscanf_r+0x68> 80037bc: 2b5b cmp r3, #91 ; 0x5b 80037be: d061 beq.n 8003884 <__ssvfiscanf_r+0x1d0> 80037c0: d80c bhi.n 80037dc <__ssvfiscanf_r+0x128> 80037c2: 2b58 cmp r3, #88 ; 0x58 80037c4: d1d2 bne.n 800376c <__ssvfiscanf_r+0xb8> 80037c6: 9a43 ldr r2, [sp, #268] ; 0x10c 80037c8: f442 7200 orr.w r2, r2, #512 ; 0x200 80037cc: 9243 str r2, [sp, #268] ; 0x10c 80037ce: 2210 movs r2, #16 80037d0: 9244 str r2, [sp, #272] ; 0x110 80037d2: 2b6f cmp r3, #111 ; 0x6f 80037d4: bfb4 ite lt 80037d6: 2303 movlt r3, #3 80037d8: 2304 movge r3, #4 80037da: e010 b.n 80037fe <__ssvfiscanf_r+0x14a> 80037dc: 2b63 cmp r3, #99 ; 0x63 80037de: d05c beq.n 800389a <__ssvfiscanf_r+0x1e6> 80037e0: 2b64 cmp r3, #100 ; 0x64 80037e2: d1c3 bne.n 800376c <__ssvfiscanf_r+0xb8> 80037e4: 9744 str r7, [sp, #272] ; 0x110 80037e6: e7f4 b.n 80037d2 <__ssvfiscanf_r+0x11e> 80037e8: 2b70 cmp r3, #112 ; 0x70 80037ea: d042 beq.n 8003872 <__ssvfiscanf_r+0x1be> 80037ec: d81d bhi.n 800382a <__ssvfiscanf_r+0x176> 80037ee: 2b6e cmp r3, #110 ; 0x6e 80037f0: d059 beq.n 80038a6 <__ssvfiscanf_r+0x1f2> 80037f2: d843 bhi.n 800387c <__ssvfiscanf_r+0x1c8> 80037f4: 2b69 cmp r3, #105 ; 0x69 80037f6: d1b9 bne.n 800376c <__ssvfiscanf_r+0xb8> 80037f8: 2300 movs r3, #0 80037fa: 9344 str r3, [sp, #272] ; 0x110 80037fc: 2303 movs r3, #3 80037fe: 9349 str r3, [sp, #292] ; 0x124 8003800: 6863 ldr r3, [r4, #4] 8003802: 2b00 cmp r3, #0 8003804: dd61 ble.n 80038ca <__ssvfiscanf_r+0x216> 8003806: 9b43 ldr r3, [sp, #268] ; 0x10c 8003808: 0659 lsls r1, r3, #25 800380a: d56f bpl.n 80038ec <__ssvfiscanf_r+0x238> 800380c: 9b49 ldr r3, [sp, #292] ; 0x124 800380e: 2b02 cmp r3, #2 8003810: dc7c bgt.n 800390c <__ssvfiscanf_r+0x258> 8003812: ab01 add r3, sp, #4 8003814: 4622 mov r2, r4 8003816: a943 add r1, sp, #268 ; 0x10c 8003818: 4630 mov r0, r6 800381a: f000 f89f bl 800395c <_scanf_chars> 800381e: 2801 cmp r0, #1 8003820: f000 8092 beq.w 8003948 <__ssvfiscanf_r+0x294> 8003824: 2802 cmp r0, #2 8003826: d1ba bne.n 800379e <__ssvfiscanf_r+0xea> 8003828: e01d b.n 8003866 <__ssvfiscanf_r+0x1b2> 800382a: 2b75 cmp r3, #117 ; 0x75 800382c: d0da beq.n 80037e4 <__ssvfiscanf_r+0x130> 800382e: 2b78 cmp r3, #120 ; 0x78 8003830: d0c9 beq.n 80037c6 <__ssvfiscanf_r+0x112> 8003832: 2b73 cmp r3, #115 ; 0x73 8003834: d19a bne.n 800376c <__ssvfiscanf_r+0xb8> 8003836: 2302 movs r3, #2 8003838: e7e1 b.n 80037fe <__ssvfiscanf_r+0x14a> 800383a: 6863 ldr r3, [r4, #4] 800383c: 2b00 cmp r3, #0 800383e: dd0c ble.n 800385a <__ssvfiscanf_r+0x1a6> 8003840: 6823 ldr r3, [r4, #0] 8003842: 781a ldrb r2, [r3, #0] 8003844: 4593 cmp fp, r2 8003846: d17f bne.n 8003948 <__ssvfiscanf_r+0x294> 8003848: 3301 adds r3, #1 800384a: 6862 ldr r2, [r4, #4] 800384c: 6023 str r3, [r4, #0] 800384e: 9b47 ldr r3, [sp, #284] ; 0x11c 8003850: 3a01 subs r2, #1 8003852: 3301 adds r3, #1 8003854: 6062 str r2, [r4, #4] 8003856: 9347 str r3, [sp, #284] ; 0x11c 8003858: e7a1 b.n 800379e <__ssvfiscanf_r+0xea> 800385a: 9ba3 ldr r3, [sp, #652] ; 0x28c 800385c: 4621 mov r1, r4 800385e: 4630 mov r0, r6 8003860: 4798 blx r3 8003862: 2800 cmp r0, #0 8003864: d0ec beq.n 8003840 <__ssvfiscanf_r+0x18c> 8003866: 9846 ldr r0, [sp, #280] ; 0x118 8003868: 2800 cmp r0, #0 800386a: d163 bne.n 8003934 <__ssvfiscanf_r+0x280> 800386c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8003870: e066 b.n 8003940 <__ssvfiscanf_r+0x28c> 8003872: 9a43 ldr r2, [sp, #268] ; 0x10c 8003874: f042 0220 orr.w r2, r2, #32 8003878: 9243 str r2, [sp, #268] ; 0x10c 800387a: e7a4 b.n 80037c6 <__ssvfiscanf_r+0x112> 800387c: 2308 movs r3, #8 800387e: 9344 str r3, [sp, #272] ; 0x110 8003880: 2304 movs r3, #4 8003882: e7bc b.n 80037fe <__ssvfiscanf_r+0x14a> 8003884: 4629 mov r1, r5 8003886: 4640 mov r0, r8 8003888: f000 f9d2 bl 8003c30 <__sccl> 800388c: 9b43 ldr r3, [sp, #268] ; 0x10c 800388e: 4605 mov r5, r0 8003890: f043 0340 orr.w r3, r3, #64 ; 0x40 8003894: 9343 str r3, [sp, #268] ; 0x10c 8003896: 2301 movs r3, #1 8003898: e7b1 b.n 80037fe <__ssvfiscanf_r+0x14a> 800389a: 9b43 ldr r3, [sp, #268] ; 0x10c 800389c: f043 0340 orr.w r3, r3, #64 ; 0x40 80038a0: 9343 str r3, [sp, #268] ; 0x10c 80038a2: 2300 movs r3, #0 80038a4: e7ab b.n 80037fe <__ssvfiscanf_r+0x14a> 80038a6: 9a43 ldr r2, [sp, #268] ; 0x10c 80038a8: 06d0 lsls r0, r2, #27 80038aa: f53f af78 bmi.w 800379e <__ssvfiscanf_r+0xea> 80038ae: f012 0f01 tst.w r2, #1 80038b2: 9a01 ldr r2, [sp, #4] 80038b4: 9b47 ldr r3, [sp, #284] ; 0x11c 80038b6: f102 0104 add.w r1, r2, #4 80038ba: 9101 str r1, [sp, #4] 80038bc: 6812 ldr r2, [r2, #0] 80038be: bf14 ite ne 80038c0: 8013 strhne r3, [r2, #0] 80038c2: 6013 streq r3, [r2, #0] 80038c4: e76b b.n 800379e <__ssvfiscanf_r+0xea> 80038c6: 2305 movs r3, #5 80038c8: e799 b.n 80037fe <__ssvfiscanf_r+0x14a> 80038ca: 9ba3 ldr r3, [sp, #652] ; 0x28c 80038cc: 4621 mov r1, r4 80038ce: 4630 mov r0, r6 80038d0: 4798 blx r3 80038d2: 2800 cmp r0, #0 80038d4: d097 beq.n 8003806 <__ssvfiscanf_r+0x152> 80038d6: e7c6 b.n 8003866 <__ssvfiscanf_r+0x1b2> 80038d8: 9a47 ldr r2, [sp, #284] ; 0x11c 80038da: 3201 adds r2, #1 80038dc: 9247 str r2, [sp, #284] ; 0x11c 80038de: 6862 ldr r2, [r4, #4] 80038e0: 3a01 subs r2, #1 80038e2: 2a00 cmp r2, #0 80038e4: 6062 str r2, [r4, #4] 80038e6: dd0a ble.n 80038fe <__ssvfiscanf_r+0x24a> 80038e8: 3301 adds r3, #1 80038ea: 6023 str r3, [r4, #0] 80038ec: f000 fb2e bl 8003f4c <__locale_ctype_ptr> 80038f0: 6823 ldr r3, [r4, #0] 80038f2: 781a ldrb r2, [r3, #0] 80038f4: 4410 add r0, r2 80038f6: 7842 ldrb r2, [r0, #1] 80038f8: 0712 lsls r2, r2, #28 80038fa: d4ed bmi.n 80038d8 <__ssvfiscanf_r+0x224> 80038fc: e786 b.n 800380c <__ssvfiscanf_r+0x158> 80038fe: 9ba3 ldr r3, [sp, #652] ; 0x28c 8003900: 4621 mov r1, r4 8003902: 4630 mov r0, r6 8003904: 4798 blx r3 8003906: 2800 cmp r0, #0 8003908: d0f0 beq.n 80038ec <__ssvfiscanf_r+0x238> 800390a: e7ac b.n 8003866 <__ssvfiscanf_r+0x1b2> 800390c: 2b04 cmp r3, #4 800390e: dc06 bgt.n 800391e <__ssvfiscanf_r+0x26a> 8003910: ab01 add r3, sp, #4 8003912: 4622 mov r2, r4 8003914: a943 add r1, sp, #268 ; 0x10c 8003916: 4630 mov r0, r6 8003918: f000 f884 bl 8003a24 <_scanf_i> 800391c: e77f b.n 800381e <__ssvfiscanf_r+0x16a> 800391e: 4b0e ldr r3, [pc, #56] ; (8003958 <__ssvfiscanf_r+0x2a4>) 8003920: 2b00 cmp r3, #0 8003922: f43f af3c beq.w 800379e <__ssvfiscanf_r+0xea> 8003926: ab01 add r3, sp, #4 8003928: 4622 mov r2, r4 800392a: a943 add r1, sp, #268 ; 0x10c 800392c: 4630 mov r0, r6 800392e: f3af 8000 nop.w 8003932: e774 b.n 800381e <__ssvfiscanf_r+0x16a> 8003934: 89a3 ldrh r3, [r4, #12] 8003936: f013 0f40 tst.w r3, #64 ; 0x40 800393a: bf18 it ne 800393c: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8003940: f50d 7d25 add.w sp, sp, #660 ; 0x294 8003944: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003948: 9846 ldr r0, [sp, #280] ; 0x118 800394a: e7f9 b.n 8003940 <__ssvfiscanf_r+0x28c> 800394c: 08003601 .word 0x08003601 8003950: 0800367b .word 0x0800367b 8003954: 080040b4 .word 0x080040b4 8003958: 00000000 .word 0x00000000 0800395c <_scanf_chars>: 800395c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8003960: 4615 mov r5, r2 8003962: 688a ldr r2, [r1, #8] 8003964: 4680 mov r8, r0 8003966: 460c mov r4, r1 8003968: b932 cbnz r2, 8003978 <_scanf_chars+0x1c> 800396a: 698a ldr r2, [r1, #24] 800396c: 2a00 cmp r2, #0 800396e: bf0c ite eq 8003970: 2201 moveq r2, #1 8003972: f04f 32ff movne.w r2, #4294967295 ; 0xffffffff 8003976: 608a str r2, [r1, #8] 8003978: 2600 movs r6, #0 800397a: 6822 ldr r2, [r4, #0] 800397c: 06d1 lsls r1, r2, #27 800397e: bf5f itttt pl 8003980: 681a ldrpl r2, [r3, #0] 8003982: 1d11 addpl r1, r2, #4 8003984: 6019 strpl r1, [r3, #0] 8003986: 6817 ldrpl r7, [r2, #0] 8003988: 69a3 ldr r3, [r4, #24] 800398a: b1db cbz r3, 80039c4 <_scanf_chars+0x68> 800398c: 2b01 cmp r3, #1 800398e: d107 bne.n 80039a0 <_scanf_chars+0x44> 8003990: 682b ldr r3, [r5, #0] 8003992: 6962 ldr r2, [r4, #20] 8003994: 781b ldrb r3, [r3, #0] 8003996: 5cd3 ldrb r3, [r2, r3] 8003998: b9a3 cbnz r3, 80039c4 <_scanf_chars+0x68> 800399a: 2e00 cmp r6, #0 800399c: d131 bne.n 8003a02 <_scanf_chars+0xa6> 800399e: e006 b.n 80039ae <_scanf_chars+0x52> 80039a0: 2b02 cmp r3, #2 80039a2: d007 beq.n 80039b4 <_scanf_chars+0x58> 80039a4: 2e00 cmp r6, #0 80039a6: d12c bne.n 8003a02 <_scanf_chars+0xa6> 80039a8: 69a3 ldr r3, [r4, #24] 80039aa: 2b01 cmp r3, #1 80039ac: d129 bne.n 8003a02 <_scanf_chars+0xa6> 80039ae: 2001 movs r0, #1 80039b0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80039b4: f000 faca bl 8003f4c <__locale_ctype_ptr> 80039b8: 682b ldr r3, [r5, #0] 80039ba: 781b ldrb r3, [r3, #0] 80039bc: 4418 add r0, r3 80039be: 7843 ldrb r3, [r0, #1] 80039c0: 071b lsls r3, r3, #28 80039c2: d4ef bmi.n 80039a4 <_scanf_chars+0x48> 80039c4: 6823 ldr r3, [r4, #0] 80039c6: 3601 adds r6, #1 80039c8: 06da lsls r2, r3, #27 80039ca: bf5e ittt pl 80039cc: 682b ldrpl r3, [r5, #0] 80039ce: 781b ldrbpl r3, [r3, #0] 80039d0: 703b strbpl r3, [r7, #0] 80039d2: 682a ldr r2, [r5, #0] 80039d4: 686b ldr r3, [r5, #4] 80039d6: f102 0201 add.w r2, r2, #1 80039da: 602a str r2, [r5, #0] 80039dc: 68a2 ldr r2, [r4, #8] 80039de: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff 80039e2: f102 32ff add.w r2, r2, #4294967295 ; 0xffffffff 80039e6: 606b str r3, [r5, #4] 80039e8: bf58 it pl 80039ea: 3701 addpl r7, #1 80039ec: 60a2 str r2, [r4, #8] 80039ee: b142 cbz r2, 8003a02 <_scanf_chars+0xa6> 80039f0: 2b00 cmp r3, #0 80039f2: dcc9 bgt.n 8003988 <_scanf_chars+0x2c> 80039f4: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 80039f8: 4629 mov r1, r5 80039fa: 4640 mov r0, r8 80039fc: 4798 blx r3 80039fe: 2800 cmp r0, #0 8003a00: d0c2 beq.n 8003988 <_scanf_chars+0x2c> 8003a02: 6823 ldr r3, [r4, #0] 8003a04: f013 0310 ands.w r3, r3, #16 8003a08: d105 bne.n 8003a16 <_scanf_chars+0xba> 8003a0a: 68e2 ldr r2, [r4, #12] 8003a0c: 3201 adds r2, #1 8003a0e: 60e2 str r2, [r4, #12] 8003a10: 69a2 ldr r2, [r4, #24] 8003a12: b102 cbz r2, 8003a16 <_scanf_chars+0xba> 8003a14: 703b strb r3, [r7, #0] 8003a16: 6923 ldr r3, [r4, #16] 8003a18: 2000 movs r0, #0 8003a1a: 441e add r6, r3 8003a1c: 6126 str r6, [r4, #16] 8003a1e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} ... 08003a24 <_scanf_i>: 8003a24: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003a28: 460c mov r4, r1 8003a2a: 469a mov sl, r3 8003a2c: 4b74 ldr r3, [pc, #464] ; (8003c00 <_scanf_i+0x1dc>) 8003a2e: b087 sub sp, #28 8003a30: 4683 mov fp, r0 8003a32: 4616 mov r6, r2 8003a34: e893 0007 ldmia.w r3, {r0, r1, r2} 8003a38: ab03 add r3, sp, #12 8003a3a: 68a7 ldr r7, [r4, #8] 8003a3c: e883 0007 stmia.w r3, {r0, r1, r2} 8003a40: 4b70 ldr r3, [pc, #448] ; (8003c04 <_scanf_i+0x1e0>) 8003a42: 69a1 ldr r1, [r4, #24] 8003a44: 4a70 ldr r2, [pc, #448] ; (8003c08 <_scanf_i+0x1e4>) 8003a46: f104 091c add.w r9, r4, #28 8003a4a: 2903 cmp r1, #3 8003a4c: bf18 it ne 8003a4e: 461a movne r2, r3 8003a50: 1e7b subs r3, r7, #1 8003a52: f5b3 7fae cmp.w r3, #348 ; 0x15c 8003a56: bf84 itt hi 8003a58: f240 135d movwhi r3, #349 ; 0x15d 8003a5c: 60a3 strhi r3, [r4, #8] 8003a5e: 6823 ldr r3, [r4, #0] 8003a60: bf88 it hi 8003a62: f46f 75ae mvnhi.w r5, #348 ; 0x15c 8003a66: f443 6350 orr.w r3, r3, #3328 ; 0xd00 8003a6a: 6023 str r3, [r4, #0] 8003a6c: bf98 it ls 8003a6e: 2700 movls r7, #0 8003a70: 464b mov r3, r9 8003a72: f04f 0800 mov.w r8, #0 8003a76: 9200 str r2, [sp, #0] 8003a78: bf88 it hi 8003a7a: 197f addhi r7, r7, r5 8003a7c: 6831 ldr r1, [r6, #0] 8003a7e: 9301 str r3, [sp, #4] 8003a80: ab03 add r3, sp, #12 8003a82: f853 0028 ldr.w r0, [r3, r8, lsl #2] 8003a86: 2202 movs r2, #2 8003a88: 7809 ldrb r1, [r1, #0] 8003a8a: f000 fa7f bl 8003f8c 8003a8e: 9b01 ldr r3, [sp, #4] 8003a90: b328 cbz r0, 8003ade <_scanf_i+0xba> 8003a92: f1b8 0f01 cmp.w r8, #1 8003a96: d156 bne.n 8003b46 <_scanf_i+0x122> 8003a98: 6862 ldr r2, [r4, #4] 8003a9a: b92a cbnz r2, 8003aa8 <_scanf_i+0x84> 8003a9c: 2208 movs r2, #8 8003a9e: 6062 str r2, [r4, #4] 8003aa0: 6822 ldr r2, [r4, #0] 8003aa2: f442 7200 orr.w r2, r2, #512 ; 0x200 8003aa6: 6022 str r2, [r4, #0] 8003aa8: 6822 ldr r2, [r4, #0] 8003aaa: f422 62a0 bic.w r2, r2, #1280 ; 0x500 8003aae: 6022 str r2, [r4, #0] 8003ab0: 68a2 ldr r2, [r4, #8] 8003ab2: 1e51 subs r1, r2, #1 8003ab4: 60a1 str r1, [r4, #8] 8003ab6: b192 cbz r2, 8003ade <_scanf_i+0xba> 8003ab8: 6832 ldr r2, [r6, #0] 8003aba: 1c5d adds r5, r3, #1 8003abc: 1c51 adds r1, r2, #1 8003abe: 6031 str r1, [r6, #0] 8003ac0: 7812 ldrb r2, [r2, #0] 8003ac2: 701a strb r2, [r3, #0] 8003ac4: 6873 ldr r3, [r6, #4] 8003ac6: 3b01 subs r3, #1 8003ac8: 2b00 cmp r3, #0 8003aca: 6073 str r3, [r6, #4] 8003acc: dc06 bgt.n 8003adc <_scanf_i+0xb8> 8003ace: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 8003ad2: 4631 mov r1, r6 8003ad4: 4658 mov r0, fp 8003ad6: 4798 blx r3 8003ad8: 2800 cmp r0, #0 8003ada: d177 bne.n 8003bcc <_scanf_i+0x1a8> 8003adc: 462b mov r3, r5 8003ade: f108 0801 add.w r8, r8, #1 8003ae2: f1b8 0f03 cmp.w r8, #3 8003ae6: d1c9 bne.n 8003a7c <_scanf_i+0x58> 8003ae8: 6862 ldr r2, [r4, #4] 8003aea: b90a cbnz r2, 8003af0 <_scanf_i+0xcc> 8003aec: 220a movs r2, #10 8003aee: 6062 str r2, [r4, #4] 8003af0: 6862 ldr r2, [r4, #4] 8003af2: 4946 ldr r1, [pc, #280] ; (8003c0c <_scanf_i+0x1e8>) 8003af4: 6960 ldr r0, [r4, #20] 8003af6: 1a89 subs r1, r1, r2 8003af8: 9301 str r3, [sp, #4] 8003afa: f000 f899 bl 8003c30 <__sccl> 8003afe: 9b01 ldr r3, [sp, #4] 8003b00: f04f 0800 mov.w r8, #0 8003b04: 461d mov r5, r3 8003b06: 68a3 ldr r3, [r4, #8] 8003b08: 2b00 cmp r3, #0 8003b0a: d039 beq.n 8003b80 <_scanf_i+0x15c> 8003b0c: 6831 ldr r1, [r6, #0] 8003b0e: 6960 ldr r0, [r4, #20] 8003b10: 780a ldrb r2, [r1, #0] 8003b12: 5c80 ldrb r0, [r0, r2] 8003b14: 2800 cmp r0, #0 8003b16: d033 beq.n 8003b80 <_scanf_i+0x15c> 8003b18: 2a30 cmp r2, #48 ; 0x30 8003b1a: 6822 ldr r2, [r4, #0] 8003b1c: d121 bne.n 8003b62 <_scanf_i+0x13e> 8003b1e: 0510 lsls r0, r2, #20 8003b20: d51f bpl.n 8003b62 <_scanf_i+0x13e> 8003b22: f108 0801 add.w r8, r8, #1 8003b26: b117 cbz r7, 8003b2e <_scanf_i+0x10a> 8003b28: 3301 adds r3, #1 8003b2a: 3f01 subs r7, #1 8003b2c: 60a3 str r3, [r4, #8] 8003b2e: 6873 ldr r3, [r6, #4] 8003b30: 3b01 subs r3, #1 8003b32: 2b00 cmp r3, #0 8003b34: 6073 str r3, [r6, #4] 8003b36: dd1c ble.n 8003b72 <_scanf_i+0x14e> 8003b38: 6833 ldr r3, [r6, #0] 8003b3a: 3301 adds r3, #1 8003b3c: 6033 str r3, [r6, #0] 8003b3e: 68a3 ldr r3, [r4, #8] 8003b40: 3b01 subs r3, #1 8003b42: 60a3 str r3, [r4, #8] 8003b44: e7df b.n 8003b06 <_scanf_i+0xe2> 8003b46: f1b8 0f02 cmp.w r8, #2 8003b4a: d1b1 bne.n 8003ab0 <_scanf_i+0x8c> 8003b4c: 6822 ldr r2, [r4, #0] 8003b4e: f402 61c0 and.w r1, r2, #1536 ; 0x600 8003b52: f5b1 7f00 cmp.w r1, #512 ; 0x200 8003b56: d1c2 bne.n 8003ade <_scanf_i+0xba> 8003b58: 2110 movs r1, #16 8003b5a: f442 7280 orr.w r2, r2, #256 ; 0x100 8003b5e: 6061 str r1, [r4, #4] 8003b60: e7a5 b.n 8003aae <_scanf_i+0x8a> 8003b62: f422 6210 bic.w r2, r2, #2304 ; 0x900 8003b66: 6022 str r2, [r4, #0] 8003b68: 780b ldrb r3, [r1, #0] 8003b6a: 3501 adds r5, #1 8003b6c: f805 3c01 strb.w r3, [r5, #-1] 8003b70: e7dd b.n 8003b2e <_scanf_i+0x10a> 8003b72: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 8003b76: 4631 mov r1, r6 8003b78: 4658 mov r0, fp 8003b7a: 4798 blx r3 8003b7c: 2800 cmp r0, #0 8003b7e: d0de beq.n 8003b3e <_scanf_i+0x11a> 8003b80: 6823 ldr r3, [r4, #0] 8003b82: 05d9 lsls r1, r3, #23 8003b84: d50c bpl.n 8003ba0 <_scanf_i+0x17c> 8003b86: 454d cmp r5, r9 8003b88: d908 bls.n 8003b9c <_scanf_i+0x178> 8003b8a: f815 1c01 ldrb.w r1, [r5, #-1] 8003b8e: 1e6f subs r7, r5, #1 8003b90: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c 8003b94: 4632 mov r2, r6 8003b96: 4658 mov r0, fp 8003b98: 4798 blx r3 8003b9a: 463d mov r5, r7 8003b9c: 454d cmp r5, r9 8003b9e: d02c beq.n 8003bfa <_scanf_i+0x1d6> 8003ba0: 6822 ldr r2, [r4, #0] 8003ba2: f012 0210 ands.w r2, r2, #16 8003ba6: d11e bne.n 8003be6 <_scanf_i+0x1c2> 8003ba8: 702a strb r2, [r5, #0] 8003baa: 6863 ldr r3, [r4, #4] 8003bac: 4649 mov r1, r9 8003bae: 4658 mov r0, fp 8003bb0: 9e00 ldr r6, [sp, #0] 8003bb2: 47b0 blx r6 8003bb4: 6822 ldr r2, [r4, #0] 8003bb6: f8da 3000 ldr.w r3, [sl] 8003bba: f012 0f20 tst.w r2, #32 8003bbe: d008 beq.n 8003bd2 <_scanf_i+0x1ae> 8003bc0: 1d1a adds r2, r3, #4 8003bc2: f8ca 2000 str.w r2, [sl] 8003bc6: 681b ldr r3, [r3, #0] 8003bc8: 6018 str r0, [r3, #0] 8003bca: e009 b.n 8003be0 <_scanf_i+0x1bc> 8003bcc: f04f 0800 mov.w r8, #0 8003bd0: e7d6 b.n 8003b80 <_scanf_i+0x15c> 8003bd2: 07d2 lsls r2, r2, #31 8003bd4: d5f4 bpl.n 8003bc0 <_scanf_i+0x19c> 8003bd6: 1d1a adds r2, r3, #4 8003bd8: f8ca 2000 str.w r2, [sl] 8003bdc: 681b ldr r3, [r3, #0] 8003bde: 8018 strh r0, [r3, #0] 8003be0: 68e3 ldr r3, [r4, #12] 8003be2: 3301 adds r3, #1 8003be4: 60e3 str r3, [r4, #12] 8003be6: 2000 movs r0, #0 8003be8: eba5 0509 sub.w r5, r5, r9 8003bec: 44a8 add r8, r5 8003bee: 6925 ldr r5, [r4, #16] 8003bf0: 4445 add r5, r8 8003bf2: 6125 str r5, [r4, #16] 8003bf4: b007 add sp, #28 8003bf6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003bfa: 2001 movs r0, #1 8003bfc: e7fa b.n 8003bf4 <_scanf_i+0x1d0> 8003bfe: bf00 nop 8003c00: 08004054 .word 0x08004054 8003c04: 08003eb1 .word 0x08003eb1 8003c08: 08003d91 .word 0x08003d91 8003c0c: 080040c8 .word 0x080040c8 08003c10 <_sbrk_r>: 8003c10: b538 push {r3, r4, r5, lr} 8003c12: 2300 movs r3, #0 8003c14: 4c05 ldr r4, [pc, #20] ; (8003c2c <_sbrk_r+0x1c>) 8003c16: 4605 mov r5, r0 8003c18: 4608 mov r0, r1 8003c1a: 6023 str r3, [r4, #0] 8003c1c: f7ff f88a bl 8002d34 <_sbrk> 8003c20: 1c43 adds r3, r0, #1 8003c22: d102 bne.n 8003c2a <_sbrk_r+0x1a> 8003c24: 6823 ldr r3, [r4, #0] 8003c26: b103 cbz r3, 8003c2a <_sbrk_r+0x1a> 8003c28: 602b str r3, [r5, #0] 8003c2a: bd38 pop {r3, r4, r5, pc} 8003c2c: 20000390 .word 0x20000390 08003c30 <__sccl>: 8003c30: b570 push {r4, r5, r6, lr} 8003c32: 780b ldrb r3, [r1, #0] 8003c34: 1e44 subs r4, r0, #1 8003c36: 2b5e cmp r3, #94 ; 0x5e 8003c38: bf13 iteet ne 8003c3a: 1c4a addne r2, r1, #1 8003c3c: 1c8a addeq r2, r1, #2 8003c3e: 784b ldrbeq r3, [r1, #1] 8003c40: 2100 movne r1, #0 8003c42: bf08 it eq 8003c44: 2101 moveq r1, #1 8003c46: f100 05ff add.w r5, r0, #255 ; 0xff 8003c4a: f804 1f01 strb.w r1, [r4, #1]! 8003c4e: 42a5 cmp r5, r4 8003c50: d1fb bne.n 8003c4a <__sccl+0x1a> 8003c52: b913 cbnz r3, 8003c5a <__sccl+0x2a> 8003c54: 3a01 subs r2, #1 8003c56: 4610 mov r0, r2 8003c58: bd70 pop {r4, r5, r6, pc} 8003c5a: f081 0401 eor.w r4, r1, #1 8003c5e: 4611 mov r1, r2 8003c60: 54c4 strb r4, [r0, r3] 8003c62: 780d ldrb r5, [r1, #0] 8003c64: 1c4a adds r2, r1, #1 8003c66: 2d2d cmp r5, #45 ; 0x2d 8003c68: d006 beq.n 8003c78 <__sccl+0x48> 8003c6a: 2d5d cmp r5, #93 ; 0x5d 8003c6c: d0f3 beq.n 8003c56 <__sccl+0x26> 8003c6e: b90d cbnz r5, 8003c74 <__sccl+0x44> 8003c70: 460a mov r2, r1 8003c72: e7f0 b.n 8003c56 <__sccl+0x26> 8003c74: 462b mov r3, r5 8003c76: e7f2 b.n 8003c5e <__sccl+0x2e> 8003c78: 784e ldrb r6, [r1, #1] 8003c7a: 2e5d cmp r6, #93 ; 0x5d 8003c7c: d0fa beq.n 8003c74 <__sccl+0x44> 8003c7e: 42b3 cmp r3, r6 8003c80: dcf8 bgt.n 8003c74 <__sccl+0x44> 8003c82: 3102 adds r1, #2 8003c84: 3301 adds r3, #1 8003c86: 429e cmp r6, r3 8003c88: 54c4 strb r4, [r0, r3] 8003c8a: dcfb bgt.n 8003c84 <__sccl+0x54> 8003c8c: e7e9 b.n 8003c62 <__sccl+0x32> 08003c8e <_strtol_l.isra.0>: 8003c8e: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003c92: 4680 mov r8, r0 8003c94: 4689 mov r9, r1 8003c96: 4692 mov sl, r2 8003c98: 461f mov r7, r3 8003c9a: 468b mov fp, r1 8003c9c: 465d mov r5, fp 8003c9e: 980a ldr r0, [sp, #40] ; 0x28 8003ca0: f815 4b01 ldrb.w r4, [r5], #1 8003ca4: f000 f94f bl 8003f46 <__locale_ctype_ptr_l> 8003ca8: 4420 add r0, r4 8003caa: 7846 ldrb r6, [r0, #1] 8003cac: f016 0608 ands.w r6, r6, #8 8003cb0: d10b bne.n 8003cca <_strtol_l.isra.0+0x3c> 8003cb2: 2c2d cmp r4, #45 ; 0x2d 8003cb4: d10b bne.n 8003cce <_strtol_l.isra.0+0x40> 8003cb6: 2601 movs r6, #1 8003cb8: 782c ldrb r4, [r5, #0] 8003cba: f10b 0502 add.w r5, fp, #2 8003cbe: b167 cbz r7, 8003cda <_strtol_l.isra.0+0x4c> 8003cc0: 2f10 cmp r7, #16 8003cc2: d114 bne.n 8003cee <_strtol_l.isra.0+0x60> 8003cc4: 2c30 cmp r4, #48 ; 0x30 8003cc6: d00a beq.n 8003cde <_strtol_l.isra.0+0x50> 8003cc8: e011 b.n 8003cee <_strtol_l.isra.0+0x60> 8003cca: 46ab mov fp, r5 8003ccc: e7e6 b.n 8003c9c <_strtol_l.isra.0+0xe> 8003cce: 2c2b cmp r4, #43 ; 0x2b 8003cd0: bf04 itt eq 8003cd2: 782c ldrbeq r4, [r5, #0] 8003cd4: f10b 0502 addeq.w r5, fp, #2 8003cd8: e7f1 b.n 8003cbe <_strtol_l.isra.0+0x30> 8003cda: 2c30 cmp r4, #48 ; 0x30 8003cdc: d127 bne.n 8003d2e <_strtol_l.isra.0+0xa0> 8003cde: 782b ldrb r3, [r5, #0] 8003ce0: f003 03df and.w r3, r3, #223 ; 0xdf 8003ce4: 2b58 cmp r3, #88 ; 0x58 8003ce6: d14b bne.n 8003d80 <_strtol_l.isra.0+0xf2> 8003ce8: 2710 movs r7, #16 8003cea: 786c ldrb r4, [r5, #1] 8003cec: 3502 adds r5, #2 8003cee: 2e00 cmp r6, #0 8003cf0: bf0c ite eq 8003cf2: f06f 4100 mvneq.w r1, #2147483648 ; 0x80000000 8003cf6: f04f 4100 movne.w r1, #2147483648 ; 0x80000000 8003cfa: 2200 movs r2, #0 8003cfc: fbb1 fef7 udiv lr, r1, r7 8003d00: 4610 mov r0, r2 8003d02: fb07 1c1e mls ip, r7, lr, r1 8003d06: f1a4 0330 sub.w r3, r4, #48 ; 0x30 8003d0a: 2b09 cmp r3, #9 8003d0c: d811 bhi.n 8003d32 <_strtol_l.isra.0+0xa4> 8003d0e: 461c mov r4, r3 8003d10: 42a7 cmp r7, r4 8003d12: dd1d ble.n 8003d50 <_strtol_l.isra.0+0xc2> 8003d14: 1c53 adds r3, r2, #1 8003d16: d007 beq.n 8003d28 <_strtol_l.isra.0+0x9a> 8003d18: 4586 cmp lr, r0 8003d1a: d316 bcc.n 8003d4a <_strtol_l.isra.0+0xbc> 8003d1c: d101 bne.n 8003d22 <_strtol_l.isra.0+0x94> 8003d1e: 45a4 cmp ip, r4 8003d20: db13 blt.n 8003d4a <_strtol_l.isra.0+0xbc> 8003d22: 2201 movs r2, #1 8003d24: fb00 4007 mla r0, r0, r7, r4 8003d28: f815 4b01 ldrb.w r4, [r5], #1 8003d2c: e7eb b.n 8003d06 <_strtol_l.isra.0+0x78> 8003d2e: 270a movs r7, #10 8003d30: e7dd b.n 8003cee <_strtol_l.isra.0+0x60> 8003d32: f1a4 0341 sub.w r3, r4, #65 ; 0x41 8003d36: 2b19 cmp r3, #25 8003d38: d801 bhi.n 8003d3e <_strtol_l.isra.0+0xb0> 8003d3a: 3c37 subs r4, #55 ; 0x37 8003d3c: e7e8 b.n 8003d10 <_strtol_l.isra.0+0x82> 8003d3e: f1a4 0361 sub.w r3, r4, #97 ; 0x61 8003d42: 2b19 cmp r3, #25 8003d44: d804 bhi.n 8003d50 <_strtol_l.isra.0+0xc2> 8003d46: 3c57 subs r4, #87 ; 0x57 8003d48: e7e2 b.n 8003d10 <_strtol_l.isra.0+0x82> 8003d4a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8003d4e: e7eb b.n 8003d28 <_strtol_l.isra.0+0x9a> 8003d50: 1c53 adds r3, r2, #1 8003d52: d108 bne.n 8003d66 <_strtol_l.isra.0+0xd8> 8003d54: 2322 movs r3, #34 ; 0x22 8003d56: 4608 mov r0, r1 8003d58: f8c8 3000 str.w r3, [r8] 8003d5c: f1ba 0f00 cmp.w sl, #0 8003d60: d107 bne.n 8003d72 <_strtol_l.isra.0+0xe4> 8003d62: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003d66: b106 cbz r6, 8003d6a <_strtol_l.isra.0+0xdc> 8003d68: 4240 negs r0, r0 8003d6a: f1ba 0f00 cmp.w sl, #0 8003d6e: d00c beq.n 8003d8a <_strtol_l.isra.0+0xfc> 8003d70: b122 cbz r2, 8003d7c <_strtol_l.isra.0+0xee> 8003d72: 3d01 subs r5, #1 8003d74: f8ca 5000 str.w r5, [sl] 8003d78: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003d7c: 464d mov r5, r9 8003d7e: e7f9 b.n 8003d74 <_strtol_l.isra.0+0xe6> 8003d80: 2430 movs r4, #48 ; 0x30 8003d82: 2f00 cmp r7, #0 8003d84: d1b3 bne.n 8003cee <_strtol_l.isra.0+0x60> 8003d86: 2708 movs r7, #8 8003d88: e7b1 b.n 8003cee <_strtol_l.isra.0+0x60> 8003d8a: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} ... 08003d90 <_strtol_r>: 8003d90: b537 push {r0, r1, r2, r4, r5, lr} 8003d92: 4c06 ldr r4, [pc, #24] ; (8003dac <_strtol_r+0x1c>) 8003d94: 4d06 ldr r5, [pc, #24] ; (8003db0 <_strtol_r+0x20>) 8003d96: 6824 ldr r4, [r4, #0] 8003d98: 6a24 ldr r4, [r4, #32] 8003d9a: 2c00 cmp r4, #0 8003d9c: bf08 it eq 8003d9e: 462c moveq r4, r5 8003da0: 9400 str r4, [sp, #0] 8003da2: f7ff ff74 bl 8003c8e <_strtol_l.isra.0> 8003da6: b003 add sp, #12 8003da8: bd30 pop {r4, r5, pc} 8003daa: bf00 nop 8003dac: 2000001c .word 0x2000001c 8003db0: 20000080 .word 0x20000080 08003db4 <_strtoul_l.isra.0>: 8003db4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8003db8: 4680 mov r8, r0 8003dba: 4689 mov r9, r1 8003dbc: 4692 mov sl, r2 8003dbe: 461e mov r6, r3 8003dc0: 460f mov r7, r1 8003dc2: 463d mov r5, r7 8003dc4: 9808 ldr r0, [sp, #32] 8003dc6: f815 4b01 ldrb.w r4, [r5], #1 8003dca: f000 f8bc bl 8003f46 <__locale_ctype_ptr_l> 8003dce: 4420 add r0, r4 8003dd0: 7843 ldrb r3, [r0, #1] 8003dd2: f013 0308 ands.w r3, r3, #8 8003dd6: d10a bne.n 8003dee <_strtoul_l.isra.0+0x3a> 8003dd8: 2c2d cmp r4, #45 ; 0x2d 8003dda: d10a bne.n 8003df2 <_strtoul_l.isra.0+0x3e> 8003ddc: 2301 movs r3, #1 8003dde: 782c ldrb r4, [r5, #0] 8003de0: 1cbd adds r5, r7, #2 8003de2: b15e cbz r6, 8003dfc <_strtoul_l.isra.0+0x48> 8003de4: 2e10 cmp r6, #16 8003de6: d113 bne.n 8003e10 <_strtoul_l.isra.0+0x5c> 8003de8: 2c30 cmp r4, #48 ; 0x30 8003dea: d009 beq.n 8003e00 <_strtoul_l.isra.0+0x4c> 8003dec: e010 b.n 8003e10 <_strtoul_l.isra.0+0x5c> 8003dee: 462f mov r7, r5 8003df0: e7e7 b.n 8003dc2 <_strtoul_l.isra.0+0xe> 8003df2: 2c2b cmp r4, #43 ; 0x2b 8003df4: bf04 itt eq 8003df6: 782c ldrbeq r4, [r5, #0] 8003df8: 1cbd addeq r5, r7, #2 8003dfa: e7f2 b.n 8003de2 <_strtoul_l.isra.0+0x2e> 8003dfc: 2c30 cmp r4, #48 ; 0x30 8003dfe: d125 bne.n 8003e4c <_strtoul_l.isra.0+0x98> 8003e00: 782a ldrb r2, [r5, #0] 8003e02: f002 02df and.w r2, r2, #223 ; 0xdf 8003e06: 2a58 cmp r2, #88 ; 0x58 8003e08: d14a bne.n 8003ea0 <_strtoul_l.isra.0+0xec> 8003e0a: 2610 movs r6, #16 8003e0c: 786c ldrb r4, [r5, #1] 8003e0e: 3502 adds r5, #2 8003e10: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8003e14: fbb1 f1f6 udiv r1, r1, r6 8003e18: 2700 movs r7, #0 8003e1a: fb06 fe01 mul.w lr, r6, r1 8003e1e: 4638 mov r0, r7 8003e20: ea6f 0e0e mvn.w lr, lr 8003e24: f1a4 0230 sub.w r2, r4, #48 ; 0x30 8003e28: 2a09 cmp r2, #9 8003e2a: d811 bhi.n 8003e50 <_strtoul_l.isra.0+0x9c> 8003e2c: 4614 mov r4, r2 8003e2e: 42a6 cmp r6, r4 8003e30: dd1d ble.n 8003e6e <_strtoul_l.isra.0+0xba> 8003e32: 2f00 cmp r7, #0 8003e34: db18 blt.n 8003e68 <_strtoul_l.isra.0+0xb4> 8003e36: 4281 cmp r1, r0 8003e38: d316 bcc.n 8003e68 <_strtoul_l.isra.0+0xb4> 8003e3a: d101 bne.n 8003e40 <_strtoul_l.isra.0+0x8c> 8003e3c: 45a6 cmp lr, r4 8003e3e: db13 blt.n 8003e68 <_strtoul_l.isra.0+0xb4> 8003e40: 2701 movs r7, #1 8003e42: fb00 4006 mla r0, r0, r6, r4 8003e46: f815 4b01 ldrb.w r4, [r5], #1 8003e4a: e7eb b.n 8003e24 <_strtoul_l.isra.0+0x70> 8003e4c: 260a movs r6, #10 8003e4e: e7df b.n 8003e10 <_strtoul_l.isra.0+0x5c> 8003e50: f1a4 0241 sub.w r2, r4, #65 ; 0x41 8003e54: 2a19 cmp r2, #25 8003e56: d801 bhi.n 8003e5c <_strtoul_l.isra.0+0xa8> 8003e58: 3c37 subs r4, #55 ; 0x37 8003e5a: e7e8 b.n 8003e2e <_strtoul_l.isra.0+0x7a> 8003e5c: f1a4 0261 sub.w r2, r4, #97 ; 0x61 8003e60: 2a19 cmp r2, #25 8003e62: d804 bhi.n 8003e6e <_strtoul_l.isra.0+0xba> 8003e64: 3c57 subs r4, #87 ; 0x57 8003e66: e7e2 b.n 8003e2e <_strtoul_l.isra.0+0x7a> 8003e68: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 8003e6c: e7eb b.n 8003e46 <_strtoul_l.isra.0+0x92> 8003e6e: 2f00 cmp r7, #0 8003e70: da09 bge.n 8003e86 <_strtoul_l.isra.0+0xd2> 8003e72: 2322 movs r3, #34 ; 0x22 8003e74: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8003e78: f8c8 3000 str.w r3, [r8] 8003e7c: f1ba 0f00 cmp.w sl, #0 8003e80: d107 bne.n 8003e92 <_strtoul_l.isra.0+0xde> 8003e82: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8003e86: b103 cbz r3, 8003e8a <_strtoul_l.isra.0+0xd6> 8003e88: 4240 negs r0, r0 8003e8a: f1ba 0f00 cmp.w sl, #0 8003e8e: d00c beq.n 8003eaa <_strtoul_l.isra.0+0xf6> 8003e90: b127 cbz r7, 8003e9c <_strtoul_l.isra.0+0xe8> 8003e92: 3d01 subs r5, #1 8003e94: f8ca 5000 str.w r5, [sl] 8003e98: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8003e9c: 464d mov r5, r9 8003e9e: e7f9 b.n 8003e94 <_strtoul_l.isra.0+0xe0> 8003ea0: 2430 movs r4, #48 ; 0x30 8003ea2: 2e00 cmp r6, #0 8003ea4: d1b4 bne.n 8003e10 <_strtoul_l.isra.0+0x5c> 8003ea6: 2608 movs r6, #8 8003ea8: e7b2 b.n 8003e10 <_strtoul_l.isra.0+0x5c> 8003eaa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} ... 08003eb0 <_strtoul_r>: 8003eb0: b537 push {r0, r1, r2, r4, r5, lr} 8003eb2: 4c06 ldr r4, [pc, #24] ; (8003ecc <_strtoul_r+0x1c>) 8003eb4: 4d06 ldr r5, [pc, #24] ; (8003ed0 <_strtoul_r+0x20>) 8003eb6: 6824 ldr r4, [r4, #0] 8003eb8: 6a24 ldr r4, [r4, #32] 8003eba: 2c00 cmp r4, #0 8003ebc: bf08 it eq 8003ebe: 462c moveq r4, r5 8003ec0: 9400 str r4, [sp, #0] 8003ec2: f7ff ff77 bl 8003db4 <_strtoul_l.isra.0> 8003ec6: b003 add sp, #12 8003ec8: bd30 pop {r4, r5, pc} 8003eca: bf00 nop 8003ecc: 2000001c .word 0x2000001c 8003ed0: 20000080 .word 0x20000080 08003ed4 <__submore>: 8003ed4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8003ed8: 460c mov r4, r1 8003eda: 6b49 ldr r1, [r1, #52] ; 0x34 8003edc: f104 0344 add.w r3, r4, #68 ; 0x44 8003ee0: 4299 cmp r1, r3 8003ee2: d11c bne.n 8003f1e <__submore+0x4a> 8003ee4: f44f 6180 mov.w r1, #1024 ; 0x400 8003ee8: f7ff fb2c bl 8003544 <_malloc_r> 8003eec: b918 cbnz r0, 8003ef6 <__submore+0x22> 8003eee: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8003ef2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8003ef6: f44f 6380 mov.w r3, #1024 ; 0x400 8003efa: 63a3 str r3, [r4, #56] ; 0x38 8003efc: f894 3046 ldrb.w r3, [r4, #70] ; 0x46 8003f00: 6360 str r0, [r4, #52] ; 0x34 8003f02: f880 33ff strb.w r3, [r0, #1023] ; 0x3ff 8003f06: f894 3045 ldrb.w r3, [r4, #69] ; 0x45 8003f0a: f200 30fd addw r0, r0, #1021 ; 0x3fd 8003f0e: 7043 strb r3, [r0, #1] 8003f10: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 8003f14: 7003 strb r3, [r0, #0] 8003f16: 6020 str r0, [r4, #0] 8003f18: 2000 movs r0, #0 8003f1a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8003f1e: 6ba6 ldr r6, [r4, #56] ; 0x38 8003f20: 0077 lsls r7, r6, #1 8003f22: 463a mov r2, r7 8003f24: f000 f84d bl 8003fc2 <_realloc_r> 8003f28: 4605 mov r5, r0 8003f2a: 2800 cmp r0, #0 8003f2c: d0df beq.n 8003eee <__submore+0x1a> 8003f2e: eb00 0806 add.w r8, r0, r6 8003f32: 4601 mov r1, r0 8003f34: 4632 mov r2, r6 8003f36: 4640 mov r0, r8 8003f38: f000 f836 bl 8003fa8 8003f3c: f8c4 8000 str.w r8, [r4] 8003f40: 6365 str r5, [r4, #52] ; 0x34 8003f42: 63a7 str r7, [r4, #56] ; 0x38 8003f44: e7e8 b.n 8003f18 <__submore+0x44> 08003f46 <__locale_ctype_ptr_l>: 8003f46: f8d0 00ec ldr.w r0, [r0, #236] ; 0xec 8003f4a: 4770 bx lr 08003f4c <__locale_ctype_ptr>: 8003f4c: 4b04 ldr r3, [pc, #16] ; (8003f60 <__locale_ctype_ptr+0x14>) 8003f4e: 4a05 ldr r2, [pc, #20] ; (8003f64 <__locale_ctype_ptr+0x18>) 8003f50: 681b ldr r3, [r3, #0] 8003f52: 6a1b ldr r3, [r3, #32] 8003f54: 2b00 cmp r3, #0 8003f56: bf08 it eq 8003f58: 4613 moveq r3, r2 8003f5a: f8d3 00ec ldr.w r0, [r3, #236] ; 0xec 8003f5e: 4770 bx lr 8003f60: 2000001c .word 0x2000001c 8003f64: 20000080 .word 0x20000080 08003f68 <__ascii_mbtowc>: 8003f68: b082 sub sp, #8 8003f6a: b901 cbnz r1, 8003f6e <__ascii_mbtowc+0x6> 8003f6c: a901 add r1, sp, #4 8003f6e: b142 cbz r2, 8003f82 <__ascii_mbtowc+0x1a> 8003f70: b14b cbz r3, 8003f86 <__ascii_mbtowc+0x1e> 8003f72: 7813 ldrb r3, [r2, #0] 8003f74: 600b str r3, [r1, #0] 8003f76: 7812 ldrb r2, [r2, #0] 8003f78: 1c10 adds r0, r2, #0 8003f7a: bf18 it ne 8003f7c: 2001 movne r0, #1 8003f7e: b002 add sp, #8 8003f80: 4770 bx lr 8003f82: 4610 mov r0, r2 8003f84: e7fb b.n 8003f7e <__ascii_mbtowc+0x16> 8003f86: f06f 0001 mvn.w r0, #1 8003f8a: e7f8 b.n 8003f7e <__ascii_mbtowc+0x16> 08003f8c : 8003f8c: b510 push {r4, lr} 8003f8e: b2c9 uxtb r1, r1 8003f90: 4402 add r2, r0 8003f92: 4290 cmp r0, r2 8003f94: 4603 mov r3, r0 8003f96: d101 bne.n 8003f9c 8003f98: 2000 movs r0, #0 8003f9a: bd10 pop {r4, pc} 8003f9c: 781c ldrb r4, [r3, #0] 8003f9e: 3001 adds r0, #1 8003fa0: 428c cmp r4, r1 8003fa2: d1f6 bne.n 8003f92 8003fa4: 4618 mov r0, r3 8003fa6: bd10 pop {r4, pc} 08003fa8 : 8003fa8: b510 push {r4, lr} 8003faa: 1e43 subs r3, r0, #1 8003fac: 440a add r2, r1 8003fae: 4291 cmp r1, r2 8003fb0: d100 bne.n 8003fb4 8003fb2: bd10 pop {r4, pc} 8003fb4: f811 4b01 ldrb.w r4, [r1], #1 8003fb8: f803 4f01 strb.w r4, [r3, #1]! 8003fbc: e7f7 b.n 8003fae 08003fbe <__malloc_lock>: 8003fbe: 4770 bx lr 08003fc0 <__malloc_unlock>: 8003fc0: 4770 bx lr 08003fc2 <_realloc_r>: 8003fc2: b5f8 push {r3, r4, r5, r6, r7, lr} 8003fc4: 4607 mov r7, r0 8003fc6: 4614 mov r4, r2 8003fc8: 460e mov r6, r1 8003fca: b921 cbnz r1, 8003fd6 <_realloc_r+0x14> 8003fcc: 4611 mov r1, r2 8003fce: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} 8003fd2: f7ff bab7 b.w 8003544 <_malloc_r> 8003fd6: b922 cbnz r2, 8003fe2 <_realloc_r+0x20> 8003fd8: f7ff fa68 bl 80034ac <_free_r> 8003fdc: 4625 mov r5, r4 8003fde: 4628 mov r0, r5 8003fe0: bdf8 pop {r3, r4, r5, r6, r7, pc} 8003fe2: f000 f821 bl 8004028 <_malloc_usable_size_r> 8003fe6: 4284 cmp r4, r0 8003fe8: d90f bls.n 800400a <_realloc_r+0x48> 8003fea: 4621 mov r1, r4 8003fec: 4638 mov r0, r7 8003fee: f7ff faa9 bl 8003544 <_malloc_r> 8003ff2: 4605 mov r5, r0 8003ff4: 2800 cmp r0, #0 8003ff6: d0f2 beq.n 8003fde <_realloc_r+0x1c> 8003ff8: 4631 mov r1, r6 8003ffa: 4622 mov r2, r4 8003ffc: f7ff ffd4 bl 8003fa8 8004000: 4631 mov r1, r6 8004002: 4638 mov r0, r7 8004004: f7ff fa52 bl 80034ac <_free_r> 8004008: e7e9 b.n 8003fde <_realloc_r+0x1c> 800400a: 4635 mov r5, r6 800400c: e7e7 b.n 8003fde <_realloc_r+0x1c> 0800400e <__ascii_wctomb>: 800400e: b149 cbz r1, 8004024 <__ascii_wctomb+0x16> 8004010: 2aff cmp r2, #255 ; 0xff 8004012: bf8b itete hi 8004014: 238a movhi r3, #138 ; 0x8a 8004016: 700a strbls r2, [r1, #0] 8004018: 6003 strhi r3, [r0, #0] 800401a: 2001 movls r0, #1 800401c: bf88 it hi 800401e: f04f 30ff movhi.w r0, #4294967295 ; 0xffffffff 8004022: 4770 bx lr 8004024: 4608 mov r0, r1 8004026: 4770 bx lr 08004028 <_malloc_usable_size_r>: 8004028: f851 0c04 ldr.w r0, [r1, #-4] 800402c: 2800 cmp r0, #0 800402e: f1a0 0004 sub.w r0, r0, #4 8004032: bfbc itt lt 8004034: 580b ldrlt r3, [r1, r0] 8004036: 18c0 addlt r0, r0, r3 8004038: 4770 bx lr ... 0800403c <_init>: 800403c: b5f8 push {r3, r4, r5, r6, r7, lr} 800403e: bf00 nop 8004040: bcf8 pop {r3, r4, r5, r6, r7} 8004042: bc08 pop {r3} 8004044: 469e mov lr, r3 8004046: 4770 bx lr 08004048 <_fini>: 8004048: b5f8 push {r3, r4, r5, r6, r7, lr} 800404a: bf00 nop 800404c: bcf8 pop {r3, r4, r5, r6, r7} 800404e: bc08 pop {r3} 8004050: 469e mov lr, r3 8004052: 4770 bx lr