From f6f5a3eab59fc3aef890aeee9bc6356f1043dfbd Mon Sep 17 00:00:00 2001 From: Noel Jumin Date: Wed, 22 Mar 2023 14:41:17 +0100 Subject: [PATCH 1/6] New branch init --- Drivers/Inc/ADC.h | 36 +++++++++++++++++++ Drivers/Src/ADC.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 Drivers/Inc/ADC.h create mode 100644 Drivers/Src/ADC.c diff --git a/Drivers/Inc/ADC.h b/Drivers/Inc/ADC.h new file mode 100644 index 0000000..235b60b --- /dev/null +++ b/Drivers/Inc/ADC.h @@ -0,0 +1,36 @@ +#ifndef MYTIMER_H +#define MYTIMER_H +#include "stm32f10x.h" + +typedef struct +{ + TIM_TypeDef * Timer ; // TIM1 à TIM4 + unsigned short ARR; + unsigned short PSC; +}MyTimer_Struct_TypeDef; +/* +***************************************************************************************** +* @brief +* @param -> Paramètre sous forme d’une structure (son adresse) contenant les +informations de base +* @Note -> Fonction à lancer systématiquement avant d’aller plus en détail dans les +conf plus fines (PWM, codeur inc...) +************************************************************************************************* +*/ +void MyTimer_Base_Init (MyTimer_Struct_TypeDef * Timer); +/* +***************************************************************************************** +* @brief +* @param -> - TIM_TypeDef * Timer : Timer concerne + - char Prio : de 0 a 15 +* @Note -> La fonction MyTimer_Base_Init doit avoir ete lancee au prealable +************************************************************************************************* +*/ +void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void)); + + +#define MyTimer_Base_Start(Timer) (Timer->CR1 |= 0x01) +#define MyTimer_Base_Stop(Timer) (Timer->CR1 &= ~0x01) + + +#endif diff --git a/Drivers/Src/ADC.c b/Drivers/Src/ADC.c new file mode 100644 index 0000000..7b9f22b --- /dev/null +++ b/Drivers/Src/ADC.c @@ -0,0 +1,92 @@ +#include "TIMER.h" + +/*periode_timer=peridoe_horloge*prescaler*resolution +debordement stocké dans registre UIF +fixer val prescaler+ autoreload(equivalent resolution) +demarrage timer => CEN=1*/ + +void (*ptr_func)(void); + +void MyTimer_Base_Init ( MyTimer_Struct_TypeDef * Timer) +{ + if(Timer->Timer==TIM1) + { + RCC->APB2ENR |= 0x01<<11; + } + else if (Timer->Timer==TIM2) + { + RCC->APB1ENR |= 0x01; + } + else if (Timer->Timer==TIM3) + { + RCC->APB1ENR |= 0x01<<1; + } + else if (Timer->Timer==TIM4) + { + RCC->APB1ENR |= 0x01<<2; + } + Timer->Timer->ARR=Timer->ARR; + Timer->Timer->PSC=Timer->PSC; +} + +void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void)) +{ + int num_tim; + ptr_func=IT_function; + Timer->DIER |= 0x01; + if(Timer==TIM1) + { + num_tim=TIM1_UP_IRQn; + } + else if(Timer==TIM2) + { + num_tim=TIM2_IRQn; + } + else if(Timer==TIM3) + { + num_tim=TIM3_IRQn; + } + else if(Timer==TIM4) + { + num_tim=TIM4_IRQn; + } + NVIC->ISER[0] |= 0x01<IP[num_tim] |= Prio << 4; + +} + +void TIM2_IRQHandler (void) +{ + if(ptr_func!=0) + { + (*ptr_func)(); + } + TIM2->SR &= ~(1<<0) ; +} + +void TIM3_IRQHandler (void) +{ + if(ptr_func!=0) + { + (*ptr_func)(); + } + TIM3->SR &= ~(1<<0) ; +} + +void TIM4_IRQHandler (void) +{ + if(ptr_func!=0) + { + (*ptr_func)(); + } + TIM4->SR &= ~(1<<0) ; +} + +void TIM1_UP_IRQHandler (void) // à vérifier +{ + if(ptr_func!=0) + { + (*ptr_func)(); + } + TIM1->SR &= ~(1<<0) ; +} From 7bd8d23d41c4b8f13c7f50f180bda6575d7e0552 Mon Sep 17 00:00:00 2001 From: Noel Jumin Date: Wed, 22 Mar 2023 18:06:33 +0100 Subject: [PATCH 2/6] commit de pauline --- Drivers/Inc/ADC.h | 36 +---- Drivers/Src/ADC.c | 203 ++++++++++++++++---------- Drivers/Src/TIMER.c | 28 ++-- Projet_DevDrivers/Sources/Principal.c | 12 +- Projet_DevDrivers/TP1.uvoptx | 12 ++ Projet_DevDrivers/TP1.uvprojx | 10 ++ 6 files changed, 172 insertions(+), 129 deletions(-) diff --git a/Drivers/Inc/ADC.h b/Drivers/Inc/ADC.h index 235b60b..21bf348 100644 --- a/Drivers/Inc/ADC.h +++ b/Drivers/Inc/ADC.h @@ -1,36 +1,14 @@ -#ifndef MYTIMER_H -#define MYTIMER_H +#ifndef MYADC_H +#define MYADC_H #include "stm32f10x.h" +#include "GPIO.h" typedef struct { - TIM_TypeDef * Timer ; // TIM1 à TIM4 - unsigned short ARR; - unsigned short PSC; -}MyTimer_Struct_TypeDef; -/* -***************************************************************************************** -* @brief -* @param -> Paramètre sous forme d’une structure (son adresse) contenant les -informations de base -* @Note -> Fonction à lancer systématiquement avant d’aller plus en détail dans les -conf plus fines (PWM, codeur inc...) -************************************************************************************************* -*/ -void MyTimer_Base_Init (MyTimer_Struct_TypeDef * Timer); -/* -***************************************************************************************** -* @brief -* @param -> - TIM_TypeDef * Timer : Timer concerne - - char Prio : de 0 a 15 -* @Note -> La fonction MyTimer_Base_Init doit avoir ete lancee au prealable -************************************************************************************************* -*/ -void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void)); - - -#define MyTimer_Base_Start(Timer) (Timer->CR1 |= 0x01) -#define MyTimer_Base_Stop(Timer) (Timer->CR1 &= ~0x01) + ADC_TypeDef * ADC; + char channel; +} MyADC_Struct_TypeDef; +void MyADC_init(MyADC_Struct_TypeDef* myADC); #endif diff --git a/Drivers/Src/ADC.c b/Drivers/Src/ADC.c index 7b9f22b..18adebe 100644 --- a/Drivers/Src/ADC.c +++ b/Drivers/Src/ADC.c @@ -1,92 +1,137 @@ -#include "TIMER.h" +#include "ADC.h" -/*periode_timer=peridoe_horloge*prescaler*resolution -debordement stocké dans registre UIF -fixer val prescaler+ autoreload(equivalent resolution) -demarrage timer => CEN=1*/ - -void (*ptr_func)(void); - -void MyTimer_Base_Init ( MyTimer_Struct_TypeDef * Timer) +void MyADC_init(MyADC_Struct_TypeDef* myADC) { - if(Timer->Timer==TIM1) + MyGPIO_Struct_TypeDef Port_ADC; + RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; + if(myADC->ADC==ADC1) { - RCC->APB2ENR |= 0x01<<11; + RCC->APB2ENR |= 0x01<<9; + ADC1->CR2|= 0x01; // on active l'adc + ADC1->SQR1&= ~(0x0F<<20);// 1 convertion + ADC2->SQR3&= ~0x1F;// on met 0 la séquance 1 + ADC1->SQR3|= myADC->channel;// on indique le channel a convertir } - else if (Timer->Timer==TIM2) + else if(myADC->ADC==ADC2) { - RCC->APB1ENR |= 0x01; + RCC->APB2ENR |= 0x01<<8; + ADC2->CR2|= 0x01; // on active l'adc + ADC2->SQR1&= ~(0x0F<<20);// 1 convertion + ADC2->SQR3&= ~0x1F;// on met 0 la séquance 1 + ADC2->SQR3|= myADC->channel;// on indique le channel a convertir } - else if (Timer->Timer==TIM3) - { - RCC->APB1ENR |= 0x01<<1; - } - else if (Timer->Timer==TIM4) - { - RCC->APB1ENR |= 0x01<<2; - } - Timer->Timer->ARR=Timer->ARR; - Timer->Timer->PSC=Timer->PSC; -} - -void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void)) -{ - int num_tim; - ptr_func=IT_function; - Timer->DIER |= 0x01; - if(Timer==TIM1) - { - num_tim=TIM1_UP_IRQn; - } - else if(Timer==TIM2) - { - num_tim=TIM2_IRQn; - } - else if(Timer==TIM3) - { - num_tim=TIM3_IRQn; - } - else if(Timer==TIM4) - { - num_tim=TIM4_IRQn; - } - NVIC->ISER[0] |= 0x01<IP[num_tim] |= Prio << 4; + switch (myADC->channel) + { + case 0: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=0; + MyGPIO_Init(&Port_ADC); + break; + case 1: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=1; + MyGPIO_Init(&Port_ADC); + break; + case 2: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=2; + MyGPIO_Init(&Port_ADC); + break; + case 3: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=3; + MyGPIO_Init(&Port_ADC); + break; + case 4: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=4; + MyGPIO_Init(&Port_ADC); + break; + case 5: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=5; + MyGPIO_Init(&Port_ADC); + break; + case 6: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=6; + MyGPIO_Init(&Port_ADC); + break; + case 7: + Port_ADC.GPIO=GPIOA; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=7; + MyGPIO_Init(&Port_ADC); + break; + case 8: + Port_ADC.GPIO=GPIOB; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=0; + MyGPIO_Init(&Port_ADC); + break; + case 9: + Port_ADC.GPIO=GPIOB; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=1; + MyGPIO_Init(&Port_ADC); + break; + case 10: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=0; + MyGPIO_Init(&Port_ADC); + break; + case 11: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=1; + MyGPIO_Init(&Port_ADC); + break; + case 12: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=2; + MyGPIO_Init(&Port_ADC); + break; + case 13: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=3; + MyGPIO_Init(&Port_ADC); + break; + case 14: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=4; + MyGPIO_Init(&Port_ADC); + break; + case 15: + Port_ADC.GPIO=GPIOC; + Port_ADC.GPIO_Conf=In_Analog; + Port_ADC.GPIO_Pin=5; + MyGPIO_Init(&Port_ADC); + break; + } } -void TIM2_IRQHandler (void) -{ - if(ptr_func!=0) +int conversion(MyADC_Struct_TypeDef* myADC) { - (*ptr_func)(); - } - TIM2->SR &= ~(1<<0) ; + if() + { + + } + ADC1->CR2 |= ADC_CR2_ADON; // lancement de la conversion + While(!(ADC1->SR & ADC_SR_EOC) ) {} // attente de la fin de conversion + ADC1->SR &= ~ADC_SR_EOC; // validation de la conversion + return ADC1->DR & ~((0x0F) << 12); // retour de la conversion } -void TIM3_IRQHandler (void) -{ - if(ptr_func!=0) - { - (*ptr_func)(); - } - TIM3->SR &= ~(1<<0) ; -} -void TIM4_IRQHandler (void) -{ - if(ptr_func!=0) - { - (*ptr_func)(); - } - TIM4->SR &= ~(1<<0) ; -} - -void TIM1_UP_IRQHandler (void) // à vérifier -{ - if(ptr_func!=0) - { - (*ptr_func)(); - } - TIM1->SR &= ~(1<<0) ; -} diff --git a/Drivers/Src/TIMER.c b/Drivers/Src/TIMER.c index 7b9f22b..07c123f 100644 --- a/Drivers/Src/TIMER.c +++ b/Drivers/Src/TIMER.c @@ -5,7 +5,10 @@ debordement stock fixer val prescaler+ autoreload(equivalent resolution) demarrage timer => CEN=1*/ -void (*ptr_func)(void); +void (*ptr1_func)(void); +void (*ptr2_func)(void); +void (*ptr3_func)(void); +void (*ptr4_func)(void); void MyTimer_Base_Init ( MyTimer_Struct_TypeDef * Timer) { @@ -32,23 +35,26 @@ void MyTimer_Base_Init ( MyTimer_Struct_TypeDef * Timer) void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void)) { int num_tim; - ptr_func=IT_function; Timer->DIER |= 0x01; if(Timer==TIM1) { - num_tim=TIM1_UP_IRQn; + num_tim=TIM1_UP_IRQn; + ptr1_func=IT_function; } else if(Timer==TIM2) { num_tim=TIM2_IRQn; + ptr2_func=IT_function; } else if(Timer==TIM3) { num_tim=TIM3_IRQn; + ptr3_func=IT_function; } else if(Timer==TIM4) { num_tim=TIM4_IRQn; + ptr4_func=IT_function; } NVIC->ISER[0] |= 0x01<IP[num_tim] |= Prio << 4; @@ -57,36 +63,36 @@ void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void) void TIM2_IRQHandler (void) { - if(ptr_func!=0) + if(ptr2_func!=0) { - (*ptr_func)(); + (*ptr2_func)(); } TIM2->SR &= ~(1<<0) ; } void TIM3_IRQHandler (void) { - if(ptr_func!=0) + if(ptr3_func!=0) { - (*ptr_func)(); + (*ptr3_func)(); } TIM3->SR &= ~(1<<0) ; } void TIM4_IRQHandler (void) { - if(ptr_func!=0) + if(ptr4_func!=0) { - (*ptr_func)(); + (*ptr4_func)(); } TIM4->SR &= ~(1<<0) ; } void TIM1_UP_IRQHandler (void) // à vérifier { - if(ptr_func!=0) + if(ptr1_func!=0) { - (*ptr_func)(); + (*ptr1_func)(); } TIM1->SR &= ~(1<<0) ; } diff --git a/Projet_DevDrivers/Sources/Principal.c b/Projet_DevDrivers/Sources/Principal.c index 1cd5850..84c63ad 100644 --- a/Projet_DevDrivers/Sources/Principal.c +++ b/Projet_DevDrivers/Sources/Principal.c @@ -13,19 +13,11 @@ MyTimer_Struct_TypeDef timer2; int main ( void ) { - PA5.GPIO=GPIOA; - PA5.GPIO_Conf=Out_Ppull; - PA5.GPIO_Pin=5; - MyGPIO_Init(&PA5); - timer2.Timer=TIM2; - timer2.ARR=35999; //pour avoir 500ms - timer2.PSC=1000; - MyTimer_Base_Init(&timer2); - MyTimer_ActiveIT(timer2.Timer,1, &Mafonction_IT); - MyTimer_Base_Start(timer2.Timer); + while(1) { + } } diff --git a/Projet_DevDrivers/TP1.uvoptx b/Projet_DevDrivers/TP1.uvoptx index 6d8b9ef..ece801c 100644 --- a/Projet_DevDrivers/TP1.uvoptx +++ b/Projet_DevDrivers/TP1.uvoptx @@ -430,6 +430,18 @@ 0 0 + + 1 + 4 + 1 + 1 + 0 + 0 + ..\Drivers\Src\ADC.c + ADC.c + 0 + 0 + diff --git a/Projet_DevDrivers/TP1.uvprojx b/Projet_DevDrivers/TP1.uvprojx index dcb8b2b..9e4df6f 100644 --- a/Projet_DevDrivers/TP1.uvprojx +++ b/Projet_DevDrivers/TP1.uvprojx @@ -398,6 +398,11 @@ 1 ..\Drivers\Src\TIMER.c + + ADC.c + 1 + ..\Drivers\Src\ADC.c + @@ -800,6 +805,11 @@ 1 ..\Drivers\Src\TIMER.c + + ADC.c + 1 + ..\Drivers\Src\ADC.c + From d97f0b4c7a45de09aaa00b1745cc02243aff70e8 Mon Sep 17 00:00:00 2001 From: Noel Jumin Date: Mon, 27 Mar 2023 16:49:41 +0200 Subject: [PATCH 3/6] =?UTF-8?q?ADC=20fini=20avec=20interruption=20et=20UAR?= =?UTF-8?q?T=20=C3=A0=20tester?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Drivers/Inc/ADC.h | 4 +- Drivers/Inc/UART.h | 10 ++ Drivers/Src/ADC.c | 92 +++++++++++++------ Drivers/Src/TIMER.c | 32 +++---- Drivers/Src/UART.c | 44 +++++++++ Projet_DevDrivers/Sources/Principal.c | 30 ------ .../RTE/Device/STM32F103RB/RTE_Device.h | 0 .../Device/STM32F103RB/startup_stm32f10x_md.s | 0 .../RTE/Device/STM32F103RB/system_stm32f10x.c | 0 .../RTE/_R_el/RTE_Components.h | 0 .../RTE/_Simul_/RTE_Components.h | 0 .../RTE/_Target_1/RTE_Components.h | 0 Projet_voile/Sources/Principal.c | 38 ++++++++ .../TP1.uvoptx | 35 ++++++- .../TP1.uvprojx | 10 ++ 15 files changed, 216 insertions(+), 79 deletions(-) create mode 100644 Drivers/Inc/UART.h create mode 100644 Drivers/Src/UART.c delete mode 100644 Projet_DevDrivers/Sources/Principal.c rename {Projet_DevDrivers => Projet_voile}/RTE/Device/STM32F103RB/RTE_Device.h (100%) rename {Projet_DevDrivers => Projet_voile}/RTE/Device/STM32F103RB/startup_stm32f10x_md.s (100%) rename {Projet_DevDrivers => Projet_voile}/RTE/Device/STM32F103RB/system_stm32f10x.c (100%) rename {Projet_DevDrivers => Projet_voile}/RTE/_R_el/RTE_Components.h (100%) rename {Projet_DevDrivers => Projet_voile}/RTE/_Simul_/RTE_Components.h (100%) rename {Projet_DevDrivers => Projet_voile}/RTE/_Target_1/RTE_Components.h (100%) create mode 100644 Projet_voile/Sources/Principal.c rename {Projet_DevDrivers => Projet_voile}/TP1.uvoptx (89%) rename {Projet_DevDrivers => Projet_voile}/TP1.uvprojx (98%) diff --git a/Drivers/Inc/ADC.h b/Drivers/Inc/ADC.h index 21bf348..577d328 100644 --- a/Drivers/Inc/ADC.h +++ b/Drivers/Inc/ADC.h @@ -10,5 +10,7 @@ typedef struct } MyADC_Struct_TypeDef; void MyADC_init(MyADC_Struct_TypeDef* myADC); - +void MyADC_start_conversion(ADC_TypeDef* ADC); +void MyADC_ActiveIT (ADC_TypeDef * ADC, char Prio, void (*IT_function)(void)); +int MyADC_result(ADC_TypeDef* ADC); #endif diff --git a/Drivers/Inc/UART.h b/Drivers/Inc/UART.h new file mode 100644 index 0000000..7877d90 --- /dev/null +++ b/Drivers/Inc/UART.h @@ -0,0 +1,10 @@ +#ifndef MYUART_H +#define MYUART_H +#include "stm32f10x.h" + +void MyUART_init(void); +void UART_send(char data); //à revoir +void MyUART_ActiveIT(char Prio, void (*IT_function)(void)); +char UART_receive(); + +#endif diff --git a/Drivers/Src/ADC.c b/Drivers/Src/ADC.c index 18adebe..4a5e096 100644 --- a/Drivers/Src/ADC.c +++ b/Drivers/Src/ADC.c @@ -1,26 +1,10 @@ #include "ADC.h" +void (*adc_ptr_func)(void); + void MyADC_init(MyADC_Struct_TypeDef* myADC) { MyGPIO_Struct_TypeDef Port_ADC; - RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; - if(myADC->ADC==ADC1) - { - RCC->APB2ENR |= 0x01<<9; - ADC1->CR2|= 0x01; // on active l'adc - ADC1->SQR1&= ~(0x0F<<20);// 1 convertion - ADC2->SQR3&= ~0x1F;// on met 0 la séquance 1 - ADC1->SQR3|= myADC->channel;// on indique le channel a convertir - } - else if(myADC->ADC==ADC2) - { - RCC->APB2ENR |= 0x01<<8; - ADC2->CR2|= 0x01; // on active l'adc - ADC2->SQR1&= ~(0x0F<<20);// 1 convertion - ADC2->SQR3&= ~0x1F;// on met 0 la séquance 1 - ADC2->SQR3|= myADC->channel;// on indique le channel a convertir - } - switch (myADC->channel) { case 0: @@ -120,18 +104,68 @@ void MyADC_init(MyADC_Struct_TypeDef* myADC) MyGPIO_Init(&Port_ADC); break; } -} - -int conversion(MyADC_Struct_TypeDef* myADC) + if(myADC->ADC==ADC1) { - if() - { - - } - ADC1->CR2 |= ADC_CR2_ADON; // lancement de la conversion - While(!(ADC1->SR & ADC_SR_EOC) ) {} // attente de la fin de conversion - ADC1->SR &= ~ADC_SR_EOC; // validation de la conversion - return ADC1->DR & ~((0x0F) << 12); // retour de la conversion + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // validation horloge ADC1 + RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; // passage de l'horloge ADC1 à 12MHz + ADC1->CR2|= ADC_CR2_ADON; // démarrage ADC1 + ADC1->SQR1&= ADC_SQR1_L; // fixe le nombre de conversion à 1 + ADC1->SQR3|= myADC->channel; // indique la voie à convertir + ADC1->CR2 |= ADC_CR2_CAL; // dÈbut de la calibration + while ((ADC1->CR2 & ADC_CR2_CAL)); // attente de la fin de la calibration + } + else if(myADC->ADC==ADC2) + { + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // validation horloge ADC1 + RCC->CFGR |= RCC_CFGR_ADCPRE_DIV6; // passage de l'horloge ADC1 à 12MHz + ADC2->CR2|= ADC_CR2_ADON; // démarrage ADC1 + ADC2->SQR1&= ADC_SQR1_L; // fixe le nombre de conversion à 1 + ADC2->SQR3|= myADC->channel; // indique la voie à convertir + ADC2->CR2 |= ADC_CR2_CAL; // dÈbut de la calibration + while ((ADC2->CR2 & ADC_CR2_CAL)); // attente de la fin de la calibration + } } +void MyADC_start_conversion(ADC_TypeDef* ADC) +{ + if(ADC==ADC1) + { + ADC1->CR2 |= ADC_CR2_ADON; // lancement de la conversion + } + else if(ADC==ADC2) + { + ADC2->CR2 |= ADC_CR2_ADON; // lancement de la conversion + } +} + +void ADC1_2_IRQHandler(void) +{ + ADC1->SR &= ~ADC_SR_EOC ; + ADC2->SR &= ~ADC_SR_EOC ; + if(adc_ptr_func!=0) + { + (*adc_ptr_func)(); + } +} + +void MyADC_ActiveIT (ADC_TypeDef * ADC, char Prio, void (*IT_function)(void)) +{ + ADC->CR1 |= ADC_CR1_EOCIE; + adc_ptr_func=IT_function; + NVIC->ISER[0] |= 0x01<IP[ADC1_2_IRQn] |= Prio << 4; + +} + +int MyADC_result(ADC_TypeDef* ADC) +{ + if (ADC==ADC1) + { + return ADC1->DR & ~((0x0F) << 12); // retour de la conversion + } + else if(ADC==ADC2) + { + return ADC2->DR & ~((0x0F) << 12); // retour de la conversion + } +} \ No newline at end of file diff --git a/Drivers/Src/TIMER.c b/Drivers/Src/TIMER.c index 07c123f..8b0fe3b 100644 --- a/Drivers/Src/TIMER.c +++ b/Drivers/Src/TIMER.c @@ -5,10 +5,10 @@ debordement stock fixer val prescaler+ autoreload(equivalent resolution) demarrage timer => CEN=1*/ -void (*ptr1_func)(void); -void (*ptr2_func)(void); -void (*ptr3_func)(void); -void (*ptr4_func)(void); +void (*tim_ptr1_func)(void); +void (*tim_ptr2_func)(void); +void (*tim_ptr3_func)(void); +void (*tim_ptr4_func)(void); void MyTimer_Base_Init ( MyTimer_Struct_TypeDef * Timer) { @@ -39,22 +39,22 @@ void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void) if(Timer==TIM1) { num_tim=TIM1_UP_IRQn; - ptr1_func=IT_function; + tim_ptr1_func=IT_function; } else if(Timer==TIM2) { num_tim=TIM2_IRQn; - ptr2_func=IT_function; + tim_ptr2_func=IT_function; } else if(Timer==TIM3) { num_tim=TIM3_IRQn; - ptr3_func=IT_function; + tim_ptr3_func=IT_function; } else if(Timer==TIM4) { num_tim=TIM4_IRQn; - ptr4_func=IT_function; + tim_ptr4_func=IT_function; } NVIC->ISER[0] |= 0x01<IP[num_tim] |= Prio << 4; @@ -63,36 +63,36 @@ void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void) void TIM2_IRQHandler (void) { - if(ptr2_func!=0) + if(tim_ptr2_func!=0) { - (*ptr2_func)(); + (*tim_ptr2_func)(); } TIM2->SR &= ~(1<<0) ; } void TIM3_IRQHandler (void) { - if(ptr3_func!=0) + if(tim_ptr3_func!=0) { - (*ptr3_func)(); + (*tim_ptr3_func)(); } TIM3->SR &= ~(1<<0) ; } void TIM4_IRQHandler (void) { - if(ptr4_func!=0) + if(tim_ptr4_func!=0) { - (*ptr4_func)(); + (*tim_ptr4_func)(); } TIM4->SR &= ~(1<<0) ; } void TIM1_UP_IRQHandler (void) // à vérifier { - if(ptr1_func!=0) + if(tim_ptr1_func!=0) { - (*ptr1_func)(); + (*tim_ptr1_func)(); } TIM1->SR &= ~(1<<0) ; } diff --git a/Drivers/Src/UART.c b/Drivers/Src/UART.c new file mode 100644 index 0000000..fea85ee --- /dev/null +++ b/Drivers/Src/UART.c @@ -0,0 +1,44 @@ +#include "UART.h" + +void (*uart_ptr_func)(void); +char buffer[1000]={0}; + +void MyUART_init(void) // que pour du 9600 bauds +{ + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // validation horloge USART1 + USART1->CR1 |= USART_CR1_UE; // Activation de l'USART + USART1->CR1 &= ~USART_CR1_M; // Choix d'une taille de 8 bits de données + USART1->CR2 &= USART_CR2_STOP; // Choix d'un seul bit de stop + USART1->BRR |= 468 << 4; // Fixe le baud rate à 9600bps //valeurs trouvé p804 + USART1->BRR |= 75; // Fixe le baud rate à 9600bps + USART1->CR1 |= USART_CR1_TE; // Envoi de la première trame d'attente +} + +void UART_send(char data) +{ + USART1->DR |= data; // Ecriture de la donnée dans le registre DR + while(!(USART1->SR & USART_SR_TC)) {} // Attente de la fin de transmission +} + +void MyUART_ActiveIT(char Prio, void (*IT_function)(void)) +{ + USART1->CR1 |= USART_CR1_RXNEIE; + NVIC->ISER[1] |= 0x01<<(USART1_IRQn%32); + NVIC->IP[USART1_IRQn] |= Prio << 4; +} + +void USART1_IRQHandler() +{ + USART1->SR &= ~USART_SR_RXNE; + if(uart_ptr_func!=0) + { + (*uart_ptr_func)(); + } +} + +char UART_receive() +{ + char carac; + carac = USART1->DR; + return carac; +} diff --git a/Projet_DevDrivers/Sources/Principal.c b/Projet_DevDrivers/Sources/Principal.c deleted file mode 100644 index 84c63ad..0000000 --- a/Projet_DevDrivers/Sources/Principal.c +++ /dev/null @@ -1,30 +0,0 @@ -#include "stm32f10x.h" -#include "GPIO.h" -#include "TIMER.h" - - - -void Mafonction_IT (void); -MyGPIO_Struct_TypeDef PA5; -MyGPIO_Struct_TypeDef PC13; -MyTimer_Struct_TypeDef timer2; -//PA5 LED -//PC13 Bouton - -int main ( void ) -{ - - - while(1) - { - - } - -} - - - -void Mafonction_IT (void) -{ - MyGPIO_Toggle(PA5.GPIO,5); -} diff --git a/Projet_DevDrivers/RTE/Device/STM32F103RB/RTE_Device.h b/Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h similarity index 100% rename from Projet_DevDrivers/RTE/Device/STM32F103RB/RTE_Device.h rename to Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h diff --git a/Projet_DevDrivers/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s similarity index 100% rename from Projet_DevDrivers/RTE/Device/STM32F103RB/startup_stm32f10x_md.s rename to Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s diff --git a/Projet_DevDrivers/RTE/Device/STM32F103RB/system_stm32f10x.c b/Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c similarity index 100% rename from Projet_DevDrivers/RTE/Device/STM32F103RB/system_stm32f10x.c rename to Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c diff --git a/Projet_DevDrivers/RTE/_R_el/RTE_Components.h b/Projet_voile/RTE/_R_el/RTE_Components.h similarity index 100% rename from Projet_DevDrivers/RTE/_R_el/RTE_Components.h rename to Projet_voile/RTE/_R_el/RTE_Components.h diff --git a/Projet_DevDrivers/RTE/_Simul_/RTE_Components.h b/Projet_voile/RTE/_Simul_/RTE_Components.h similarity index 100% rename from Projet_DevDrivers/RTE/_Simul_/RTE_Components.h rename to Projet_voile/RTE/_Simul_/RTE_Components.h diff --git a/Projet_DevDrivers/RTE/_Target_1/RTE_Components.h b/Projet_voile/RTE/_Target_1/RTE_Components.h similarity index 100% rename from Projet_DevDrivers/RTE/_Target_1/RTE_Components.h rename to Projet_voile/RTE/_Target_1/RTE_Components.h diff --git a/Projet_voile/Sources/Principal.c b/Projet_voile/Sources/Principal.c new file mode 100644 index 0000000..5efa581 --- /dev/null +++ b/Projet_voile/Sources/Principal.c @@ -0,0 +1,38 @@ +#include "stm32f10x.h" +#include "GPIO.h" +#include "TIMER.h" +#include "ADC.h" +#include "UART.h" + +int val_adc=0; +MyGPIO_Struct_TypeDef PA5; //PA5 LED +MyGPIO_Struct_TypeDef PC13; //PC13 Bouton +MyTimer_Struct_TypeDef timer2; +MyADC_Struct_TypeDef myADC; +void Mafonction_IT (void); +void Mafonction_IT2(void); + +int main ( void ) +{ + myADC.ADC=ADC1; + myADC.channel=2; + MyADC_init(&myADC); + MyADC_ActiveIT(myADC.ADC,0,&Mafonction_IT2); + MyADC_start_conversion(myADC.ADC); + while(1) + { + } + +} + + + +void Mafonction_IT (void) +{ + MyGPIO_Toggle(PA5.GPIO,5); +} + +void Mafonction_IT2 (void) +{ + val_adc=MyADC_result(myADC.ADC); +} diff --git a/Projet_DevDrivers/TP1.uvoptx b/Projet_voile/TP1.uvoptx similarity index 89% rename from Projet_DevDrivers/TP1.uvoptx rename to Projet_voile/TP1.uvoptx index ece801c..9b7ddad 100644 --- a/Projet_DevDrivers/TP1.uvoptx +++ b/Projet_voile/TP1.uvoptx @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=733,260,1154,687,0)(121=-1,-1,-1,-1,0)(122=1345,565,1766,992,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=1189,292,1783,1043,1)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + (1010=1184,109,1560,666,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=733,260,1154,687,0)(121=-1,-1,-1,-1,0)(122=1345,565,1766,992,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=335,254,929,1005,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=1126,210,1574,624,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=298,316,901,1067,0)(151=-1,-1,-1,-1,0) 0 @@ -138,7 +138,24 @@ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) - + + + 0 + 0 + 37 + 1 +
134218114
+ 0 + 0 + 0 + 0 + 0 + 1 + .\Sources\Principal.c + + \\TP1\Sources/Principal.c\37 + + 0 @@ -147,7 +164,7 @@ 1 1 0 - 0 + 1 0 0 1 @@ -442,6 +459,18 @@ 0 0 + + 1 + 5 + 1 + 1 + 0 + 0 + ..\Drivers\Src\UART.c + UART.c + 0 + 0 + diff --git a/Projet_DevDrivers/TP1.uvprojx b/Projet_voile/TP1.uvprojx similarity index 98% rename from Projet_DevDrivers/TP1.uvprojx rename to Projet_voile/TP1.uvprojx index 9e4df6f..4c5f056 100644 --- a/Projet_DevDrivers/TP1.uvprojx +++ b/Projet_voile/TP1.uvprojx @@ -403,6 +403,11 @@ 1 ..\Drivers\Src\ADC.c + + UART.c + 1 + ..\Drivers\Src\UART.c + @@ -810,6 +815,11 @@ 1 ..\Drivers\Src\ADC.c + + UART.c + 1 + ..\Drivers\Src\UART.c + From adcecf465c090ed5763cc66dd1620ec13bd8603b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?No=C3=ABl=20JUMIN?= Date: Mon, 27 Mar 2023 20:17:23 +0200 Subject: [PATCH 4/6] =?UTF-8?q?Choses=20=C3=A0=20revoir=20sur=20l'uart?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Drivers/Inc/UART.h | 2 +- Drivers/Src/ADC.c | 36 +- Drivers/Src/UART.c | 39 +- .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ .../startup_stm32f10x_md.s.update@1.0.1 | 308 +++ .../system_stm32f10x.c.update@1.0.1 | 1092 ++++++++++ Projet_voile/Sources/Principal.c | 52 +- Projet_voile/TP1.uvoptx | 30 +- Projet_voile/TP1.uvprojx | 34 +- 9 files changed, 3370 insertions(+), 51 deletions(-) create mode 100644 Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 create mode 100644 Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 diff --git a/Drivers/Inc/UART.h b/Drivers/Inc/UART.h index 7877d90..398b87b 100644 --- a/Drivers/Inc/UART.h +++ b/Drivers/Inc/UART.h @@ -4,7 +4,7 @@ void MyUART_init(void); void UART_send(char data); //à revoir -void MyUART_ActiveIT(char Prio, void (*IT_function)(void)); +void MyUART_ActiveIT(char Prio, void (*IT_function)(void), char mode); //mode permet d'activer soit l'interruption sur RX (mode='r') soit TX (mode='t') char UART_receive(); #endif diff --git a/Drivers/Src/ADC.c b/Drivers/Src/ADC.c index 4a5e096..50fa86a 100644 --- a/Drivers/Src/ADC.c +++ b/Drivers/Src/ADC.c @@ -1,6 +1,7 @@ #include "ADC.h" -void (*adc_ptr_func)(void); +void (*adc1_ptr_func)(void); +void (*adc2_ptr_func)(void); void MyADC_init(MyADC_Struct_TypeDef* myADC) { @@ -111,7 +112,7 @@ void MyADC_init(MyADC_Struct_TypeDef* myADC) ADC1->CR2|= ADC_CR2_ADON; // démarrage ADC1 ADC1->SQR1&= ADC_SQR1_L; // fixe le nombre de conversion à 1 ADC1->SQR3|= myADC->channel; // indique la voie à convertir - ADC1->CR2 |= ADC_CR2_CAL; // dÈbut de la calibration + ADC1->CR2 |= ADC_CR2_CAL; // début de la calibration while ((ADC1->CR2 & ADC_CR2_CAL)); // attente de la fin de la calibration } else if(myADC->ADC==ADC2) @@ -121,7 +122,7 @@ void MyADC_init(MyADC_Struct_TypeDef* myADC) ADC2->CR2|= ADC_CR2_ADON; // démarrage ADC1 ADC2->SQR1&= ADC_SQR1_L; // fixe le nombre de conversion à 1 ADC2->SQR3|= myADC->channel; // indique la voie à convertir - ADC2->CR2 |= ADC_CR2_CAL; // dÈbut de la calibration + ADC2->CR2 |= ADC_CR2_CAL; // début de la calibration while ((ADC2->CR2 & ADC_CR2_CAL)); // attente de la fin de la calibration } } @@ -141,18 +142,36 @@ void MyADC_start_conversion(ADC_TypeDef* ADC) void ADC1_2_IRQHandler(void) { - ADC1->SR &= ~ADC_SR_EOC ; - ADC2->SR &= ~ADC_SR_EOC ; - if(adc_ptr_func!=0) + if(ADC1->SR & ~ADC_SR_EOC) { - (*adc_ptr_func)(); + ADC1->SR &= ~ADC_SR_EOC ; + if(adc1_ptr_func!=0) + { + (*adc1_ptr_func)(); + } } + else if(ADC2->SR & ~ADC_SR_EOC) + { + ADC2->SR &= ~ADC_SR_EOC ; + if(adc2_ptr_func!=0) + { + (*adc2_ptr_func)(); + } + } + } void MyADC_ActiveIT (ADC_TypeDef * ADC, char Prio, void (*IT_function)(void)) { ADC->CR1 |= ADC_CR1_EOCIE; - adc_ptr_func=IT_function; + if(ADC==ADC1) + { + adc1_ptr_func=IT_function; + } + else if(ADC==ADC2) + { + adc2_ptr_func=IT_function; + } NVIC->ISER[0] |= 0x01<IP[ADC1_2_IRQn] |= Prio << 4; @@ -168,4 +187,5 @@ int MyADC_result(ADC_TypeDef* ADC) { return ADC2->DR & ~((0x0F) << 12); // retour de la conversion } + return 0; } \ No newline at end of file diff --git a/Drivers/Src/UART.c b/Drivers/Src/UART.c index fea85ee..e89e7f6 100644 --- a/Drivers/Src/UART.c +++ b/Drivers/Src/UART.c @@ -1,6 +1,7 @@ #include "UART.h" -void (*uart_ptr_func)(void); +void (*uart_rx_ptr_func)(void); +void (*uart_tx_ptr_func)(void); char buffer[1000]={0}; void MyUART_init(void) // que pour du 9600 bauds @@ -17,28 +18,46 @@ void MyUART_init(void) // que pour du 9600 bauds void UART_send(char data) { USART1->DR |= data; // Ecriture de la donnée dans le registre DR - while(!(USART1->SR & USART_SR_TC)) {} // Attente de la fin de transmission } -void MyUART_ActiveIT(char Prio, void (*IT_function)(void)) +void MyUART_ActiveIT(char Prio, void (*IT_function)(void), char mode) { - USART1->CR1 |= USART_CR1_RXNEIE; + if (mode=='r') + { + USART1->CR1 |= USART_CR1_RXNEIE; + uart_rx_ptr_func=IT_function; + } + else if (mode=='t') + { + USART1->CR1 |= USART_CR1_TXEIE; + uart_tx_ptr_func=IT_function; + } NVIC->ISER[1] |= 0x01<<(USART1_IRQn%32); NVIC->IP[USART1_IRQn] |= Prio << 4; } void USART1_IRQHandler() { - USART1->SR &= ~USART_SR_RXNE; - if(uart_ptr_func!=0) + if (USART1->SR & USART_SR_RXNE) { - (*uart_ptr_func)(); + USART1->SR &= ~USART_SR_RXNE; + if(uart_rx_ptr_func!=0) + { + (*uart_rx_ptr_func)(); + } } + else if (USART1->SR & USART_SR_TXE) // à revoir car si rien dedans il va tout le temps y retourner vu qu'il est vide + { + USART1->SR &= ~USART_SR_TXE; + if(uart_tx_ptr_func!=0) + { + (*uart_tx_ptr_func)(); + } + } + } char UART_receive() { - char carac; - carac = USART1->DR; - return carac; + return USART1->DR; } diff --git a/Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..0d10ed8 --- /dev/null +++ b/Projet_voile/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 b/Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 new file mode 100644 index 0000000..1ab7096 --- /dev/null +++ b/Projet_voile/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 b/Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 new file mode 100644 index 0000000..9e31f67 --- /dev/null +++ b/Projet_voile/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Projet_voile/Sources/Principal.c b/Projet_voile/Sources/Principal.c index 5efa581..7dff07f 100644 --- a/Projet_voile/Sources/Principal.c +++ b/Projet_voile/Sources/Principal.c @@ -1,24 +1,38 @@ #include "stm32f10x.h" +#include +#include #include "GPIO.h" #include "TIMER.h" #include "ADC.h" #include "UART.h" int val_adc=0; +int cpt_buff_tx=0; +int cpt_buff_rx=0; MyGPIO_Struct_TypeDef PA5; //PA5 LED MyGPIO_Struct_TypeDef PC13; //PC13 Bouton MyTimer_Struct_TypeDef timer2; MyADC_Struct_TypeDef myADC; -void Mafonction_IT (void); -void Mafonction_IT2(void); +char buffer_tx[100]={0}; +char buffer_rx[100]={0}; +void GPIO_led_IT (void); +void ADC_IT(void); +void UART_RX_IT(void); +void UART_TX_IT(void); int main ( void ) { myADC.ADC=ADC1; myADC.channel=2; MyADC_init(&myADC); - MyADC_ActiveIT(myADC.ADC,0,&Mafonction_IT2); + MyADC_ActiveIT(myADC.ADC,4,&ADC_IT); MyADC_start_conversion(myADC.ADC); + + MyUART_init(); + MyUART_ActiveIT(1, &UART_RX_IT, 'r'); //mode permet d'activer soit l'interruption sur RX (mode=0) soit TX (mode=1) + MyUART_ActiveIT(3, &UART_TX_IT, 't'); //mode permet d'activer soit l'interruption sur RX (mode=0) soit TX (mode=1) + sprintf(buffer_tx,"Test"); + while(1) { } @@ -27,12 +41,40 @@ int main ( void ) -void Mafonction_IT (void) +void GPIO_led_IT (void) { MyGPIO_Toggle(PA5.GPIO,5); } -void Mafonction_IT2 (void) +void ADC_IT (void) { val_adc=MyADC_result(myADC.ADC); } + +void UART_TX_IT (void) +{ + if(buffer_tx[cpt_buff_tx]!=0) + { + UART_send(buffer_tx[cpt_buff_tx]); + cpt_buff_tx++; + } + else + { + cpt_buff_tx=0; + memset(buffer_tx, 0, sizeof buffer_tx); + } + +} + +void UART_RX_IT (void) +{ + if((cpt_buff_rx!=-1)&&(cpt_buff_rx<100)) + { + buffer_rx[cpt_buff_rx]=UART_receive(); + } + else + { + cpt_buff_rx=0; + memset(buffer_rx, 0, sizeof buffer_rx); + } +} \ No newline at end of file diff --git a/Projet_voile/TP1.uvoptx b/Projet_voile/TP1.uvoptx index 9b7ddad..38a78b5 100644 --- a/Projet_voile/TP1.uvoptx +++ b/Projet_voile/TP1.uvoptx @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=1184,109,1560,666,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=733,260,1154,687,0)(121=-1,-1,-1,-1,0)(122=1345,565,1766,992,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=335,254,929,1005,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=1126,210,1574,624,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=298,316,901,1067,0)(151=-1,-1,-1,-1,0) + (1010=984,109,1360,666,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=733,260,1154,687,0)(121=-1,-1,-1,-1,0)(122=939,341,1360,768,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=335,17,929,768,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=695,235,1143,649,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=298,17,901,768,0)(151=-1,-1,-1,-1,0) 0 @@ -142,9 +142,9 @@ 0 0 - 37 + 31 1 -
134218114
+
134219858
0 0 0 @@ -153,9 +153,21 @@ 1 .\Sources\Principal.c - \\TP1\Sources/Principal.c\37 + \\TP1\Sources/Principal.c\31 + + + 0 + 1 + mode + + + 1 + 1 + ADC + + 0 @@ -176,7 +188,7 @@ 0 0 0 - 1 + 0 0 0 0 @@ -207,13 +219,9 @@ - System Viewer\ADC1 + System Viewer\USART1 35905 - - System Viewer\TIM2 - 35904 - 1 @@ -439,7 +447,7 @@ 1 3 1 - 1 + 0 0 0 ..\Drivers\Src\TIMER.c diff --git a/Projet_voile/TP1.uvprojx b/Projet_voile/TP1.uvprojx index 4c5f056..8e098ec 100644 --- a/Projet_voile/TP1.uvprojx +++ b/Projet_voile/TP1.uvprojx @@ -10,13 +10,13 @@ Simulé 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::.\ARMCC - 0 + 6190000::V6.19::ARMCLANG + 1 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.3.0 + Keil.STM32F1xx_DFP.2.4.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -33,8 +33,8 @@ - $$Device:STM32F103RB$SVD\STM32F103xx.svd - 0 + C:\Users\noelj\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\SVD\STM32F103xx.SFR + 1 0 @@ -186,6 +186,7 @@ 0 0 0 + 0 0 0 8 @@ -313,7 +314,7 @@ 1 - 1 + 2 0 0 1 @@ -322,14 +323,14 @@ 0 0 0 - 2 + 3 0 0 0 0 0 - 3 - 3 + 1 + 5 1 1 0 @@ -339,7 +340,7 @@ - .\Includes;..\Drivers\Inc + ..\Drivers\Inc @@ -598,6 +599,7 @@ 0 0 0 + 0 0 0 8 @@ -835,15 +837,15 @@ - - + + - + @@ -854,7 +856,7 @@ RTE\Device\STM32F103RB\RTE_Device.h - + @@ -863,7 +865,7 @@ RTE\Device\STM32F103RB\startup_stm32f10x_md.s - + @@ -872,7 +874,7 @@ RTE\Device\STM32F103RB\system_stm32f10x.c - + From a6bd0409e62851f6bbab0a185001da1200a97f63 Mon Sep 17 00:00:00 2001 From: Olivier Chevilley Date: Tue, 4 Apr 2023 12:58:52 +0200 Subject: [PATCH 5/6] =?UTF-8?q?UART=20fini=20et=20test=C3=A9=20mais=20sans?= =?UTF-8?q?=20DMA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Drivers/Inc/GPIO.h | 15 +++--- Drivers/Inc/UART.h | 6 +-- Drivers/Src/ADC.c | 2 +- Drivers/Src/TIMER.c | 2 +- Drivers/Src/UART.c | 63 +++++++++++----------- Projet_voile/Sources/Principal.c | 91 ++++++++------------------------ Projet_voile/TP1.uvoptx | 44 +++++++++------ Projet_voile/TP1.uvprojx | 24 ++++----- 8 files changed, 110 insertions(+), 137 deletions(-) diff --git a/Drivers/Inc/GPIO.h b/Drivers/Inc/GPIO.h index 3b8deb3..2bd5695 100644 --- a/Drivers/Inc/GPIO.h +++ b/Drivers/Inc/GPIO.h @@ -1,12 +1,6 @@ #ifndef MYGPIO_H #define MYGPIO_H #include "stm32f10x.h" -typedef struct -{ - GPIO_TypeDef * GPIO ; - char GPIO_Pin ; // numero de 0 a 15 - char GPIO_Conf ; // voir ci dessous -} MyGPIO_Struct_TypeDef ; #define In_Floating 0x4 // a completer #define In_PullDown 0x8 @@ -17,6 +11,15 @@ typedef struct #define AltOut_Ppull 0xA // deux derniers bits pour regler la vitesse max (due a la valeur de res) (01:10MHz 10:2MHz 11:50MHz) #define AltOut_OD 0xD // deux derniers bits pour regler la vitesse max (due a la valeur de res) (01:10MHz 10:2MHz 11:50MHz) +typedef struct +{ + GPIO_TypeDef * GPIO ; + char GPIO_Pin ; // numero de 0 a 15 + char GPIO_Conf ; // voir ci dessous +} MyGPIO_Struct_TypeDef ; + + + void MyGPIO_Init ( MyGPIO_Struct_TypeDef * GPIOStructPtr ) ; int MyGPIO_Read ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; // renvoie 0 ou autre chose different de 0 void MyGPIO_Set ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; diff --git a/Drivers/Inc/UART.h b/Drivers/Inc/UART.h index 398b87b..7a2fdcc 100644 --- a/Drivers/Inc/UART.h +++ b/Drivers/Inc/UART.h @@ -3,8 +3,8 @@ #include "stm32f10x.h" void MyUART_init(void); -void UART_send(char data); //à revoir -void MyUART_ActiveIT(char Prio, void (*IT_function)(void), char mode); //mode permet d'activer soit l'interruption sur RX (mode='r') soit TX (mode='t') -char UART_receive(); +void UART_send(char data); +void MyUART_ActiveIT(char Prio, void (*IT_function)(void)); +char UART_receive(void); #endif diff --git a/Drivers/Src/ADC.c b/Drivers/Src/ADC.c index 50fa86a..55fdf88 100644 --- a/Drivers/Src/ADC.c +++ b/Drivers/Src/ADC.c @@ -188,4 +188,4 @@ int MyADC_result(ADC_TypeDef* ADC) return ADC2->DR & ~((0x0F) << 12); // retour de la conversion } return 0; -} \ No newline at end of file +} diff --git a/Drivers/Src/TIMER.c b/Drivers/Src/TIMER.c index 8b0fe3b..76e67aa 100644 --- a/Drivers/Src/TIMER.c +++ b/Drivers/Src/TIMER.c @@ -88,7 +88,7 @@ void TIM4_IRQHandler (void) TIM4->SR &= ~(1<<0) ; } -void TIM1_UP_IRQHandler (void) // à vérifier +void TIM1_UP_IRQHandler (void) { if(tim_ptr1_func!=0) { diff --git a/Drivers/Src/UART.c b/Drivers/Src/UART.c index e89e7f6..b84c1a6 100644 --- a/Drivers/Src/UART.c +++ b/Drivers/Src/UART.c @@ -1,4 +1,5 @@ #include "UART.h" +#include "GPIO.h" void (*uart_rx_ptr_func)(void); void (*uart_tx_ptr_func)(void); @@ -6,34 +7,45 @@ char buffer[1000]={0}; void MyUART_init(void) // que pour du 9600 bauds { - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // validation horloge USART1 - USART1->CR1 |= USART_CR1_UE; // Activation de l'USART - USART1->CR1 &= ~USART_CR1_M; // Choix d'une taille de 8 bits de données - USART1->CR2 &= USART_CR2_STOP; // Choix d'un seul bit de stop - USART1->BRR |= 468 << 4; // Fixe le baud rate à 9600bps //valeurs trouvé p804 - USART1->BRR |= 75; // Fixe le baud rate à 9600bps - USART1->CR1 |= USART_CR1_TE; // Envoi de la première trame d'attente + MyGPIO_Struct_TypeDef RX_pin; + MyGPIO_Struct_TypeDef TX_pin; + + RX_pin.GPIO = GPIOA; + RX_pin.GPIO_Conf = In_Floating; + RX_pin.GPIO_Pin = 10; + + TX_pin.GPIO = GPIOA; + TX_pin.GPIO_Conf = AltOut_Ppull; + TX_pin.GPIO_Pin = 9; + + MyGPIO_Init (&RX_pin); + MyGPIO_Init (&TX_pin); + + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // validation horloge USART1 + USART1->CR1 |= USART_CR1_UE; // Activation de l'USART + USART1->CR1 &= ~USART_CR1_M; // Choix d'une taille de 8 bits de données + USART1->CR2 &= USART_CR2_STOP; // Choix d'un seul bit de stop + USART1->BRR |= 468 << 4; // Fixe le baud rate à 9600bps //valeurs trouvé p804 + USART1->BRR |= 75; // Fixe le baud rate à 9600bps + USART1->CR1 |= USART_CR1_RE; + USART1->CR1 |= USART_CR1_TE; } void UART_send(char data) { - USART1->DR |= data; // Ecriture de la donnée dans le registre DR + while(!(USART1->SR & USART_SR_TXE)) + { + } + USART1->DR = data; // Ecriture de la donnée dans le registre DR } -void MyUART_ActiveIT(char Prio, void (*IT_function)(void), char mode) +void MyUART_ActiveIT(char Prio, void (*IT_function)(void)) { - if (mode=='r') - { - USART1->CR1 |= USART_CR1_RXNEIE; - uart_rx_ptr_func=IT_function; - } - else if (mode=='t') - { - USART1->CR1 |= USART_CR1_TXEIE; - uart_tx_ptr_func=IT_function; - } + //activer l'interrupt sur reception + USART1->CR1 |= USART_CR1_RXNEIE; + uart_rx_ptr_func=IT_function; NVIC->ISER[1] |= 0x01<<(USART1_IRQn%32); - NVIC->IP[USART1_IRQn] |= Prio << 4; + NVIC->IP[USART1_IRQn] |= Prio << 4; } void USART1_IRQHandler() @@ -46,18 +58,9 @@ void USART1_IRQHandler() (*uart_rx_ptr_func)(); } } - else if (USART1->SR & USART_SR_TXE) // à revoir car si rien dedans il va tout le temps y retourner vu qu'il est vide - { - USART1->SR &= ~USART_SR_TXE; - if(uart_tx_ptr_func!=0) - { - (*uart_tx_ptr_func)(); - } - } - } char UART_receive() { - return USART1->DR; + return USART1->DR; // on recupere dans DR } diff --git a/Projet_voile/Sources/Principal.c b/Projet_voile/Sources/Principal.c index 7dff07f..2b8afb2 100644 --- a/Projet_voile/Sources/Principal.c +++ b/Projet_voile/Sources/Principal.c @@ -2,79 +2,34 @@ #include #include #include "GPIO.h" -#include "TIMER.h" -#include "ADC.h" #include "UART.h" -int val_adc=0; -int cpt_buff_tx=0; -int cpt_buff_rx=0; -MyGPIO_Struct_TypeDef PA5; //PA5 LED -MyGPIO_Struct_TypeDef PC13; //PC13 Bouton -MyTimer_Struct_TypeDef timer2; -MyADC_Struct_TypeDef myADC; -char buffer_tx[100]={0}; -char buffer_rx[100]={0}; -void GPIO_led_IT (void); -void ADC_IT(void); -void UART_RX_IT(void); -void UART_TX_IT(void); +char MyChar; -int main ( void ) -{ - myADC.ADC=ADC1; - myADC.channel=2; - MyADC_init(&myADC); - MyADC_ActiveIT(myADC.ADC,4,&ADC_IT); - MyADC_start_conversion(myADC.ADC); - - MyUART_init(); - MyUART_ActiveIT(1, &UART_RX_IT, 'r'); //mode permet d'activer soit l'interruption sur RX (mode=0) soit TX (mode=1) - MyUART_ActiveIT(3, &UART_TX_IT, 't'); //mode permet d'activer soit l'interruption sur RX (mode=0) soit TX (mode=1) - sprintf(buffer_tx,"Test"); - - while(1) - { - } - -} - - - -void GPIO_led_IT (void) -{ - MyGPIO_Toggle(PA5.GPIO,5); -} - -void ADC_IT (void) -{ - val_adc=MyADC_result(myADC.ADC); -} - -void UART_TX_IT (void) -{ - if(buffer_tx[cpt_buff_tx]!=0) - { - UART_send(buffer_tx[cpt_buff_tx]); - cpt_buff_tx++; - } - else - { - cpt_buff_tx=0; - memset(buffer_tx, 0, sizeof buffer_tx); - } - -} +//MyGPIO_Struct_TypeDef PA5; //PA5 LED +//MyGPIO_Struct_TypeDef PC13; //PC13 Bouton void UART_RX_IT (void) { - if((cpt_buff_rx!=-1)&&(cpt_buff_rx<100)) + MyChar=UART_receive(); +} + +int main ( void ) +{ + MyGPIO_Struct_TypeDef myGPIO; + myGPIO.GPIO = GPIOA; + myGPIO.GPIO_Conf = Out_Ppull; + myGPIO.GPIO_Pin = 5; + + MyGPIO_Init (&myGPIO); + + MyUART_init(); + MyUART_ActiveIT(1, &UART_RX_IT); //mode permet d'activer soit l'interruption sur TX + + while(1) { - buffer_rx[cpt_buff_rx]=UART_receive(); + } - else - { - cpt_buff_rx=0; - memset(buffer_rx, 0, sizeof buffer_rx); - } -} \ No newline at end of file +} + + diff --git a/Projet_voile/TP1.uvoptx b/Projet_voile/TP1.uvoptx index 38a78b5..4d68f84 100644 --- a/Projet_voile/TP1.uvoptx +++ b/Projet_voile/TP1.uvoptx @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=984,109,1360,666,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=733,260,1154,687,0)(121=-1,-1,-1,-1,0)(122=939,341,1360,768,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=335,17,929,768,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=695,235,1143,649,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=298,17,901,768,0)(151=-1,-1,-1,-1,0) + (1010=984,109,1360,666,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1084,185,1505,612,0)(121=-1,-1,-1,-1,0)(122=939,341,1360,768,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=335,17,929,768,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=1177,417,1625,831,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=298,17,901,768,0)(151=-1,-1,-1,-1,0) 0 @@ -142,9 +142,9 @@ 0 0 - 31 + 15 1 -
134219858
+
134219150
0 0 0 @@ -153,7 +153,7 @@ 1 .\Sources\Principal.c - \\TP1\Sources/Principal.c\31 + \\TP1\Sources/Principal.c\15 @@ -167,6 +167,26 @@ 1 ADC + + 2 + 1 + MyChar + + + 3 + 1 + RX_pin + + + 4 + 1 + RX_pin + + + 5 + 1 + MyChar + 0 @@ -217,12 +237,6 @@ FF000000000000000000000000000000E0FFEF400100000000000000000000000000000028504F5254412026203078303030303030323029203E3E2035000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F170000000000000000000000000000000000000090020008 - - - System Viewer\USART1 - 35905 - - 1 1 @@ -337,7 +351,7 @@ 0 DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=318,388,739,793,0)(121=1101,403,1522,808,0)(122=1281,393,1702,798,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=318,388,739,793,0)(121=1101,403,1522,808,0)(122=1281,393,1702,798,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=1106,213,1554,627,1)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 0 @@ -369,7 +383,7 @@ 1 1 0 - 0 + 1 0 0 1 @@ -381,7 +395,7 @@ 0 0 0 - 1 + 0 0 0 0 @@ -459,7 +473,7 @@ 1 4 1 - 1 + 0 0 0 ..\Drivers\Src\ADC.c @@ -471,7 +485,7 @@ 1 5 1 - 1 + 0 0 0 ..\Drivers\Src\UART.c diff --git a/Projet_voile/TP1.uvprojx b/Projet_voile/TP1.uvprojx index 8e098ec..3755d44 100644 --- a/Projet_voile/TP1.uvprojx +++ b/Projet_voile/TP1.uvprojx @@ -10,13 +10,13 @@ Simulé 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG - 1 + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.4.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -186,7 +186,6 @@ 0 0 0 - 0 0 0 8 @@ -314,7 +313,7 @@ 1 - 2 + 1 0 0 1 @@ -323,7 +322,7 @@ 0 0 0 - 3 + 2 0 0 0 @@ -599,7 +598,6 @@ 0 0 0 - 0 0 0 8 @@ -837,15 +835,15 @@ - - + + - + @@ -856,7 +854,7 @@ RTE\Device\STM32F103RB\RTE_Device.h - + @@ -865,7 +863,7 @@ RTE\Device\STM32F103RB\startup_stm32f10x_md.s - + @@ -874,7 +872,7 @@ RTE\Device\STM32F103RB\system_stm32f10x.c - + From 695a1f765d2b68a981f4b856cc6a92650d7397ee Mon Sep 17 00:00:00 2001 From: Olivier Chevilley Date: Tue, 4 Apr 2023 15:19:16 +0200 Subject: [PATCH 6/6] =?UTF-8?q?Code=20bugg=C3=A9=20depuis=20l'ajout=20du?= =?UTF-8?q?=20truc=20de=20GPIO.c?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Drivers/Inc/GPIO.h | 1 + Drivers/Src/GPIO.c | 40 +++++++++++++++++++++++++++++++ Drivers/Src/TIMER.c | 6 +++++ Drivers/Src/UART.c | 1 - Projet_voile/Includes/Girouette.h | 8 +++++++ Projet_voile/Sources/Girouette.c | 13 ++++++++++ Projet_voile/TP1.uvoptx | 36 ++++++++++++++++++---------- Projet_voile/TP1.uvprojx | 12 +++++++++- 8 files changed, 103 insertions(+), 14 deletions(-) create mode 100644 Projet_voile/Includes/Girouette.h create mode 100644 Projet_voile/Sources/Girouette.c diff --git a/Drivers/Inc/GPIO.h b/Drivers/Inc/GPIO.h index 2bd5695..d84a12b 100644 --- a/Drivers/Inc/GPIO.h +++ b/Drivers/Inc/GPIO.h @@ -25,5 +25,6 @@ int MyGPIO_Read ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; // renvoie 0 ou autre void MyGPIO_Set ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; void MyGPIO_Reset ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; void MyGPIO_Toggle ( GPIO_TypeDef * GPIO , char GPIO_Pin ) ; +void MyGPIO_ActiveIT (GPIO_TypeDef * GPIO, char GPIO_Pin, char Prio, void (*IT_function)(void)) #endif diff --git a/Drivers/Src/GPIO.c b/Drivers/Src/GPIO.c index a6b0668..e7b522f 100644 --- a/Drivers/Src/GPIO.c +++ b/Drivers/Src/GPIO.c @@ -1,5 +1,8 @@ #include "GPIO.h" +void (*gpio_ptr_func)(void); +// interruption NVIC p197 RM8 et ISER p119 + void MyGPIO_Init ( MyGPIO_Struct_TypeDef * GPIOStructPtr ) { if(GPIOStructPtr->GPIO==GPIOA) @@ -68,3 +71,40 @@ void MyGPIO_Toggle ( GPIO_TypeDef * GPIO , char GPIO_Pin ) } } +void MyGPIO_ActiveIT (GPIO_TypeDef * GPIO, char GPIO_Pin, char Prio, void (*IT_function)(void)) //p210 +{ + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; + if (GPIO==GPIOA) + { + AFIO->EXTICR[0] |= (AFIO_EXTICR1_EXTI0_PA << (4*GPIO_Pin)); + } + else if (GPIO==GPIOB) + { + AFIO->EXTICR[0] |= (AFIO_EXTICR1_EXTI0_PB << (4*GPIO_Pin)); + } + else if (GPIO==GPIOC) + { + AFIO->EXTICR[0] |= (AFIO_EXTICR1_EXTI0_PC << (4*GPIO_Pin)); + } + else if (GPIO==GPIOD) + { + AFIO->EXTICR[0] |= (AFIO_EXTICR1_EXTI0_PD << (4*GPIO_Pin)); + } + // manque ligne pour activer l'interruption + NVIC->ISER[0] |= 0x01<IP[EXTI0_IRQn] |= Prio << 4; +} + +void EXTI0_IRQHandler(void) +{ + if (EXTI->RTSR) //on test si RTSR est différent de 0 + { + if(gpio_ptr_func!=0) + { + (*gpio_ptr_func)(); + } + } + EXTI->RTSR &=0xFFFFF; + + //reset flag +} diff --git a/Drivers/Src/TIMER.c b/Drivers/Src/TIMER.c index 76e67aa..e1aa544 100644 --- a/Drivers/Src/TIMER.c +++ b/Drivers/Src/TIMER.c @@ -61,6 +61,12 @@ void MyTimer_ActiveIT (TIM_TypeDef * Timer, char Prio, void (*IT_function)(void) } +void init_encoder_timer(TIM_TypeDef * Timer) //voir page 391 +{ + Timer->SMCR = 0x1; + +} + void TIM2_IRQHandler (void) { if(tim_ptr2_func!=0) diff --git a/Drivers/Src/UART.c b/Drivers/Src/UART.c index b84c1a6..0aa7a02 100644 --- a/Drivers/Src/UART.c +++ b/Drivers/Src/UART.c @@ -2,7 +2,6 @@ #include "GPIO.h" void (*uart_rx_ptr_func)(void); -void (*uart_tx_ptr_func)(void); char buffer[1000]={0}; void MyUART_init(void) // que pour du 9600 bauds diff --git a/Projet_voile/Includes/Girouette.h b/Projet_voile/Includes/Girouette.h new file mode 100644 index 0000000..d3eb84e --- /dev/null +++ b/Projet_voile/Includes/Girouette.h @@ -0,0 +1,8 @@ +#ifndef MYGIROUETTE_H +#define MYGIROUETTE_H +#include "stm32f10x.h" +#include "GPIO.h" + + + +#endif diff --git a/Projet_voile/Sources/Girouette.c b/Projet_voile/Sources/Girouette.c new file mode 100644 index 0000000..634c02e --- /dev/null +++ b/Projet_voile/Sources/Girouette.c @@ -0,0 +1,13 @@ +#include "Girouette.h" + +int bordage(void){ + /*MyGPIO_Struct_TypeDef signalA = (GPIOC, 6, In_PullDown); + MyGPIO_Struct_TypeDef signalB = (GPIOC, 7, In_PullDown); + MyGPIO_Struct_TypeDef signalI = (GPIOC, 8, In_PullDown); + + MyGPIO_Init(&signalA); + MyGPIO_Init(&signalB); + MyGPIO_Init(&signalI);*/ + + +} \ No newline at end of file diff --git a/Projet_voile/TP1.uvoptx b/Projet_voile/TP1.uvoptx index 4d68f84..bc6d311 100644 --- a/Projet_voile/TP1.uvoptx +++ b/Projet_voile/TP1.uvoptx @@ -144,16 +144,16 @@ 0 15 1 -
134219150
+
0
0 0 0 0 0 - 1 + 0 .\Sources\Principal.c - \\TP1\Sources/Principal.c\15 + @@ -194,9 +194,9 @@ 0 1 - 1 + 0 0 - 1 + 0 0 0 1 @@ -449,7 +449,19 @@ 1 2 1 - 0 + 1 + 0 + 0 + .\Sources\Girouette.c + Girouette.c + 0 + 0 + + + 1 + 3 + 1 + 1 0 0 ..\DRIVERS\Src\GPIO.c @@ -459,9 +471,9 @@ 1 - 3 + 4 1 - 0 + 1 0 0 ..\Drivers\Src\TIMER.c @@ -471,9 +483,9 @@ 1 - 4 + 5 1 - 0 + 1 0 0 ..\Drivers\Src\ADC.c @@ -483,9 +495,9 @@ 1 - 5 + 6 1 - 0 + 1 0 0 ..\Drivers\Src\UART.c diff --git a/Projet_voile/TP1.uvprojx b/Projet_voile/TP1.uvprojx index 3755d44..e03a12f 100644 --- a/Projet_voile/TP1.uvprojx +++ b/Projet_voile/TP1.uvprojx @@ -339,7 +339,7 @@ - ..\Drivers\Inc + ..\Drivers\Inc;.\Includes @@ -388,6 +388,11 @@ 1 .\Sources\Principal.c + + Girouette.c + 1 + .\Sources\Girouette.c + GPIO.c 1 @@ -800,6 +805,11 @@ 1 .\Sources\Principal.c + + Girouette.c + 1 + .\Sources\Girouette.c + GPIO.c 1