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reorganisation du code de dumber et passage à une version recente

Sébastien DI MERCURIO 5 years ago
parent
commit
b1d9461430
100 changed files with 46813 additions and 8221 deletions
  1. 0
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      software/raspberry/superviseur-robot/example/src/Makefile
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      software/raspberry/superviseur-robot/example/src/rtvideoExample.cpp
  3. 0
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      software/raspberry/superviseur-robot/example/src/serialExample.cpp
  4. 0
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      software/raspberry/superviseur-robot/example/src/uiExample.cpp
  5. 0
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      software/raspberry/superviseur-robot/example/src/videoExample.cpp
  6. 284
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      software/robot/.gitignore
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      software/robot/.settings/com.atollic.truestudio.debug.hardware_device.prefs
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  11. 11
    0
      software/robot/.settings/org.eclipse.cdt.managedbuilder.core.prefs
  12. 0
    193
      software/robot/Battery.c
  13. 0
    17
      software/robot/Battery.h
  14. 0
    1094
      software/robot/Boot/system_stm32f10x.c
  15. 0
    97
      software/robot/DebugConfig/Target_1_STM32F103RB.dbgconf
  16. 0
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      software/robot/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf
  17. 40
    0
      software/robot/Dumber-Robot-Firmware.elf.launch
  18. 0
    9
      software/robot/EventRecorderStub.scvd
  19. BIN
      software/robot/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
  20. 8388
    0
      software/robot/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h
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  23. 35
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      software/robot/Libraries/CMSIS/Include/core_cmFunc.h
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      software/robot/Libraries/CMSIS/Include/core_cmInstr.h
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      software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
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      software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
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      software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
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      software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
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  48. 141
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  49. 537
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  50. 493
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  52. 429
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  53. 121
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  54. 231
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  55. 1313
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  60. 577
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  61. 168
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  62. 720
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  63. 275
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  64. 1685
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  65. 872
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  66. 656
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  67. 1337
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  68. 196
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  69. 313
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  70. 1476
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  71. 358
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  72. 804
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  73. 914
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  74. 2896
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  75. 1065
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  76. 230
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  77. 0
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  95. 0
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      software/robot/SPI.c
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      software/robot/cmde_spi.c
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      software/robot/cmde_usart.c
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      software/robot/cmde_usart.h

software/raspberry/superviseur-robot/example/Makefile → software/raspberry/superviseur-robot/example/src/Makefile View File


software/raspberry/superviseur-robot/example/rtvideoExample.cpp → software/raspberry/superviseur-robot/example/src/rtvideoExample.cpp View File


software/raspberry/superviseur-robot/example/serialExample.cpp → software/raspberry/superviseur-robot/example/src/serialExample.cpp View File


software/raspberry/superviseur-robot/example/uiExample.cpp → software/raspberry/superviseur-robot/example/src/uiExample.cpp View File


software/raspberry/superviseur-robot/example/videoExample.cpp → software/raspberry/superviseur-robot/example/src/videoExample.cpp View File


+ 284
- 0
software/robot/.cproject View File

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+									<listOptionValue builtIn="false" value="../src"/>
215
+									<listOptionValue builtIn="false" value="../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
216
+									<listOptionValue builtIn="false" value="../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
217
+									<listOptionValue builtIn="false" value="../Libraries/CMSIS/Include"/>
218
+								</option>
219
+								<option id="com.atollic.truestudio.common_options.target.endianess.1967238277" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
220
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1875365386" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103C6" valueType="enumerated"/>
221
+								<option id="com.atollic.truestudio.common_options.target.instr_set.585318403" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
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+								<option id="com.atollic.truestudio.common_options.target.fpucore.302951526" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="com.atollic.truestudio.common_options.target.fpucore.None" valueType="enumerated"/>
223
+								<option id="com.atollic.truestudio.common_options.target.fpu.225902667" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1354058843" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.prep_data.588745643" name="Prepare dead data removal" superClass="com.atollic.truestudio.gpp.optimization.prep_data" value="true" valueType="boolean"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.252107689" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
227
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2129524145" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
228
+								<inputType id="com.atollic.truestudio.gpp.input.1229320757" superClass="com.atollic.truestudio.gpp.input"/>
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+							</tool>
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+								<option id="com.atollic.truestudio.common_options.target.endianess.463874311" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
232
+								<option id="com.atollic.truestudio.common_options.target.mcpu.310965165" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103C6" valueType="enumerated"/>
233
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1819338136" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
234
+								<option id="com.atollic.truestudio.common_options.target.fpucore.1383712909" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="com.atollic.truestudio.common_options.target.fpucore.None" valueType="enumerated"/>
235
+								<option id="com.atollic.truestudio.common_options.target.fpu.740897850" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>
236
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1252563406" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
237
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1933119698" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="../stm32_flash.ld" valueType="string"/>
238
+								<inputType id="com.atollic.truestudio.ldcc.input.889935215" name="Input" superClass="com.atollic.truestudio.ldcc.input">
239
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
240
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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245
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246
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+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Libraries"/>
249
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250
+					</sourceEntries>
251
+				</configuration>
252
+			</storageModule>
253
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
254
+		</cconfiguration>
255
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257
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
258
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.0;com.atollic.truestudio.exe.0.;com.atollic.truestudio.exe.debug.toolchain.gpp.1674232344;com.atollic.truestudio.gpp.input.1866433999">
259
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.atollic.truestudio.mbs.ARMToolsPerProjectProfileCPP"/>
260
+		</scannerConfigBuildInfo>
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+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.0;com.atollic.truestudio.exe.0.;com.atollic.truestudio.exe.debug.toolchain.gcc.336346342;com.atollic.truestudio.gcc.input.1356287886">
262
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.atollic.truestudio.mbs.ARMToolsPerProjectProfileC"/>
263
+		</scannerConfigBuildInfo>
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+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.1;com.atollic.truestudio.exe.1.;com.atollic.truestudio.exe.release.toolchain.gcc.116564969;com.atollic.truestudio.gcc.input.293180129">
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.atollic.truestudio.mbs.ARMToolsPerProjectProfileC"/>
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+		</scannerConfigBuildInfo>
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+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.1;com.atollic.truestudio.exe.1.;com.atollic.truestudio.exe.release.toolchain.gpp.1644109583;com.atollic.truestudio.gpp.input.1338307187">
268
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.atollic.truestudio.mbs.ARMToolsPerProjectProfileCPP"/>
269
+		</scannerConfigBuildInfo>
270
+	</storageModule>
271
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+		<project id="Dumber-Robot-Firmware.com.atollic.truestudio.exe.1270107101" name="Executable" projectType="com.atollic.truestudio.exe"/>
273
+	</storageModule>
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+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
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+	<storageModule moduleId="refreshScope" versionNumber="2">
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+		<configuration configurationName="Debug">
277
+			<resource resourceType="PROJECT" workspacePath="/Dumber-Robot-Firmware"/>
278
+		</configuration>
279
+		<configuration configurationName="Release">
280
+			<resource resourceType="PROJECT" workspacePath="/Dumber-Robot-Firmware"/>
281
+		</configuration>
282
+	</storageModule>
283
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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+</cproject>

+ 3
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software/robot/.gitignore View File

@@ -0,0 +1,3 @@
1
+/Debug/
2
+/html/
3
+

+ 27
- 0
software/robot/.project View File

@@ -0,0 +1,27 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<projectDescription>
3
+	<name>robot</name>
4
+	<comment></comment>
5
+	<projects>
6
+	</projects>
7
+	<buildSpec>
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+		<buildCommand>
9
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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+			<triggers>clean,full,incremental,</triggers>
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+			<arguments>
12
+			</arguments>
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+		</buildCommand>
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+		<buildCommand>
15
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
16
+			<triggers>full,incremental,</triggers>
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+			<arguments>
18
+			</arguments>
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+		</buildCommand>
20
+	</buildSpec>
21
+	<natures>
22
+		<nature>org.eclipse.cdt.core.cnature</nature>
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+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
24
+		<nature>org.eclipse.cdt.core.ccnature</nature>
25
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
26
+	</natures>
27
+</projectDescription>

+ 11
- 0
software/robot/.settings/com.atollic.truestudio.debug.hardware_device.prefs View File

@@ -0,0 +1,11 @@
1
+BOARD=None
2
+CODE_LOCATION=FLASH
3
+ENDIAN=Little-endian
4
+MCU=STM32F103C6
5
+MCU_VENDOR=STMicroelectronics
6
+MODEL=Pro
7
+PROBE=ST-LINK
8
+PROJECT_FORMAT_VERSION=2
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+TARGET=STM32
10
+VERSION=9.0.0
11
+eclipse.preferences.version=1

+ 23
- 0
software/robot/.settings/language.settings.xml View File

@@ -0,0 +1,23 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2
+<project>
3
+	<configuration id="com.atollic.truestudio.exe.debug.584431509" name="Debug">
4
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
5
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
6
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
7
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="-862055963807747175" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
8
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
9
+				<language-scope id="org.eclipse.cdt.core.g++"/>
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+			</provider>
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+		</extension>
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+	</configuration>
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+	<configuration id="com.atollic.truestudio.configuration.release.1711240076" name="Release">
14
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
15
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
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+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="-862055963807747175" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
18
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
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+				<language-scope id="org.eclipse.cdt.core.g++"/>
20
+			</provider>
21
+		</extension>
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+	</configuration>
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+</project>

+ 11
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software/robot/.settings/org.eclipse.cdt.managedbuilder.core.prefs View File

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+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.584431509/CPATH/operation=remove
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11
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.584431509/appendContributed=true

+ 0
- 193
software/robot/Battery.c View File

@@ -1,193 +0,0 @@
1
-#include "system_dumby.h"
2
-#include "Battery.h"
3
-#include "motor.h"
4
-#include <stm32f10x.h>
5
-
6
-
7
-
8
-
9
-uint16_t PrescalerValue = 0;
10
-uint16_t PWM_BATTERY_ON = 0xC0;
11
-uint16_t PWM_BATTERY_OFF = 0;
12
-TIM_TimeBaseInitTypeDef TIM_BaseTempsTimer;
13
-TIM_OCInitTypeDef TIM_PWMConfigure;
14
-
15
-
16
-ADC_InitTypeDef ADC_InitStructure;
17
-DMA_InitTypeDef DMA_BAT_InitStructure;
18
-__IO uint16_t ADCConvertedValue[16];
19
-
20
-
21
-
22
-
23
- /*
24
-	*	@brief Initialise les PIN Necessaire à la mesure de la batterie et à la detection d'une charge
25
-	* EXTI-11 PB11 pour la detection de charge.
26
-	* Pin : A0, A4, A3
27
-	*/
28
-
29
-void MAP_batteryPin(void)
30
-{
31
-		GPIO_InitTypeDef Init_Structure;
32
-		NVIC_InitTypeDef NVIC_InitStructure;
33
-		EXTI_InitTypeDef   EXTI_InitStructure;
34
-		/// Variable local necessaire à l'initialisation des structures
35
-	
36
-	
37
-	  /// Configure A3 en output / alternate fonction
38
-		Init_Structure.GPIO_Pin = GPIO_Pin_3;
39
-		Init_Structure.GPIO_Speed = GPIO_Speed_10MHz;
40
-		Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP;
41
-		GPIO_Init(GPIOA, &Init_Structure);
42
-		
43
-		/// Configure les PIN A0,A4 en input floating.
44
-		Init_Structure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_4;
45
-		Init_Structure.GPIO_Mode = GPIO_Mode_AIN;
46
-		GPIO_Init(GPIOA, &Init_Structure);
47
-	
48
-	
49
-		// Configure PB11 en input floating (à configurer en exti)
50
-		Init_Structure.GPIO_Pin = GPIO_Pin_11;
51
-		Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
52
-		GPIO_Init(GPIOB, &Init_Structure);
53
-	
54
-	  GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource11);
55
-	
56
-		EXTI_InitStructure.EXTI_Line = EXTI_Line11;
57
-		EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
58
-		EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;  
59
-		EXTI_InitStructure.EXTI_LineCmd = ENABLE;
60
-		EXTI_Init(&EXTI_InitStructure);
61
-		
62
-		NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
63
-		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x00;
64
-		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00;
65
-		NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
66
-		NVIC_Init(&NVIC_InitStructure);
67
-}
68
-
69
-
70
-
71
-
72
- /*
73
-	* Fonction necessaire au bon fonctionneemnt de la mesure de tension.
74
-  * DMA_BAT : Initialise la dma pour stocké les valeurs dans ADCConvertedValue[]
75
-	* On stockera 16 valeurs de façon à faire un moyennage.
76
-	*/
77
-
78
-
79
-void DMA_BAT(void)
80
-{
81
-	 /* DMA1 channel1 configuration ----------------------------------------------*/
82
-  DMA_DeInit(DMA1_Channel1);
83
-  DMA_BAT_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(ADC1->DR); //   ADC1_DR_Address;
84
-  DMA_BAT_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADCConvertedValue;
85
-  DMA_BAT_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
86
-  DMA_BAT_InitStructure.DMA_BufferSize = 16; // voir shcémas ci dessus
87
-  DMA_BAT_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
88
-  DMA_BAT_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
89
-  DMA_BAT_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
90
-  DMA_BAT_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
91
-  DMA_BAT_InitStructure.DMA_Mode = DMA_Mode_Normal;
92
-  DMA_BAT_InitStructure.DMA_Priority = DMA_Priority_High;
93
-  DMA_BAT_InitStructure.DMA_M2M = DMA_M2M_Disable;
94
-  DMA_Init(DMA1_Channel1, &DMA_BAT_InitStructure);
95
-	
96
-	DMA_Cmd(DMA1_Channel1, ENABLE);
97
-	DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE);
98
-}
99
-
100
-
101
- /*
102
-	* Demmarer acquisition
103
-	*/
104
-void startACQDMA(void)
105
-{
106
-		ADC_DMACmd(ADC1, ENABLE);
107
-		DMA_DeInit(DMA1_Channel1);
108
-		DMA_Init(DMA1_Channel1, &DMA_BAT_InitStructure);
109
-		DMA_Cmd(DMA1_Channel1, ENABLE);
110
-		DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE);
111
-}
112
- /*
113
-	* Configuration de l'ADC
114
-	*/
115
-void ADC1_CONFIG(void)
116
-{
117
- 
118
-	/* ADC1 configuration ------------------------------------------------------*/
119
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
120
-  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
121
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
122
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
123
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
124
-  ADC_InitStructure.ADC_NbrOfChannel = 1;
125
-  ADC_Init(ADC1, &ADC_InitStructure);
126
-
127
-  /* ADC1 regular channel1 configuration */ 
128
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_55Cycles5);
129
- // ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 2, ADC_SampleTime_55Cycles5);
130
- 
131
-  /* Start ADC1 Software Conversion */ 
132
-	ADC_Cmd(ADC1, ENABLE);
133
-	
134
-	ADC_StartCalibration(ADC1);
135
-  /* Check the end of ADC1 calibration */
136
-  while(ADC_GetCalibrationStatus(ADC1));
137
-
138
-  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
139
-}
140
-
141
-	/* voltagePrepare:
142
-	* Demarer acquisition de 16 valeurs de tension
143
-  */
144
-void voltagePrepare(void)
145
-{
146
-	DMA_BAT_InitStructure.DMA_BufferSize = 16;
147
-	//DMA_Init(DMA1_Channel1, &DMA_BAT_InitStructure);
148
-	ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_55Cycles5);
149
-	ADC_Cmd(ADC1, ENABLE);
150
-	startACQDMA();
151
-}
152
-
153
- /* INIT_IT_DMA:
154
-	* Initialise l'IT de fin d'acquisition
155
-	*/
156
-void INIT_IT_DMA(void)
157
-{
158
-	   NVIC_InitTypeDef NVIC_InitStructure;
159
-
160
-  /* Enable the USARTz Interrupt */
161
-  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;
162
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
163
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
164
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
165
-  NVIC_Init(&NVIC_InitStructure);
166
-}
167
-
168
-
169
-
170
-
171
- /*DMA1_Channel1_IRQHandler:
172
-	* Interuption DMA pour mettre à jour le flag de calcul de la moyenne des tensions récupérer.
173
-	*/
174
-void DMA1_Channel1_IRQHandler(void)
175
-{
176
-  //Test on DMA1 Channel1 Transfer Complete interrupt
177
-  if(DMA_GetITStatus(DMA1_IT_TC1))
178
-  {
179
-		Dumber.BatterieChecking=TRUE;
180
-   //Clear DMA1 Channel1 Half Transfer, Transfer Complete and Global interrupt pending bits
181
-    DMA_ClearITPendingBit(DMA1_IT_GL1);
182
-		
183
-  }
184
-}
185
-
186
- /*
187
-	* Interuption de detection de chargeur. shutDown le robot;
188
-	*/
189
-void EXTI15_10_IRQHandler(void)
190
-{
191
-	shutDown();
192
-	while(1);
193
-}

+ 0
- 17
software/robot/Battery.h View File

@@ -1,17 +0,0 @@
1
-#ifndef Battery_H
2
-#define Battery_H
3
-
4
-#include "stm32f10x.h"
5
-
6
- 
7
-
8
-extern __IO uint16_t ADCConvertedValue[16];
9
-void MAP_batteryPin(void);
10
-void DMA_BAT(void);
11
-void ADC1_CONFIG(void);
12
-void INIT_IT_DMA(void);
13
-void startACQDMA(void);
14
-void voltagePrepare(void);
15
-
16
-#endif /* Battery_H */
17
-

+ 0
- 1094
software/robot/Boot/system_stm32f10x.c
File diff suppressed because it is too large
View File


+ 0
- 97
software/robot/DebugConfig/Target_1_STM32F103RB.dbgconf View File

@@ -1,97 +0,0 @@
1
-// <<< Use Configuration Wizard in Context Menu >>>
2
-// <h> Debug MCU Configuration
3
-//   <o0.0>    DBG_SLEEP
4
-// <i> Debug Sleep Mode
5
-// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
6
-// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
7
-//   <o0.1>    DBG_STOP
8
-// <i> Debug Stop Mode
9
-// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10
-// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11
-//   <o0.2>    DBG_STANDBY
12
-// <i> Debug Standby Mode
13
-// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14
-// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15
-//   <o0.8>    DBG_IWDG_STOP
16
-// <i> Debug independent watchdog stopped when core is halted
17
-// <i> 0: The watchdog counter clock continues even if the core is halted
18
-// <i> 1: The watchdog counter clock is stopped when the core is halted
19
-//   <o0.9>    DBG_WWDG_STOP
20
-// <i> Debug window watchdog stopped when core is halted
21
-// <i> 0: The window watchdog counter clock continues even if the core is halted
22
-// <i> 1: The window watchdog counter clock is stopped when the core is halted
23
-//   <o0.10>   DBG_TIM1_STOP
24
-// <i> Timer 1 counter stopped when core is halted
25
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27
-//   <o0.11>   DBG_TIM2_STOP
28
-// <i> Timer 2 counter stopped when core is halted
29
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31
-//   <o0.12>   DBG_TIM3_STOP
32
-// <i> Timer 3 counter stopped when core is halted
33
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35
-//   <o0.13>   DBG_TIM4_STOP
36
-// <i> Timer 4 counter stopped when core is halted
37
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39
-//   <o0.14>   DBG_CAN1_STOP
40
-// <i> Debug CAN1 stopped when Core is halted
41
-// <i> 0: Same behavior as in normal mode
42
-// <i> 1: CAN1 receive registers are frozen
43
-//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44
-// <i> I2C1 SMBUS timeout mode stopped when Core is halted
45
-// <i> 0: Same behavior as in normal mode
46
-// <i> 1: The SMBUS timeout is frozen
47
-//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48
-// <i> I2C2 SMBUS timeout mode stopped when Core is halted
49
-// <i> 0: Same behavior as in normal mode
50
-// <i> 1: The SMBUS timeout is frozen
51
-//   <o0.17>   DBG_TIM8_STOP
52
-// <i> Timer 8 counter stopped when core is halted
53
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55
-//   <o0.18>   DBG_TIM5_STOP
56
-// <i> Timer 5 counter stopped when core is halted
57
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59
-//   <o0.19>   DBG_TIM6_STOP
60
-// <i> Timer 6 counter stopped when core is halted
61
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63
-//   <o0.20>   DBG_TIM7_STOP
64
-// <i> Timer 7 counter stopped when core is halted
65
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67
-//   <o0.21>   DBG_CAN2_STOP
68
-// <i> Debug CAN2 stopped when Core is halted
69
-// <i> 0: Same behavior as in normal mode
70
-// <i> 1: CAN2 receive registers are frozen
71
-//   <o0.25>   DBG_TIM12_STOP
72
-// <i> Timer 12 counter stopped when core is halted
73
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75
-//   <o0.26>   DBG_TIM13_STOP
76
-// <i> Timer 13 counter stopped when core is halted
77
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79
-//   <o0.27>   DBG_TIM14_STOP
80
-// <i> Timer 14 counter stopped when core is halted
81
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83
-//   <o0.28>   DBG_TIM9_STOP
84
-// <i> Timer 9 counter stopped when core is halted
85
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87
-//   <o0.29>   DBG_TIM10_STOP
88
-// <i> Timer 10 counter stopped when core is halted
89
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91
-//   <o0.30>   DBG_TIM11_STOP
92
-// <i> Timer 11 counter stopped when core is halted
93
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95
-// </h>
96
-DbgMCU_CR = 0x00000007;
97
-// <<< end of configuration section >>>

+ 0
- 97
software/robot/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf View File

@@ -1,97 +0,0 @@
1
-// <<< Use Configuration Wizard in Context Menu >>>
2
-// <h> Debug MCU Configuration
3
-//   <o0.0>    DBG_SLEEP
4
-// <i> Debug Sleep Mode
5
-// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
6
-// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
7
-//   <o0.1>    DBG_STOP
8
-// <i> Debug Stop Mode
9
-// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10
-// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11
-//   <o0.2>    DBG_STANDBY
12
-// <i> Debug Standby Mode
13
-// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14
-// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15
-//   <o0.8>    DBG_IWDG_STOP
16
-// <i> Debug independent watchdog stopped when core is halted
17
-// <i> 0: The watchdog counter clock continues even if the core is halted
18
-// <i> 1: The watchdog counter clock is stopped when the core is halted
19
-//   <o0.9>    DBG_WWDG_STOP
20
-// <i> Debug window watchdog stopped when core is halted
21
-// <i> 0: The window watchdog counter clock continues even if the core is halted
22
-// <i> 1: The window watchdog counter clock is stopped when the core is halted
23
-//   <o0.10>   DBG_TIM1_STOP
24
-// <i> Timer 1 counter stopped when core is halted
25
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27
-//   <o0.11>   DBG_TIM2_STOP
28
-// <i> Timer 2 counter stopped when core is halted
29
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31
-//   <o0.12>   DBG_TIM3_STOP
32
-// <i> Timer 3 counter stopped when core is halted
33
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35
-//   <o0.13>   DBG_TIM4_STOP
36
-// <i> Timer 4 counter stopped when core is halted
37
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39
-//   <o0.14>   DBG_CAN1_STOP
40
-// <i> Debug CAN1 stopped when Core is halted
41
-// <i> 0: Same behavior as in normal mode
42
-// <i> 1: CAN1 receive registers are frozen
43
-//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44
-// <i> I2C1 SMBUS timeout mode stopped when Core is halted
45
-// <i> 0: Same behavior as in normal mode
46
-// <i> 1: The SMBUS timeout is frozen
47
-//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48
-// <i> I2C2 SMBUS timeout mode stopped when Core is halted
49
-// <i> 0: Same behavior as in normal mode
50
-// <i> 1: The SMBUS timeout is frozen
51
-//   <o0.17>   DBG_TIM8_STOP
52
-// <i> Timer 8 counter stopped when core is halted
53
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55
-//   <o0.18>   DBG_TIM5_STOP
56
-// <i> Timer 5 counter stopped when core is halted
57
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59
-//   <o0.19>   DBG_TIM6_STOP
60
-// <i> Timer 6 counter stopped when core is halted
61
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63
-//   <o0.20>   DBG_TIM7_STOP
64
-// <i> Timer 7 counter stopped when core is halted
65
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67
-//   <o0.21>   DBG_CAN2_STOP
68
-// <i> Debug CAN2 stopped when Core is halted
69
-// <i> 0: Same behavior as in normal mode
70
-// <i> 1: CAN2 receive registers are frozen
71
-//   <o0.25>   DBG_TIM12_STOP
72
-// <i> Timer 12 counter stopped when core is halted
73
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75
-//   <o0.26>   DBG_TIM13_STOP
76
-// <i> Timer 13 counter stopped when core is halted
77
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79
-//   <o0.27>   DBG_TIM14_STOP
80
-// <i> Timer 14 counter stopped when core is halted
81
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83
-//   <o0.28>   DBG_TIM9_STOP
84
-// <i> Timer 9 counter stopped when core is halted
85
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87
-//   <o0.29>   DBG_TIM10_STOP
88
-// <i> Timer 10 counter stopped when core is halted
89
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91
-//   <o0.30>   DBG_TIM11_STOP
92
-// <i> Timer 11 counter stopped when core is halted
93
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95
-// </h>
96
-DbgMCU_CR = 0x00000007;
97
-// <<< end of configuration section >>>

+ 40
- 0
software/robot/Dumber-Robot-Firmware.elf.launch View File

@@ -0,0 +1,40 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
3
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
4
+<stringAttribute key="com.atollic.hardwaredebug.launch.hwinitCommands" value="# Initialize your hardware here&#10;"/>
5
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
6
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
7
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
8
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
9
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
10
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#10;#monitor flash set_parallelism_mode 2&#10;&#10;# Set character encoding&#10;set host-charset CP1252&#10;set target-charset CP1252&#10;&#10;# Reset to known state&#10;monitor reset&#10;&#10;# Load the program executable&#10;load&#9;&#9;&#10;&#10;# Reset the chip to get to a known state. Remove &quot;monitor reset&quot; command &#10;#  if the code is not located at default address and does not run by reset. &#10;monitor reset&#10;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#10;&#10;# Set a breakpoint at main().&#10;tbreak main&#10;&#10;# Run to the breakpoint.&#10;continue"/>
11
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d -z 61235 -a 8000000 -b 8 -s"/>
12
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
13
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
14
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
15
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
16
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
17
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
18
+<intAttribute key="com.atollic.hardwaredebug.launch.trace_system" value="1"/>
19
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
20
+<booleanAttribute key="com.atollic.hardwaredebug.launch.verify_flash_download" value="true"/>
21
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
22
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="/home/dimercur/Documents/Travail/git/dumber/software/robot/Debug/st-link_gdbserver_log.txt"/>
23
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.stlink_check_serial_number" value="false"/>
24
+<stringAttribute key="com.atollic.hardwaredebug.stlink.stlink_txt_serial_number" value=""/>
25
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
26
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
27
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
28
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/Dumber-Robot-Firmware.elf"/>
29
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Dumber-Robot-Firmware"/>
30
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
31
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
32
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
33
+<listEntry value="/Dumber-Robot-Firmware"/>
34
+</listAttribute>
35
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
36
+<listEntry value="4"/>
37
+</listAttribute>
38
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
39
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
40
+</launchConfiguration>

+ 0
- 9
software/robot/EventRecorderStub.scvd View File

@@ -1,9 +0,0 @@
1
-<?xml version="1.0" encoding="utf-8"?>
2
-
3
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
4
-
5
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
6
-  <events>
7
-  </events>
8
-
9
-</component_viewer>

BIN
software/robot/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf View File


+ 8388
- 0
software/robot/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h
File diff suppressed because it is too large
View File


+ 104
- 0
software/robot/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h View File

@@ -0,0 +1,104 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    system_stm32f10x.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    09-March-2012
7
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/** @addtogroup CMSIS
29
+  * @{
30
+  */
31
+
32
+/** @addtogroup stm32f10x_system
33
+  * @{
34
+  */  
35
+  
36
+/**
37
+  * @brief Define to prevent recursive inclusion
38
+  */
39
+#ifndef __SYSTEM_STM32F10X_H
40
+#define __SYSTEM_STM32F10X_H
41
+
42
+#ifdef __cplusplus
43
+ extern "C" {
44
+#endif 
45
+
46
+/** @addtogroup STM32F10x_System_Includes
47
+  * @{
48
+  */
49
+
50
+/**
51
+  * @}
52
+  */
53
+
54
+
55
+/** @addtogroup STM32F10x_System_Exported_types
56
+  * @{
57
+  */
58
+
59
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
60
+
61
+/**
62
+  * @}
63
+  */
64
+
65
+/** @addtogroup STM32F10x_System_Exported_Constants
66
+  * @{
67
+  */
68
+
69
+/**
70
+  * @}
71
+  */
72
+
73
+/** @addtogroup STM32F10x_System_Exported_Macros
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+  * @{
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+  */
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+
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+/**
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+  * @}
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+  */
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+
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+/** @addtogroup STM32F10x_System_Exported_Functions
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+  * @{
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+  */
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+  
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+extern void SystemInit(void);
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+extern void SystemCoreClockUpdate(void);
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+/**
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+  * @}
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+  */
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+
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+#ifdef __cplusplus
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+}
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+#endif
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+
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+#endif /*__SYSTEM_STM32F10X_H */
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+
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+/**
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+  * @}
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+  */
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+  
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+/**
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+  * @}
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+  */  
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+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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software/robot/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html View File

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+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
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+</o:p></span></p>
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+<div align="center">
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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+<tbody>
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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+<tbody>
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+          <tr>
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+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../../Release_Notes.html">Back to Release page</a></span></td>
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+          </tr>
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+<tr style="">
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+<td style="padding: 1.5pt;">
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+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
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+Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
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+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img style="border: 0px solid ; width: 86px; height: 65px;" src="../../../../../_htmresc/logo.bmp" id="_x0000_i1025" alt=""></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+</td>
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+</tr>
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+</tbody>
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+</table>
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+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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+<tbody>
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+<tr>
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+<td style="padding: 0cm;" valign="top">
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+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
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+<ol style="margin-top: 0cm;" start="1" type="1">
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+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS
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+update History</a><o:p></o:p></span></li>
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+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
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+</ol>
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+<span style="font-family: &quot;Times New Roman&quot;;"></span>
104
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS
105
+update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.1 / 09-March-2012<o:p></o:p></span></h3>
106
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
107
+Changes<o:p></o:p></span></u></b></p>
108
+
109
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.0 / 27-January-2012<o:p></o:p></span></h3>
110
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
111
+Changes<o:p></o:p></span></u></b></p>
112
+
113
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update directory structure&nbsp;to be compliant&nbsp;with CMSIS V2.1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the&nbsp;new license agreement</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for Cortex-M3 revision&nbsp;<span style="font-style: italic;">__CM3_REV</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Allow
114
+modification of&nbsp;some constants by the application code, definition of
115
+these constants is now bracketed by &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="font-style: italic;">#if !defined</span><span style="font-style: italic;"></span>. The concerned constant are <span style="font-style: italic;">HSE_VALUE</span>, <span style="font-style: italic;">HSI_VALUE</span> and <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for&nbsp;<span style="font-style: italic;">DAC CR</span> register</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for <span style="font-style: italic;">FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4</span> registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Definition for </span><span style="font-size: 10pt; font-family: Verdana;">Flash keys moved from stm32f10x_flash.c to stm32f10x.h<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add startup file for <span style="font-style: italic;">TASKING</span> toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; text-decoration: underline; font-style: italic;">V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1)</span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline; font-style: italic;">&nbsp;compatibility update</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Due to the </span><span style="font-size: 10pt; font-family: Verdana;"> directory structure </span><span style="font-size: 10pt; font-family: Verdana;">difference between&nbsp;CMSIS V1.3 and&nbsp;V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to </span><span style="font-size: 10pt; font-family: Verdana;">V3.6.0 </span><span style="font-size: 10pt; font-family: Verdana;">you need to perform the following update:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In
116
+the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3
117
+CMSIS files are included by default in your development toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove core_cm3.c file (if it is used).&nbsp;Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the compiler preprocessor, update&nbsp;path of&nbsp;</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> CMSIS</span> <span style="font-style: italic;">include</span> files from &nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\CM3\DeviceSupport\ST\</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">to</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Include</span><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the project settings, update path of <span style="font-style: italic;">startup_stm32f10x_xx.s</span> file&nbsp;from</span><span style="font-size: 10pt; font-family: Verdana;"> Libraries\CMSIS\CM3\DeviceSupport\ST\</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\startup\&#8221;Compiler&#8221;</span> to </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\&#8221;Compiler&#8221;</span></li></ul></ul></ul><div style="margin-left: 40px;"><div style="margin-left: 80px;"><span style="font-size: 10pt; font-family: Verdana;">where, "Compiler" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO</span><br></div><span style="font-size: 10pt; font-family: Verdana;"></span></div>
118
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
119
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
120
+Changes<o:p></o:p></span></u></b></p>
121
+
122
+            <ul style="margin-top: 0cm;" type="square">
123
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h
124
+</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt
125
+definition for STM32F10x High-density Value line devices.<br>
126
+</span></li>
127
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file&nbsp;provided within the CMSIS folder. <br>
128
+</span></li>
129
+
130
+            </ul>
131
+
132
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
133
+- 10/15/2010</span></h3>
134
+
135
+            <ol>
136
+<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>
137
+            </ol>
138
+
139
+            <ul style="margin-top: 0in;" type="disc">
140
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
141
+for&nbsp;<b>STM32F10x High-density Value line devices</b>.</span></li>
142
+            </ul>
143
+            <ol start="2">
144
+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>
145
+            </ol>
146
+
147
+
148
+            
149
+            <ul style="margin-top: 0in;" type="disc">
150
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
151
+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>
152
+                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>
153
+</ul>
154
+                <li class="MsoNormal" style="">
155
+
156
+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">All
157
+STM32 devices definitions are commented by default. User has to select the
158
+appropriate device before starting else an error will be signaled on compile
159
+time.</span></li>
160
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>
161
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
162
+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li>
163
+</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
164
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
165
+              <ul>
166
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
167
+<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
168
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>
169
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
170
+to select if the user want to place the Vector Table in internal SRAM.
171
+An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
172
+                  </span></li>
173
+
174
+              </ul>
175
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
176
+startup files for STM32 High-density Value line devices:
177
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>
178
+            </ul>
179
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
180
+- 04/16/2010</span></h3>
181
+
182
+<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
183
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
184
+for&nbsp;<b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
185
+
186
+            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
187
+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices&nbsp;(remove&nbsp;comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
188
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><br>
189
+                  </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
190
+startup files for STM32 XL-density&nbsp;devices:
191
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ&nbsp;Handler (was missing in&nbsp;previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
192
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
193
+- 03/01/2010</span></h3>
194
+<ol style="margin-top: 0in;" start="1" type="1">
195
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
196
+</ol>
197
+<ul style="margin-top: 0in;" type="disc">
198
+
199
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
200
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
201
+                </span></li>
202
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
203
+for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
204
+Medium-density Value line (STM32F100x8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
205
+
206
+</ul>
207
+<ol style="margin-top: 0in;" start="2" type="1">
208
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
209
+            <ul>
210
+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
211
+            </ul>
212
+            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
213
+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
214
+
215
+            </ol>
216
+
217
+            <ul style="margin-top: 0in;" type="disc">
218
+
219
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
220
+              </li>
221
+              <ul>
222
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
223
+the stm32f10x.h file to support new Value line devices features: CEC
224
+peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>
225
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
226
+                  </span></li>
227
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
228
+HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
229
+HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
230
+purposes.<br>
231
+                  </span></li>
232
+              </ul>
233
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
234
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
235
+              <ul>
236
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
237
+                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
238
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
239
+                  </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
240
+                  </span></li>
241
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
242
+                  </span></li>
243
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
244
+                  </span></li>
245
+              </ul>
246
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>
247
+              <ul>
248
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
249
+startup files for STM32 Low-density Value line devices:
250
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>
251
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
252
+files for STM32 Medium-density Value line devices:
253
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>
254
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
255
+To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
256
+</span></li>
257
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
258
+</span></li>
259
+              </ul>
260
+
261
+            </ul>
262
+
263
+<ul style="margin-top: 0in;" type="disc">
264
+</ul>
265
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
266
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
267
+required by applicable law or agreed to in writing, software
268
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
269
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
270
+the License for the specific language governing permissions and
271
+limitations under the License.</span>
272
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
273
+<hr align="center" size="2" width="100%"></span></div>
274
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
275
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
276
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
277
+</td>
278
+</tr>
279
+</tbody>
280
+</table>
281
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
282
+</td>
283
+</tr>
284
+</tbody>
285
+</table>
286
+</div>
287
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
288
+</div>
289
+</body></html>

+ 35
- 0
software/robot/Libraries/CMSIS/Include/arm_common_tables.h View File

@@ -0,0 +1,35 @@
1
+/* ---------------------------------------------------------------------- 
2
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
3
+* 
4
+* $Date:        11. November 2010  
5
+* $Revision: 	V1.0.2  
6
+* 
7
+* Project: 	    CMSIS DSP Library 
8
+* Title:	    arm_common_tables.h 
9
+* 
10
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
11
+* 
12
+* Target Processor: Cortex-M4/Cortex-M3
13
+*  
14
+* Version 1.0.2 2010/11/11 
15
+*    Documentation updated.  
16
+* 
17
+* Version 1.0.1 2010/10/05  
18
+*    Production release and review comments incorporated. 
19
+* 
20
+* Version 1.0.0 2010/09/20  
21
+*    Production release and review comments incorporated. 
22
+* -------------------------------------------------------------------- */ 
23
+ 
24
+#ifndef _ARM_COMMON_TABLES_H 
25
+#define _ARM_COMMON_TABLES_H 
26
+ 
27
+#include "arm_math.h" 
28
+ 
29
+extern uint16_t armBitRevTable[256]; 
30
+extern q15_t armRecipTableQ15[64]; 
31
+extern q31_t armRecipTableQ31[64]; 
32
+extern const q31_t realCoefAQ31[1024];
33
+extern const q31_t realCoefBQ31[1024];
34
+ 
35
+#endif /*  ARM_COMMON_TABLES_H */ 

+ 7051
- 0
software/robot/Libraries/CMSIS/Include/arm_math.h
File diff suppressed because it is too large
View File


+ 1236
- 0
software/robot/Libraries/CMSIS/Include/core_cm3.h
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+ 609
- 0
software/robot/Libraries/CMSIS/Include/core_cmFunc.h View File

@@ -0,0 +1,609 @@
1
+/**************************************************************************//**
2
+ * @file     core_cmFunc.h
3
+ * @brief    CMSIS Cortex-M Core Function Access Header File
4
+ * @version  V2.10
5
+ * @date     26. July 2011
6
+ *
7
+ * @note
8
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
9
+ *
10
+ * @par
11
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
12
+ * processor based microcontrollers.  This file can be freely distributed 
13
+ * within development tools that are supporting such ARM based processors. 
14
+ *
15
+ * @par
16
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21
+ *
22
+ ******************************************************************************/
23
+
24
+#ifndef __CORE_CMFUNC_H
25
+#define __CORE_CMFUNC_H
26
+
27
+
28
+/* ###########################  Core Function Access  ########################### */
29
+/** \ingroup  CMSIS_Core_FunctionInterface   
30
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
31
+  @{
32
+ */
33
+
34
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35
+/* ARM armcc specific functions */
36
+
37
+#if (__ARMCC_VERSION < 400677)
38
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39
+#endif
40
+
41
+/* intrinsic void __enable_irq();     */
42
+/* intrinsic void __disable_irq();    */
43
+
44
+/** \brief  Get Control Register
45
+
46
+    This function returns the content of the Control Register.
47
+
48
+    \return               Control Register value
49
+ */
50
+static __INLINE uint32_t __get_CONTROL(void)
51
+{
52
+  register uint32_t __regControl         __ASM("control");
53
+  return(__regControl);
54
+}
55
+
56
+
57
+/** \brief  Set Control Register
58
+
59
+    This function writes the given value to the Control Register.
60
+
61
+    \param [in]    control  Control Register value to set
62
+ */
63
+static __INLINE void __set_CONTROL(uint32_t control)
64
+{
65
+  register uint32_t __regControl         __ASM("control");
66
+  __regControl = control;
67
+}
68
+
69
+
70
+/** \brief  Get ISPR Register
71
+
72
+    This function returns the content of the ISPR Register.
73
+
74
+    \return               ISPR Register value
75
+ */
76
+static __INLINE uint32_t __get_IPSR(void)
77
+{
78
+  register uint32_t __regIPSR          __ASM("ipsr");
79
+  return(__regIPSR);
80
+}
81
+
82
+
83
+/** \brief  Get APSR Register
84
+
85
+    This function returns the content of the APSR Register.
86
+
87
+    \return               APSR Register value
88
+ */
89
+static __INLINE uint32_t __get_APSR(void)
90
+{
91
+  register uint32_t __regAPSR          __ASM("apsr");
92
+  return(__regAPSR);
93
+}
94
+
95
+
96
+/** \brief  Get xPSR Register
97
+
98
+    This function returns the content of the xPSR Register.
99
+
100
+    \return               xPSR Register value
101
+ */
102
+static __INLINE uint32_t __get_xPSR(void)
103
+{
104
+  register uint32_t __regXPSR          __ASM("xpsr");
105
+  return(__regXPSR);
106
+}
107
+
108
+
109
+/** \brief  Get Process Stack Pointer
110
+
111
+    This function returns the current value of the Process Stack Pointer (PSP).
112
+
113
+    \return               PSP Register value
114
+ */
115
+static __INLINE uint32_t __get_PSP(void)
116
+{
117
+  register uint32_t __regProcessStackPointer  __ASM("psp");
118
+  return(__regProcessStackPointer);
119
+}
120
+
121
+
122
+/** \brief  Set Process Stack Pointer
123
+
124
+    This function assigns the given value to the Process Stack Pointer (PSP).
125
+
126
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
127
+ */
128
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
129
+{
130
+  register uint32_t __regProcessStackPointer  __ASM("psp");
131
+  __regProcessStackPointer = topOfProcStack;
132
+}
133
+
134
+
135
+/** \brief  Get Main Stack Pointer
136
+
137
+    This function returns the current value of the Main Stack Pointer (MSP).
138
+
139
+    \return               MSP Register value
140
+ */
141
+static __INLINE uint32_t __get_MSP(void)
142
+{
143
+  register uint32_t __regMainStackPointer     __ASM("msp");
144
+  return(__regMainStackPointer);
145
+}
146
+
147
+
148
+/** \brief  Set Main Stack Pointer
149
+
150
+    This function assigns the given value to the Main Stack Pointer (MSP).
151
+
152
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
153
+ */
154
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
155
+{
156
+  register uint32_t __regMainStackPointer     __ASM("msp");
157
+  __regMainStackPointer = topOfMainStack;
158
+}
159
+
160
+
161
+/** \brief  Get Priority Mask
162
+
163
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
164
+
165
+    \return               Priority Mask value
166
+ */
167
+static __INLINE uint32_t __get_PRIMASK(void)
168
+{
169
+  register uint32_t __regPriMask         __ASM("primask");
170
+  return(__regPriMask);
171
+}
172
+
173
+
174
+/** \brief  Set Priority Mask
175
+
176
+    This function assigns the given value to the Priority Mask Register.
177
+
178
+    \param [in]    priMask  Priority Mask
179
+ */
180
+static __INLINE void __set_PRIMASK(uint32_t priMask)
181
+{
182
+  register uint32_t __regPriMask         __ASM("primask");
183
+  __regPriMask = (priMask);
184
+}
185
+ 
186
+
187
+#if       (__CORTEX_M >= 0x03)
188
+
189
+/** \brief  Enable FIQ
190
+
191
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
192
+    Can only be executed in Privileged modes.
193
+ */
194
+#define __enable_fault_irq                __enable_fiq
195
+
196
+
197
+/** \brief  Disable FIQ
198
+
199
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
200
+    Can only be executed in Privileged modes.
201
+ */
202
+#define __disable_fault_irq               __disable_fiq
203
+
204
+
205
+/** \brief  Get Base Priority
206
+
207
+    This function returns the current value of the Base Priority register.
208
+
209
+    \return               Base Priority register value
210
+ */
211
+static __INLINE uint32_t  __get_BASEPRI(void)
212
+{
213
+  register uint32_t __regBasePri         __ASM("basepri");
214
+  return(__regBasePri);
215
+}
216
+
217
+
218
+/** \brief  Set Base Priority
219
+
220
+    This function assigns the given value to the Base Priority register.
221
+
222
+    \param [in]    basePri  Base Priority value to set
223
+ */
224
+static __INLINE void __set_BASEPRI(uint32_t basePri)
225
+{
226
+  register uint32_t __regBasePri         __ASM("basepri");
227
+  __regBasePri = (basePri & 0xff);
228
+}
229
+ 
230
+
231
+/** \brief  Get Fault Mask
232
+
233
+    This function returns the current value of the Fault Mask register.
234
+
235
+    \return               Fault Mask register value
236
+ */
237
+static __INLINE uint32_t __get_FAULTMASK(void)
238
+{
239
+  register uint32_t __regFaultMask       __ASM("faultmask");
240
+  return(__regFaultMask);
241
+}
242
+
243
+
244
+/** \brief  Set Fault Mask
245
+
246
+    This function assigns the given value to the Fault Mask register.
247
+
248
+    \param [in]    faultMask  Fault Mask value to set
249
+ */
250
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
251
+{
252
+  register uint32_t __regFaultMask       __ASM("faultmask");
253
+  __regFaultMask = (faultMask & (uint32_t)1);
254
+}
255
+
256
+#endif /* (__CORTEX_M >= 0x03) */
257
+
258
+
259
+#if       (__CORTEX_M == 0x04)
260
+
261
+/** \brief  Get FPSCR
262
+
263
+    This function returns the current value of the Floating Point Status/Control register.
264
+
265
+    \return               Floating Point Status/Control register value
266
+ */
267
+static __INLINE uint32_t __get_FPSCR(void)
268
+{
269
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
270
+  register uint32_t __regfpscr         __ASM("fpscr");
271
+  return(__regfpscr);
272
+#else
273
+   return(0);
274
+#endif
275
+}
276
+
277
+
278
+/** \brief  Set FPSCR
279
+
280
+    This function assigns the given value to the Floating Point Status/Control register.
281
+
282
+    \param [in]    fpscr  Floating Point Status/Control value to set
283
+ */
284
+static __INLINE void __set_FPSCR(uint32_t fpscr)
285
+{
286
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
287
+  register uint32_t __regfpscr         __ASM("fpscr");
288
+  __regfpscr = (fpscr);
289
+#endif
290
+}
291
+
292
+#endif /* (__CORTEX_M == 0x04) */
293
+
294
+
295
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
296
+/* IAR iccarm specific functions */
297
+
298
+#include <cmsis_iar.h>
299
+
300
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
301
+/* GNU gcc specific functions */
302
+
303
+/** \brief  Enable IRQ Interrupts
304
+
305
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
306
+  Can only be executed in Privileged modes.
307
+ */
308
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
309
+{
310
+  __ASM volatile ("cpsie i");
311
+}
312
+
313
+
314
+/** \brief  Disable IRQ Interrupts
315
+
316
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
317
+  Can only be executed in Privileged modes.
318
+ */
319
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
320
+{
321
+  __ASM volatile ("cpsid i");
322
+}
323
+
324
+
325
+/** \brief  Get Control Register
326
+
327
+    This function returns the content of the Control Register.
328
+
329
+    \return               Control Register value
330
+ */
331
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
332
+{
333
+  uint32_t result;
334
+
335
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
336
+  return(result);
337
+}
338
+
339
+
340
+/** \brief  Set Control Register
341
+
342
+    This function writes the given value to the Control Register.
343
+
344
+    \param [in]    control  Control Register value to set
345
+ */
346
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
347
+{
348
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
349
+}
350
+
351
+
352
+/** \brief  Get ISPR Register
353
+
354
+    This function returns the content of the ISPR Register.
355
+
356
+    \return               ISPR Register value
357
+ */
358
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
359
+{
360
+  uint32_t result;
361
+
362
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
363
+  return(result);
364
+}
365
+
366
+
367
+/** \brief  Get APSR Register
368
+
369
+    This function returns the content of the APSR Register.
370
+
371
+    \return               APSR Register value
372
+ */
373
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
374
+{
375
+  uint32_t result;
376
+
377
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
378
+  return(result);
379
+}
380
+
381
+
382
+/** \brief  Get xPSR Register
383
+
384
+    This function returns the content of the xPSR Register.
385
+
386
+    \return               xPSR Register value
387
+ */
388
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
389
+{
390
+  uint32_t result;
391
+
392
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
393
+  return(result);
394
+}
395
+
396
+
397
+/** \brief  Get Process Stack Pointer
398
+
399
+    This function returns the current value of the Process Stack Pointer (PSP).
400
+
401
+    \return               PSP Register value
402
+ */
403
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
404
+{
405
+  register uint32_t result;
406
+
407
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
408
+  return(result);
409
+}
410
+ 
411
+
412
+/** \brief  Set Process Stack Pointer
413
+
414
+    This function assigns the given value to the Process Stack Pointer (PSP).
415
+
416
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
417
+ */
418
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
419
+{
420
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
421
+}
422
+
423
+
424
+/** \brief  Get Main Stack Pointer
425
+
426
+    This function returns the current value of the Main Stack Pointer (MSP).
427
+
428
+    \return               MSP Register value
429
+ */
430
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
431
+{
432
+  register uint32_t result;
433
+
434
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
435
+  return(result);
436
+}
437
+ 
438
+
439
+/** \brief  Set Main Stack Pointer
440
+
441
+    This function assigns the given value to the Main Stack Pointer (MSP).
442
+
443
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
444
+ */
445
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
446
+{
447
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
448
+}
449
+
450
+
451
+/** \brief  Get Priority Mask
452
+
453
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
454
+
455
+    \return               Priority Mask value
456
+ */
457
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
458
+{
459
+  uint32_t result;
460
+
461
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
462
+  return(result);
463
+}
464
+
465
+
466
+/** \brief  Set Priority Mask
467
+
468
+    This function assigns the given value to the Priority Mask Register.
469
+
470
+    \param [in]    priMask  Priority Mask
471
+ */
472
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
473
+{
474
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
475
+}
476
+ 
477
+
478
+#if       (__CORTEX_M >= 0x03)
479
+
480
+/** \brief  Enable FIQ
481
+
482
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
483
+    Can only be executed in Privileged modes.
484
+ */
485
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
486
+{
487
+  __ASM volatile ("cpsie f");
488
+}
489
+
490
+
491
+/** \brief  Disable FIQ
492
+
493
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
494
+    Can only be executed in Privileged modes.
495
+ */
496
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
497
+{
498
+  __ASM volatile ("cpsid f");
499
+}
500
+
501
+
502
+/** \brief  Get Base Priority
503
+
504
+    This function returns the current value of the Base Priority register.
505
+
506
+    \return               Base Priority register value
507
+ */
508
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
509
+{
510
+  uint32_t result;
511
+  
512
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
513
+  return(result);
514
+}
515
+
516
+
517
+/** \brief  Set Base Priority
518
+
519
+    This function assigns the given value to the Base Priority register.
520
+
521
+    \param [in]    basePri  Base Priority value to set
522
+ */
523
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
524
+{
525
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
526
+}
527
+
528
+
529
+/** \brief  Get Fault Mask
530
+
531
+    This function returns the current value of the Fault Mask register.
532
+
533
+    \return               Fault Mask register value
534
+ */
535
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
536
+{
537
+  uint32_t result;
538
+  
539
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
540
+  return(result);
541
+}
542
+
543
+
544
+/** \brief  Set Fault Mask
545
+
546
+    This function assigns the given value to the Fault Mask register.
547
+
548
+    \param [in]    faultMask  Fault Mask value to set
549
+ */
550
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
551
+{
552
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
553
+}
554
+
555
+#endif /* (__CORTEX_M >= 0x03) */
556
+
557
+
558
+#if       (__CORTEX_M == 0x04)
559
+
560
+/** \brief  Get FPSCR
561
+
562
+    This function returns the current value of the Floating Point Status/Control register.
563
+
564
+    \return               Floating Point Status/Control register value
565
+ */
566
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
567
+{
568
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
569
+  uint32_t result;
570
+
571
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
572
+  return(result);
573
+#else
574
+   return(0);
575
+#endif
576
+}
577
+
578
+
579
+/** \brief  Set FPSCR
580
+
581
+    This function assigns the given value to the Floating Point Status/Control register.
582
+
583
+    \param [in]    fpscr  Floating Point Status/Control value to set
584
+ */
585
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
586
+{
587
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
588
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
589
+#endif
590
+}
591
+
592
+#endif /* (__CORTEX_M == 0x04) */
593
+
594
+
595
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
596
+/* TASKING carm specific functions */
597
+
598
+/*
599
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
600
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
601
+ * Including the CMSIS ones.
602
+ */
603
+
604
+#endif
605
+
606
+/*@} end of CMSIS_Core_RegAccFunctions */
607
+
608
+
609
+#endif /* __CORE_CMFUNC_H */

+ 585
- 0
software/robot/Libraries/CMSIS/Include/core_cmInstr.h View File

@@ -0,0 +1,585 @@
1
+/**************************************************************************//**
2
+ * @file     core_cmInstr.h
3
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
4
+ * @version  V2.10
5
+ * @date     19. July 2011
6
+ *
7
+ * @note
8
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
9
+ *
10
+ * @par
11
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
12
+ * processor based microcontrollers.  This file can be freely distributed 
13
+ * within development tools that are supporting such ARM based processors. 
14
+ *
15
+ * @par
16
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21
+ *
22
+ ******************************************************************************/
23
+
24
+#ifndef __CORE_CMINSTR_H
25
+#define __CORE_CMINSTR_H
26
+
27
+
28
+/* ##########################  Core Instruction Access  ######################### */
29
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
30
+  Access to dedicated instructions
31
+  @{
32
+*/
33
+
34
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35
+/* ARM armcc specific functions */
36
+
37
+#if (__ARMCC_VERSION < 400677)
38
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39
+#endif
40
+
41
+
42
+/** \brief  No Operation
43
+
44
+    No Operation does nothing. This instruction can be used for code alignment purposes.
45
+ */
46
+#define __NOP                             __nop
47
+
48
+
49
+/** \brief  Wait For Interrupt
50
+
51
+    Wait For Interrupt is a hint instruction that suspends execution
52
+    until one of a number of events occurs.
53
+ */
54
+#define __WFI                             __wfi
55
+
56
+
57
+/** \brief  Wait For Event
58
+
59
+    Wait For Event is a hint instruction that permits the processor to enter
60
+    a low-power state until one of a number of events occurs.
61
+ */
62
+#define __WFE                             __wfe
63
+
64
+
65
+/** \brief  Send Event
66
+
67
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
68
+ */
69
+#define __SEV                             __sev
70
+
71
+
72
+/** \brief  Instruction Synchronization Barrier
73
+
74
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
75
+    so that all instructions following the ISB are fetched from cache or 
76
+    memory, after the instruction has been completed.
77
+ */
78
+#define __ISB()                           __isb(0xF)
79
+
80
+
81
+/** \brief  Data Synchronization Barrier
82
+
83
+    This function acts as a special kind of Data Memory Barrier. 
84
+    It completes when all explicit memory accesses before this instruction complete.
85
+ */
86
+#define __DSB()                           __dsb(0xF)
87
+
88
+
89
+/** \brief  Data Memory Barrier
90
+
91
+    This function ensures the apparent order of the explicit memory operations before 
92
+    and after the instruction, without ensuring their completion.
93
+ */
94
+#define __DMB()                           __dmb(0xF)
95
+
96
+
97
+/** \brief  Reverse byte order (32 bit)
98
+
99
+    This function reverses the byte order in integer value.
100
+
101
+    \param [in]    value  Value to reverse
102
+    \return               Reversed value
103
+ */
104
+#define __REV                             __rev
105
+
106
+
107
+/** \brief  Reverse byte order (16 bit)
108
+
109
+    This function reverses the byte order in two unsigned short values.
110
+
111
+    \param [in]    value  Value to reverse
112
+    \return               Reversed value
113
+ */
114
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
115
+{
116
+  rev16 r0, r0
117
+  bx lr
118
+}
119
+
120
+
121
+/** \brief  Reverse byte order in signed short value
122
+
123
+    This function reverses the byte order in a signed short value with sign extension to integer.
124
+
125
+    \param [in]    value  Value to reverse
126
+    \return               Reversed value
127
+ */
128
+static __INLINE __ASM int32_t __REVSH(int32_t value)
129
+{
130
+  revsh r0, r0
131
+  bx lr
132
+}
133
+
134
+
135
+#if       (__CORTEX_M >= 0x03)
136
+
137
+/** \brief  Reverse bit order of value
138
+
139
+    This function reverses the bit order of the given value.
140
+
141
+    \param [in]    value  Value to reverse
142
+    \return               Reversed value
143
+ */
144
+#define __RBIT                            __rbit
145
+
146
+
147
+/** \brief  LDR Exclusive (8 bit)
148
+
149
+    This function performs a exclusive LDR command for 8 bit value.
150
+
151
+    \param [in]    ptr  Pointer to data
152
+    \return             value of type uint8_t at (*ptr)
153
+ */
154
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
155
+
156
+
157
+/** \brief  LDR Exclusive (16 bit)
158
+
159
+    This function performs a exclusive LDR command for 16 bit values.
160
+
161
+    \param [in]    ptr  Pointer to data
162
+    \return        value of type uint16_t at (*ptr)
163
+ */
164
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
165
+
166
+
167
+/** \brief  LDR Exclusive (32 bit)
168
+
169
+    This function performs a exclusive LDR command for 32 bit values.
170
+
171
+    \param [in]    ptr  Pointer to data
172
+    \return        value of type uint32_t at (*ptr)
173
+ */
174
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
175
+
176
+
177
+/** \brief  STR Exclusive (8 bit)
178
+
179
+    This function performs a exclusive STR command for 8 bit values.
180
+
181
+    \param [in]  value  Value to store
182
+    \param [in]    ptr  Pointer to location
183
+    \return          0  Function succeeded
184
+    \return          1  Function failed
185
+ */
186
+#define __STREXB(value, ptr)              __strex(value, ptr)
187
+
188
+
189
+/** \brief  STR Exclusive (16 bit)
190
+
191
+    This function performs a exclusive STR command for 16 bit values.
192
+
193
+    \param [in]  value  Value to store
194
+    \param [in]    ptr  Pointer to location
195
+    \return          0  Function succeeded
196
+    \return          1  Function failed
197
+ */
198
+#define __STREXH(value, ptr)              __strex(value, ptr)
199
+
200
+
201
+/** \brief  STR Exclusive (32 bit)
202
+
203
+    This function performs a exclusive STR command for 32 bit values.
204
+
205
+    \param [in]  value  Value to store
206
+    \param [in]    ptr  Pointer to location
207
+    \return          0  Function succeeded
208
+    \return          1  Function failed
209
+ */
210
+#define __STREXW(value, ptr)              __strex(value, ptr)
211
+
212
+
213
+/** \brief  Remove the exclusive lock
214
+
215
+    This function removes the exclusive lock which is created by LDREX.
216
+
217
+ */
218
+#define __CLREX                           __clrex
219
+
220
+
221
+/** \brief  Signed Saturate
222
+
223
+    This function saturates a signed value.
224
+
225
+    \param [in]  value  Value to be saturated
226
+    \param [in]    sat  Bit position to saturate to (1..32)
227
+    \return             Saturated value
228
+ */
229
+#define __SSAT                            __ssat
230
+
231
+
232
+/** \brief  Unsigned Saturate
233
+
234
+    This function saturates an unsigned value.
235
+
236
+    \param [in]  value  Value to be saturated
237
+    \param [in]    sat  Bit position to saturate to (0..31)
238
+    \return             Saturated value
239
+ */
240
+#define __USAT                            __usat
241
+
242
+
243
+/** \brief  Count leading zeros
244
+
245
+    This function counts the number of leading zeros of a data value.
246
+
247
+    \param [in]  value  Value to count the leading zeros
248
+    \return             number of leading zeros in value
249
+ */
250
+#define __CLZ                             __clz 
251
+
252
+#endif /* (__CORTEX_M >= 0x03) */
253
+
254
+
255
+
256
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
257
+/* IAR iccarm specific functions */
258
+
259
+#include <cmsis_iar.h>
260
+
261
+
262
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
263
+/* GNU gcc specific functions */
264
+
265
+/** \brief  No Operation
266
+
267
+    No Operation does nothing. This instruction can be used for code alignment purposes.
268
+ */
269
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
270
+{
271
+  __ASM volatile ("nop");
272
+}
273
+
274
+
275
+/** \brief  Wait For Interrupt
276
+
277
+    Wait For Interrupt is a hint instruction that suspends execution
278
+    until one of a number of events occurs.
279
+ */
280
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
281
+{
282
+  __ASM volatile ("wfi");
283
+}
284
+
285
+
286
+/** \brief  Wait For Event
287
+
288
+    Wait For Event is a hint instruction that permits the processor to enter
289
+    a low-power state until one of a number of events occurs.
290
+ */
291
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
292
+{
293
+  __ASM volatile ("wfe");
294
+}
295
+
296
+
297
+/** \brief  Send Event
298
+
299
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
300
+ */
301
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
302
+{
303
+  __ASM volatile ("sev");
304
+}
305
+
306
+
307
+/** \brief  Instruction Synchronization Barrier
308
+
309
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
310
+    so that all instructions following the ISB are fetched from cache or 
311
+    memory, after the instruction has been completed.
312
+ */
313
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
314
+{
315
+  __ASM volatile ("isb");
316
+}
317
+
318
+
319
+/** \brief  Data Synchronization Barrier
320
+
321
+    This function acts as a special kind of Data Memory Barrier. 
322
+    It completes when all explicit memory accesses before this instruction complete.
323
+ */
324
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
325
+{
326
+  __ASM volatile ("dsb");
327
+}
328
+
329
+
330
+/** \brief  Data Memory Barrier
331
+
332
+    This function ensures the apparent order of the explicit memory operations before 
333
+    and after the instruction, without ensuring their completion.
334
+ */
335
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
336
+{
337
+  __ASM volatile ("dmb");
338
+}
339
+
340
+
341
+/** \brief  Reverse byte order (32 bit)
342
+
343
+    This function reverses the byte order in integer value.
344
+
345
+    \param [in]    value  Value to reverse
346
+    \return               Reversed value
347
+ */
348
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
349
+{
350
+  uint32_t result;
351
+  
352
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
353
+  return(result);
354
+}
355
+
356
+
357
+/** \brief  Reverse byte order (16 bit)
358
+
359
+    This function reverses the byte order in two unsigned short values.
360
+
361
+    \param [in]    value  Value to reverse
362
+    \return               Reversed value
363
+ */
364
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
365
+{
366
+  uint32_t result;
367
+  
368
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
369
+  return(result);
370
+}
371
+
372
+
373
+/** \brief  Reverse byte order in signed short value
374
+
375
+    This function reverses the byte order in a signed short value with sign extension to integer.
376
+
377
+    \param [in]    value  Value to reverse
378
+    \return               Reversed value
379
+ */
380
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
381
+{
382
+  uint32_t result;
383
+  
384
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
385
+  return(result);
386
+}
387
+
388
+
389
+#if       (__CORTEX_M >= 0x03)
390
+
391
+/** \brief  Reverse bit order of value
392
+
393
+    This function reverses the bit order of the given value.
394
+
395
+    \param [in]    value  Value to reverse
396
+    \return               Reversed value
397
+ */
398
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
399
+{
400
+  uint32_t result;
401
+  
402
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
403
+   return(result);
404
+}
405
+
406
+
407
+/** \brief  LDR Exclusive (8 bit)
408
+
409
+    This function performs a exclusive LDR command for 8 bit value.
410
+
411
+    \param [in]    ptr  Pointer to data
412
+    \return             value of type uint8_t at (*ptr)
413
+ */
414
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
415
+{
416
+    uint8_t result;
417
+  
418
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
419
+   return(result);
420
+}
421
+
422
+
423
+/** \brief  LDR Exclusive (16 bit)
424
+
425
+    This function performs a exclusive LDR command for 16 bit values.
426
+
427
+    \param [in]    ptr  Pointer to data
428
+    \return        value of type uint16_t at (*ptr)
429
+ */
430
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
431
+{
432
+    uint16_t result;
433
+  
434
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
435
+   return(result);
436
+}
437
+
438
+
439
+/** \brief  LDR Exclusive (32 bit)
440
+
441
+    This function performs a exclusive LDR command for 32 bit values.
442
+
443
+    \param [in]    ptr  Pointer to data
444
+    \return        value of type uint32_t at (*ptr)
445
+ */
446
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
447
+{
448
+    uint32_t result;
449
+  
450
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
451
+   return(result);
452
+}
453
+
454
+
455
+/** \brief  STR Exclusive (8 bit)
456
+
457
+    This function performs a exclusive STR command for 8 bit values.
458
+
459
+    \param [in]  value  Value to store
460
+    \param [in]    ptr  Pointer to location
461
+    \return          0  Function succeeded
462
+    \return          1  Function failed
463
+ */
464
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
465
+{
466
+   uint32_t result;
467
+  
468
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
469
+   return(result);
470
+}
471
+
472
+
473
+/** \brief  STR Exclusive (16 bit)
474
+
475
+    This function performs a exclusive STR command for 16 bit values.
476
+
477
+    \param [in]  value  Value to store
478
+    \param [in]    ptr  Pointer to location
479
+    \return          0  Function succeeded
480
+    \return          1  Function failed
481
+ */
482
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
483
+{
484
+   uint32_t result;
485
+  
486
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
487
+   return(result);
488
+}
489
+
490
+
491
+/** \brief  STR Exclusive (32 bit)
492
+
493
+    This function performs a exclusive STR command for 32 bit values.
494
+
495
+    \param [in]  value  Value to store
496
+    \param [in]    ptr  Pointer to location
497
+    \return          0  Function succeeded
498
+    \return          1  Function failed
499
+ */
500
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
501
+{
502
+   uint32_t result;
503
+  
504
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
505
+   return(result);
506
+}
507
+
508
+
509
+/** \brief  Remove the exclusive lock
510
+
511
+    This function removes the exclusive lock which is created by LDREX.
512
+
513
+ */
514
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
515
+{
516
+  __ASM volatile ("clrex");
517
+}
518
+
519
+
520
+/** \brief  Signed Saturate
521
+
522
+    This function saturates a signed value.
523
+
524
+    \param [in]  value  Value to be saturated
525
+    \param [in]    sat  Bit position to saturate to (1..32)
526
+    \return             Saturated value
527
+ */
528
+#define __SSAT(ARG1,ARG2) \
529
+({                          \
530
+  uint32_t __RES, __ARG1 = (ARG1); \
531
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
532
+  __RES; \
533
+ })
534
+
535
+
536
+/** \brief  Unsigned Saturate
537
+
538
+    This function saturates an unsigned value.
539
+
540
+    \param [in]  value  Value to be saturated
541
+    \param [in]    sat  Bit position to saturate to (0..31)
542
+    \return             Saturated value
543
+ */
544
+#define __USAT(ARG1,ARG2) \
545
+({                          \
546
+  uint32_t __RES, __ARG1 = (ARG1); \
547
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
548
+  __RES; \
549
+ })
550
+
551
+
552
+/** \brief  Count leading zeros
553
+
554
+    This function counts the number of leading zeros of a data value.
555
+
556
+    \param [in]  value  Value to count the leading zeros
557
+    \return             number of leading zeros in value
558
+ */
559
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
560
+{
561
+  uint8_t result;
562
+  
563
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
564
+  return(result);
565
+}
566
+
567
+#endif /* (__CORTEX_M >= 0x03) */
568
+
569
+
570
+
571
+
572
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
573
+/* TASKING carm specific functions */
574
+
575
+/*
576
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
577
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
578
+ * Including the CMSIS ones.
579
+ */
580
+
581
+#endif
582
+
583
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
584
+
585
+#endif /* __CORE_CMINSTR_H */

+ 34
- 0
software/robot/Libraries/CMSIS/README.txt View File

@@ -0,0 +1,34 @@
1
+* -------------------------------------------------------------------
2
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
3
+* 
4
+* Date:        25 July 2011  
5
+* Revision:    V2.10 
6
+*  
7
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
8
+* Title:       Release Note for CMSIS
9
+*
10
+* -------------------------------------------------------------------
11
+
12
+
13
+NOTE - Open the index.html file to access CMSIS documentation
14
+
15
+
16
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
17
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
18
+and reduces time-to-market for new embedded applications.
19
+
20
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
21
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
22
+
23
+
24
+You will find the following sub-directories:
25
+
26
+Documentation           - Contains CMSIS documentation.
27
+ 
28
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
29
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
30
+
31
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
32
+
33
+Lib                     - CMSIS DSP Binaries 
34
+---

+ 115
- 0
software/robot/Libraries/CMSIS/index.htm View File

@@ -0,0 +1,115 @@
1
+<html>
2
+
3
+<head>
4
+<title>CMSIS Release Notes</title>
5
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
6
+<meta name="GENERATOR" content="Microsoft FrontPage 12.0">
7
+<meta name="ProgId" content="FrontPage.Editor.Document">
8
+<style>
9
+<!--
10
+/*-----------------------------------------------------------
11
+Keil Software CHM Style Sheet
12
+-----------------------------------------------------------*/
13
+body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: 
14
+               Verdana, Arial, 'Sans Serif' }
15
+a:link       { color: #0000FF; text-decoration: underline }
16
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17
+a:active     { color: #FF0000; text-decoration: underline }
18
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19
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20
+               text-align: Center; margin-right: 3 }
21
+h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; 
22
+               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; 
23
+               padding: 6 }
24
+h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: 
25
+               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
26
+pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; 
27
+               margin-left: 24; margin-right: 24 }
28
+ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
29
+ol           { margin-top: 6pt; margin-bottom: 0 }
30
+li           { clear: both; margin-bottom: 6pt }
31
+table        { font-size: 100%; border-width: 0; padding: 0 }
32
+th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: 
33
+               bottom; padding-right: 6pt }
34
+tr           { text-align: left; vertical-align: top }
35
+td           { text-align: left; vertical-align: top; padding-right: 6pt }
36
+.ToolT       { font-size: 8pt; color: #808080 }
37
+.TinyT       { font-size: 8pt; text-align: Center }
38
+code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; 
39
+               line-height: 120%; font-style: normal }
40
+/*-----------------------------------------------------------
41
+Notes
42
+-----------------------------------------------------------*/
43
+p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
44
+/*-----------------------------------------------------------
45
+Expanding/Contracting Divisions
46
+-----------------------------------------------------------*/
47
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48
+img.expand   { border-style: none; border-width: medium }
49
+div.expand   { display: none; margin-left: 9pt; margin-top: 0 }
50
+/*-----------------------------------------------------------
51
+Where List Tags
52
+-----------------------------------------------------------*/
53
+p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
54
+table.wh     { width: 100% }
55
+td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 
56
+               6pt }
57
+td.whDesc    { padding-bottom: 6pt }
58
+/*-----------------------------------------------------------
59
+Keil Table Tags
60
+-----------------------------------------------------------*/
61
+table.kt     { border: 1pt solid #000000 }
62
+th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; 
63
+               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
64
+tr.kt        {  }
65
+td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; 
66
+               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; 
67
+               padding-bottom: 2pt }
68
+/*-----------------------------------------------------------
69
+-----------------------------------------------------------*/
70
+-->
71
+
72
+</style>
73
+</head>
74
+
75
+<body>
76
+
77
+<h1>CMSIS Release Notes</h1>
78
+<p align="center">Release Notes for CMSIS V2.00</p>
79
+<p align="center">November 2010</p>
80
+
81
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
82
+                 Copyright © ARM Ltd.<br>All rights reserved.
83
+<p align="center"><img src="Documentation/CMSIS_Logo_Final.jpg" height="78" width="197">
84
+</p>
85
+
86
+<hr>
87
+
88
+<h2>Contents</h2>
89
+
90
+<ul>
91
+  <li class="LI2"><a href="Documentation/CMSIS_History.htm">CMSIS Version History</a>
92
+    lists the changes between the different CMSIS versions.
93
+  </li>
94
+  <li class="LI2"><a href="Documentation/CMSIS_Core.htm">CMSIS Core Support</a>
95
+    contains a general description for CMSIS.
96
+  </li>
97
+  <li class="LI2"><a href="Documentation/DSP_Lib/html/index.html">CMSIS DSP Software Library</a>
98
+    describes the CMSIS DSP software library.
99
+  </li>
100
+  <li class="LI2"><a href="Documentation/CMSIS_System_View_Description.htm">CMSIS System View Description</a>
101
+    describes the CMSIS System View Description.
102
+  </li>
103
+  <li class="LI2"><a href="Documentation/CMSIS_CM4_SIMD.htm">CMSIS Support for Cortex-M4 SIMD Instructions</a>
104
+    lists the Cortex-M4 instructions supported by CMSIS.
105
+  </li>
106
+  <li class="LI2"><a href="Documentation/CMSIS_DebugSupport.htm">CMSIS Debug Support</a>
107
+    describes the available CMSIS Debug functions and the used methods.
108
+  </li>
109
+  <li class="LI2"><a href="CMSIS END USER LICENCE AGREEMENT.pdf">License</a></li>
110
+</ul>
111
+
112
+
113
+</body>
114
+
115
+</html>

+ 340
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+
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+
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+
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+
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+
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+
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+
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+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
12
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+<tbody>
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+          <tr>
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+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>
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+          </tr>
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+<tr style="">
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+<td style="padding: 1.5pt;">
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+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
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+Notes for STM32F10x Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
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+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+</td>
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+</tr>
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+</tbody>
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+</table>
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+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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+<tbody>
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+<tr>
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+<td style="padding: 0cm;" valign="top">
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+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
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+<ol style="margin-top: 0cm;" start="1" type="1">
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+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
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+Drivers update History</a><o:p></o:p></span></li>
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+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
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+</ol>
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+<span style="font-family: &quot;Times New Roman&quot;;">
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+</span>
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+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
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+Peripherals Library Drivers&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.1 / 05-March-2012<o:p></o:p></span></h3>
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+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+Changes<o:p></o:p></span></u></b></p>
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+
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+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.0 / 27-January-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+Changes<o:p></o:p></span></u></b></p>
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+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the&nbsp;new license agreement</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SDIO_SetPowerState()</span> function: fix POWER register configuration, only one access (for read or write) is allowed</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_usart.h/.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update procedure to check on&nbsp;overrun error interrupt pending bit, defines for the following flag are added:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_RX:</span> this flag is set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and&nbsp;RXNEIE bit is set</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_ER:</span> </span><span style="font-size: 10pt; font-family: Verdana;">this flag is&nbsp;set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and EIE bit is set</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove <span style="font-style: italic;">IS_USART_PERIPH_FLAG</span> macro (not used)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RTC_GetCounter()</span> function to fix issue when reading the RTC counter registers (CNTL &amp; CNTH registers) and the counter rolls over</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Flash keys moved from&nbsp;to stm32f10x.h file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_UpdateRequestConfig():&nbsp;</span>correct function header's comment&nbsp;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_exti.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">EXTI_InitTypeDef</span> structure : for &#8220;EXTI_Trigger&#8220; member, change &#8220;@ref EXTIMode_TypeDef&#8221;&nbsp; by&nbsp; &#8220;@ref EXTITrigger_TypeDef&#8221;&nbsp;</span></li></ul></ul>
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+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
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+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+Changes<o:p></o:p></span></u></b></p>
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+
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+            <ul style="margin-top: 0cm;" type="square">
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+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c files:</span></li>
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+              <ul>
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+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 5 new functions</span></li>
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+                <ul>
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+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">3
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+new functions controlling the counter errors: CAN_GetLastErrorCode(),
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+CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().</span></li>
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+                </ul>
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+                <ul>
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+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to select the CAN operating mode: CAN_OperatingModeRequest().</span></li>
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+                </ul>
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+                <ul>
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+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to support CAN TT mode: CAN_TTComModeCmd().</span><span style="font-size: 10pt; font-family: Verdana;"><br>
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+  </span></li>
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+                </ul>
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+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN_TransmitStatus() function updated to support all CAN transmit intermediate states<br>
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+                  </span></li>
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+              </ul>
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+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c files:</span></li>
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+              <ul>
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+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 1 new function:</span></li>
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+                <ul>
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+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_NACKPositionConfig():
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+This function configures the same bit (POS) as I2C_PECPositionConfig()
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+but is intended to be used in I2C mode while I2C_PECPositionConfig() is
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+intended to used in SMBUS mode.</span></li>
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+                </ul>
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+              </ul>
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+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c files:</span></li>
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+              <ul>
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+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the <span style="font-style: italic;">TIM_DMABurstLength_xBytes</span> definitions to <span style="font-style: italic;">TIM_DMABurstLength_xTansfers</span><br>
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+                  </span></li>
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+              </ul>
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+
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+
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+            </ul>
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+
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+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
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+- 10/15/2010</span></h3>
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+
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+            <ol style="margin-top: 0in;" start="1" type="1">
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+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
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+            </ol>
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+
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+            <ul style="margin-top: 0in;" type="disc">
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>
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+            </ul>
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+
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+            <ol style="margin-top: 0in;" start="2" type="1">
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+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
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+            </ol>
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+
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+            
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+            <ul style="margin-top: 0in;" type="disc">
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+
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>
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+</span></span></li>
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+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>
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+                  </span></span></li>
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+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()
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+and CAN_ClearFlag() functions: updated to support new flags (were not
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+supported in previous version). These flags are:&nbsp; CAN_FLAG_RQCP0,
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+CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,
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+CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,&nbsp;&nbsp; CAN_FLAG_FOV0,
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+CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>
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+                  </span></span></li>
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+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()
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+function: add a check of the interrupt enable bit before getting the
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+status of corresponding interrupt pending bit. <br>
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+                  </span></span></li>
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+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>
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+                  </span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>
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+              <ul>
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+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>
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+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>
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+                  </span></span></li>
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+              </ul>
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+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>
216
+              <ul>
217
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>
218
+              </ul>
219
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>
220
+              <ul>
221
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>
222
+              </ul>
223
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>
224
+              <ul>
225
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>
226
+              </ul>
227
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>
228
+              <ul>
229
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>
230
+              </ul>
231
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>
232
+              <ul>
233
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>
234
+              </ul>
235
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>
236
+              <ul>
237
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>
238
+              </ul>
239
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>
240
+<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>
241
+            
242
+            </ul>
243
+
244
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
245
+- 04/16/2010</span></h3>
246
+
247
+<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
248
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>
249
+<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
250
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:
251
+updated to support Bank2 of XL-density devices (up to 1MByte of Flash
252
+memory). For more details, refer to the description provided within
253
+stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>
254
+function: updated to check whether the last event contains the
255
+I2C_EVENT&nbsp; (instead of check whether the last event is equal to
256
+I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add
257
+detailed description of I2C events and how to manage them using the
258
+functions provided by this driver. For more information, refer to
259
+stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h:&nbsp;</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br>&nbsp;
260
+#define
261
+SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
262
+&nbsp; ((uint32_t)0x00000000)<br>&nbsp; #define
263
+SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
264
+((uint32_t)0x00000001)<br>by<br>&nbsp; #define
265
+SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
266
+&nbsp; ((uint32_t)0x00000001)<br>&nbsp; #define
267
+SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
268
+((uint32_t)0x00000000)</span></li></ul></ul>
269
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
270
+- 03/01/2010</span></h3>
271
+<ol style="margin-top: 0in;" start="1" type="1">
272
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
273
+</ol>
274
+<ul style="margin-top: 0in;" type="disc">
275
+
276
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
277
+for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
278
+Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
279
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost
280
+peripherals drivers were updated to support Value
281
+line devices features</span></li>
282
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
283
+
284
+</ul>
285
+<ol style="margin-top: 0in;" start="2" type="1">
286
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
287
+</ol>
288
+<ul style="margin-top: 0in;" type="disc">
289
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
290
+firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>
291
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>
292
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>
293
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>
294
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART
295
+driver: add support for Oversampling by 8 mode and onebit method. 2
296
+functions has been added: USART_OverSampling8Cmd() and
297
+USART_OneBitMethodCmd().<br>
298
+                </span></li>
299
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC
300
+driver: add new functions handling the DAC under run feature:
301
+DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()
302
+and DAC_ClearITPendingBit().</span></li>
303
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>
304
+                </span></li>
305
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH
306
+driver: the FLASH_EraseOptionBytes() function updated. This is now just
307
+erasing the option bytes without modifying the RDP status either
308
+enabled or disabled.</span></li>
309
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR
310
+driver: the PWR_EnterSTOPMode() function updated. When woken up from
311
+STOP mode, this function resets again the SLEEPDEEP bit in the
312
+Cortex-M3 System Control register to allow Sleep mode entering.</span></li>
313
+              
314
+
315
+</ul>
316
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
317
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
318
+required by applicable law or agreed to in writing, software
319
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
320
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
321
+the License for the specific language governing permissions and
322
+limitations under the License.</span><p class="MsoNormal"><span style="color: black;"><o:p></o:p></span><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="color: black;"><o:p></o:p></span></p>
323
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
324
+<hr align="center" size="2" width="100%"></span></div>
325
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
326
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
327
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
328
+</td>
329
+</tr>
330
+</tbody>
331
+</table>
332
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
333
+</td>
334
+</tr>
335
+</tbody>
336
+</table>
337
+</div>
338
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
339
+</div>
340
+</body></html>

+ 226
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h View File

@@ -0,0 +1,226 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    misc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the miscellaneous
8
+  *          firmware library functions (add-on to CMSIS functions).
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __MISC_H
31
+#define __MISC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup MISC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup MISC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  NVIC Init Structure definition  
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
59
+                                                   This parameter can be a value of @ref IRQn_Type 
60
+                                                   (For the complete STM32 Devices IRQ Channels list, please
61
+                                                    refer to stm32f10x.h file) */
62
+
63
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
64
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
65
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
66
+
67
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
68
+                                                   in NVIC_IRQChannel. This parameter can be a value
69
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
70
+
71
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
72
+                                                   will be enabled or disabled. 
73
+                                                   This parameter can be set either to ENABLE or DISABLE */   
74
+} NVIC_InitTypeDef;
75
+ 
76
+/**
77
+  * @}
78
+  */
79
+
80
+/** @defgroup NVIC_Priority_Table 
81
+  * @{
82
+  */
83
+
84
+/**
85
+@code  
86
+ The table below gives the allowed values of the pre-emption priority and subpriority according
87
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
88
+  ============================================================================================================================
89
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
90
+  ============================================================================================================================
91
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
92
+                         |                                   |                             |   4 bits for subpriority
93
+  ----------------------------------------------------------------------------------------------------------------------------
94
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
95
+                         |                                   |                             |   3 bits for subpriority
96
+  ----------------------------------------------------------------------------------------------------------------------------    
97
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
98
+                         |                                   |                             |   2 bits for subpriority
99
+  ----------------------------------------------------------------------------------------------------------------------------    
100
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
101
+                         |                                   |                             |   1 bits for subpriority
102
+  ----------------------------------------------------------------------------------------------------------------------------    
103
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
104
+                         |                                   |                             |   0 bits for subpriority                       
105
+  ============================================================================================================================
106
+@endcode
107
+*/
108
+
109
+/**
110
+  * @}
111
+  */
112
+
113
+/** @defgroup MISC_Exported_Constants
114
+  * @{
115
+  */
116
+
117
+/** @defgroup Vector_Table_Base 
118
+  * @{
119
+  */
120
+
121
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
122
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
123
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
124
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
125
+/**
126
+  * @}
127
+  */
128
+
129
+/** @defgroup System_Low_Power 
130
+  * @{
131
+  */
132
+
133
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
134
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
135
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
136
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
137
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
138
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
139
+/**
140
+  * @}
141
+  */
142
+
143
+/** @defgroup Preemption_Priority_Group 
144
+  * @{
145
+  */
146
+
147
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
148
+                                                            4 bits for subpriority */
149
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
150
+                                                            3 bits for subpriority */
151
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
152
+                                                            2 bits for subpriority */
153
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
154
+                                                            1 bits for subpriority */
155
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
156
+                                                            0 bits for subpriority */
157
+
158
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
159
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
160
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
161
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
162
+                                       ((GROUP) == NVIC_PriorityGroup_4))
163
+
164
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
165
+
166
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
167
+
168
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
169
+
170
+/**
171
+  * @}
172
+  */
173
+
174
+/** @defgroup SysTick_clock_source 
175
+  * @{
176
+  */
177
+
178
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
179
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
180
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
181
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
182
+/**
183
+  * @}
184
+  */
185
+
186
+/**
187
+  * @}
188
+  */
189
+
190
+/** @defgroup MISC_Exported_Macros
191
+  * @{
192
+  */
193
+
194
+/**
195
+  * @}
196
+  */
197
+
198
+/** @defgroup MISC_Exported_Functions
199
+  * @{
200
+  */
201
+
202
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
203
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
204
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
205
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
206
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
207
+
208
+#ifdef __cplusplus
209
+}
210
+#endif
211
+
212
+#endif /* __MISC_H */
213
+
214
+/**
215
+  * @}
216
+  */
217
+
218
+/**
219
+  * @}
220
+  */
221
+
222
+/**
223
+  * @}
224
+  */
225
+
226
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 489
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h View File

@@ -0,0 +1,489 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_adc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_ADC_H
31
+#define __STM32F10x_ADC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup ADC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup ADC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  ADC Init structure definition  
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
59
+                                               dual mode. 
60
+                                               This parameter can be a value of @ref ADC_mode */
61
+
62
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
63
+                                               Scan (multichannels) or Single (one channel) mode.
64
+                                               This parameter can be set to ENABLE or DISABLE */
65
+
66
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
67
+                                               Continuous or Single mode.
68
+                                               This parameter can be set to ENABLE or DISABLE. */
69
+
70
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
71
+                                               to digital conversion of regular channels. This parameter
72
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
73
+
74
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
75
+                                               This parameter can be a value of @ref ADC_data_align */
76
+
77
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
78
+                                               using the sequencer for regular channel group.
79
+                                               This parameter must range from 1 to 16. */
80
+}ADC_InitTypeDef;
81
+/**
82
+  * @}
83
+  */
84
+
85
+/** @defgroup ADC_Exported_Constants
86
+  * @{
87
+  */
88
+
89
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
90
+                                   ((PERIPH) == ADC2) || \
91
+                                   ((PERIPH) == ADC3))
92
+
93
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
94
+                                   ((PERIPH) == ADC3))
95
+
96
+/** @defgroup ADC_mode 
97
+  * @{
98
+  */
99
+
100
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
101
+#define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
102
+#define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
103
+#define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
104
+#define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
105
+#define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
106
+#define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
107
+#define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
108
+#define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
109
+#define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
110
+
111
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
112
+                           ((MODE) == ADC_Mode_RegInjecSimult) || \
113
+                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
114
+                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
115
+                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
116
+                           ((MODE) == ADC_Mode_InjecSimult) || \
117
+                           ((MODE) == ADC_Mode_RegSimult) || \
118
+                           ((MODE) == ADC_Mode_FastInterl) || \
119
+                           ((MODE) == ADC_Mode_SlowInterl) || \
120
+                           ((MODE) == ADC_Mode_AlterTrig))
121
+/**
122
+  * @}
123
+  */
124
+
125
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
126
+  * @{
127
+  */
128
+
129
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
130
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
131
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
132
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
133
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
134
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
135
+
136
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
137
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
138
+
139
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
140
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
141
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
142
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
143
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
144
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
145
+
146
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
147
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
148
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
149
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
150
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
151
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
152
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
153
+                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
154
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
155
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
156
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
157
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
158
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
159
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
160
+/**
161
+  * @}
162
+  */
163
+
164
+/** @defgroup ADC_data_align 
165
+  * @{
166
+  */
167
+
168
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
169
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
170
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
171
+                                  ((ALIGN) == ADC_DataAlign_Left))
172
+/**
173
+  * @}
174
+  */
175
+
176
+/** @defgroup ADC_channels 
177
+  * @{
178
+  */
179
+
180
+#define ADC_Channel_0                               ((uint8_t)0x00)
181
+#define ADC_Channel_1                               ((uint8_t)0x01)
182
+#define ADC_Channel_2                               ((uint8_t)0x02)
183
+#define ADC_Channel_3                               ((uint8_t)0x03)
184
+#define ADC_Channel_4                               ((uint8_t)0x04)
185
+#define ADC_Channel_5                               ((uint8_t)0x05)
186
+#define ADC_Channel_6                               ((uint8_t)0x06)
187
+#define ADC_Channel_7                               ((uint8_t)0x07)
188
+#define ADC_Channel_8                               ((uint8_t)0x08)
189
+#define ADC_Channel_9                               ((uint8_t)0x09)
190
+#define ADC_Channel_10                              ((uint8_t)0x0A)
191
+#define ADC_Channel_11                              ((uint8_t)0x0B)
192
+#define ADC_Channel_12                              ((uint8_t)0x0C)
193
+#define ADC_Channel_13                              ((uint8_t)0x0D)
194
+#define ADC_Channel_14                              ((uint8_t)0x0E)
195
+#define ADC_Channel_15                              ((uint8_t)0x0F)
196
+#define ADC_Channel_16                              ((uint8_t)0x10)
197
+#define ADC_Channel_17                              ((uint8_t)0x11)
198
+
199
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
200
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
201
+
202
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
203
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
204
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
205
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
206
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
207
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
208
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
209
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
210
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
211
+/**
212
+  * @}
213
+  */
214
+
215
+/** @defgroup ADC_sampling_time 
216
+  * @{
217
+  */
218
+
219
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
220
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
221
+#define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
222
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
223
+#define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
224
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
225
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
226
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
227
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
228
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
229
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
230
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
231
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
232
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
233
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
234
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
235
+/**
236
+  * @}
237
+  */
238
+
239
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
240
+  * @{
241
+  */
242
+
243
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
244
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
245
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
246
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
247
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
248
+
249
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
250
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
251
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
252
+
253
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
254
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
255
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
256
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
257
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
258
+
259
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
260
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
261
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
262
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
263
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
264
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
265
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
266
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
267
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
268
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
269
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
270
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
271
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
272
+/**
273
+  * @}
274
+  */
275
+
276
+/** @defgroup ADC_injected_channel_selection 
277
+  * @{
278
+  */
279
+
280
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
281
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
282
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
283
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
284
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
285
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
286
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
287
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
288
+/**
289
+  * @}
290
+  */
291
+
292
+/** @defgroup ADC_analog_watchdog_selection 
293
+  * @{
294
+  */
295
+
296
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
297
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
298
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
299
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
300
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
301
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
302
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
303
+
304
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
305
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
306
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
307
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
308
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
309
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
310
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
311
+/**
312
+  * @}
313
+  */
314
+
315
+/** @defgroup ADC_interrupts_definition 
316
+  * @{
317
+  */
318
+
319
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
320
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
321
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
322
+
323
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
324
+
325
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
326
+                           ((IT) == ADC_IT_JEOC))
327
+/**
328
+  * @}
329
+  */
330
+
331
+/** @defgroup ADC_flags_definition 
332
+  * @{
333
+  */
334
+
335
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
336
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
337
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
338
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
339
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
340
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
341
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
342
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
343
+                               ((FLAG) == ADC_FLAG_STRT))
344
+/**
345
+  * @}
346
+  */
347
+
348
+/** @defgroup ADC_thresholds 
349
+  * @{
350
+  */
351
+
352
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
353
+
354
+/**
355
+  * @}
356
+  */
357
+
358
+/** @defgroup ADC_injected_offset 
359
+  * @{
360
+  */
361
+
362
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
363
+
364
+/**
365
+  * @}
366
+  */
367
+
368
+/** @defgroup ADC_injected_length 
369
+  * @{
370
+  */
371
+
372
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
373
+
374
+/**
375
+  * @}
376
+  */
377
+
378
+/** @defgroup ADC_injected_rank 
379
+  * @{
380
+  */
381
+
382
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
383
+
384
+/**
385
+  * @}
386
+  */ 
387
+
388
+
389
+/** @defgroup ADC_regular_length 
390
+  * @{
391
+  */
392
+
393
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
394
+/**
395
+  * @}
396
+  */
397
+
398
+/** @defgroup ADC_regular_rank 
399
+  * @{
400
+  */
401
+
402
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
403
+
404
+/**
405
+  * @}
406
+  */
407
+
408
+/** @defgroup ADC_regular_discontinuous_mode_number 
409
+  * @{
410
+  */
411
+
412
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
413
+
414
+/**
415
+  * @}
416
+  */
417
+
418
+/**
419
+  * @}
420
+  */
421
+
422
+/** @defgroup ADC_Exported_Macros
423
+  * @{
424
+  */
425
+
426
+/**
427
+  * @}
428
+  */
429
+
430
+/** @defgroup ADC_Exported_Functions
431
+  * @{
432
+  */
433
+
434
+void ADC_DeInit(ADC_TypeDef* ADCx);
435
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
436
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
437
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
438
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
439
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
440
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
441
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
442
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
443
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
444
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
445
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
446
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
447
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
448
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
449
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
450
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
451
+uint32_t ADC_GetDualModeConversionValue(void);
452
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
453
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
454
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
455
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
456
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
457
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
458
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
459
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
460
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
461
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
462
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
463
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
464
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
465
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
466
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
467
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
468
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
469
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
470
+
471
+#ifdef __cplusplus
472
+}
473
+#endif
474
+
475
+#endif /*__STM32F10x_ADC_H */
476
+
477
+/**
478
+  * @}
479
+  */
480
+
481
+/**
482
+  * @}
483
+  */
484
+
485
+/**
486
+  * @}
487
+  */
488
+
489
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 201
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h View File

@@ -0,0 +1,201 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_bkp.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_BKP_H
31
+#define __STM32F10x_BKP_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup BKP
45
+  * @{
46
+  */
47
+
48
+/** @defgroup BKP_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/** @defgroup BKP_Exported_Constants
57
+  * @{
58
+  */
59
+
60
+/** @defgroup Tamper_Pin_active_level 
61
+  * @{
62
+  */
63
+
64
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
65
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
66
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
67
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
68
+/**
69
+  * @}
70
+  */
71
+
72
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
73
+  * @{
74
+  */
75
+
76
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
77
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
78
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
79
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
80
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
81
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
82
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
83
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
84
+/**
85
+  * @}
86
+  */
87
+
88
+/** @defgroup Data_Backup_Register 
89
+  * @{
90
+  */
91
+
92
+#define BKP_DR1                           ((uint16_t)0x0004)
93
+#define BKP_DR2                           ((uint16_t)0x0008)
94
+#define BKP_DR3                           ((uint16_t)0x000C)
95
+#define BKP_DR4                           ((uint16_t)0x0010)
96
+#define BKP_DR5                           ((uint16_t)0x0014)
97
+#define BKP_DR6                           ((uint16_t)0x0018)
98
+#define BKP_DR7                           ((uint16_t)0x001C)
99
+#define BKP_DR8                           ((uint16_t)0x0020)
100
+#define BKP_DR9                           ((uint16_t)0x0024)
101
+#define BKP_DR10                          ((uint16_t)0x0028)
102
+#define BKP_DR11                          ((uint16_t)0x0040)
103
+#define BKP_DR12                          ((uint16_t)0x0044)
104
+#define BKP_DR13                          ((uint16_t)0x0048)
105
+#define BKP_DR14                          ((uint16_t)0x004C)
106
+#define BKP_DR15                          ((uint16_t)0x0050)
107
+#define BKP_DR16                          ((uint16_t)0x0054)
108
+#define BKP_DR17                          ((uint16_t)0x0058)
109
+#define BKP_DR18                          ((uint16_t)0x005C)
110
+#define BKP_DR19                          ((uint16_t)0x0060)
111
+#define BKP_DR20                          ((uint16_t)0x0064)
112
+#define BKP_DR21                          ((uint16_t)0x0068)
113
+#define BKP_DR22                          ((uint16_t)0x006C)
114
+#define BKP_DR23                          ((uint16_t)0x0070)
115
+#define BKP_DR24                          ((uint16_t)0x0074)
116
+#define BKP_DR25                          ((uint16_t)0x0078)
117
+#define BKP_DR26                          ((uint16_t)0x007C)
118
+#define BKP_DR27                          ((uint16_t)0x0080)
119
+#define BKP_DR28                          ((uint16_t)0x0084)
120
+#define BKP_DR29                          ((uint16_t)0x0088)
121
+#define BKP_DR30                          ((uint16_t)0x008C)
122
+#define BKP_DR31                          ((uint16_t)0x0090)
123
+#define BKP_DR32                          ((uint16_t)0x0094)
124
+#define BKP_DR33                          ((uint16_t)0x0098)
125
+#define BKP_DR34                          ((uint16_t)0x009C)
126
+#define BKP_DR35                          ((uint16_t)0x00A0)
127
+#define BKP_DR36                          ((uint16_t)0x00A4)
128
+#define BKP_DR37                          ((uint16_t)0x00A8)
129
+#define BKP_DR38                          ((uint16_t)0x00AC)
130
+#define BKP_DR39                          ((uint16_t)0x00B0)
131
+#define BKP_DR40                          ((uint16_t)0x00B4)
132
+#define BKP_DR41                          ((uint16_t)0x00B8)
133
+#define BKP_DR42                          ((uint16_t)0x00BC)
134
+
135
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
136
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
137
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
138
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
139
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
140
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
141
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
142
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
143
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
144
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
145
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
146
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
147
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
148
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
149
+
150
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
151
+/**
152
+  * @}
153
+  */
154
+
155
+/**
156
+  * @}
157
+  */
158
+
159
+/** @defgroup BKP_Exported_Macros
160
+  * @{
161
+  */
162
+
163
+/**
164
+  * @}
165
+  */
166
+
167
+/** @defgroup BKP_Exported_Functions
168
+  * @{
169
+  */
170
+
171
+void BKP_DeInit(void);
172
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
173
+void BKP_TamperPinCmd(FunctionalState NewState);
174
+void BKP_ITConfig(FunctionalState NewState);
175
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
176
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
177
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
178
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
179
+FlagStatus BKP_GetFlagStatus(void);
180
+void BKP_ClearFlag(void);
181
+ITStatus BKP_GetITStatus(void);
182
+void BKP_ClearITPendingBit(void);
183
+
184
+#ifdef __cplusplus
185
+}
186
+#endif
187
+
188
+#endif /* __STM32F10x_BKP_H */
189
+/**
190
+  * @}
191
+  */
192
+
193
+/**
194
+  * @}
195
+  */
196
+
197
+/**
198
+  * @}
199
+  */
200
+
201
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 703
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h View File

@@ -0,0 +1,703 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_can.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_CAN_H
31
+#define __STM32F10x_CAN_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup CAN
45
+  * @{
46
+  */
47
+
48
+/** @defgroup CAN_Exported_Types
49
+  * @{
50
+  */
51
+
52
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
53
+                                   ((PERIPH) == CAN2))
54
+
55
+/** 
56
+  * @brief  CAN init structure definition
57
+  */
58
+
59
+typedef struct
60
+{
61
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
62
+                                 It ranges from 1 to 1024. */
63
+  
64
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
65
+                                 This parameter can be a value of 
66
+                                @ref CAN_operating_mode */
67
+
68
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
69
+                                 the CAN hardware is allowed to lengthen or 
70
+                                 shorten a bit to perform resynchronization.
71
+                                 This parameter can be a value of 
72
+                                 @ref CAN_synchronisation_jump_width */
73
+
74
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
75
+                                 Segment 1. This parameter can be a value of 
76
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
77
+
78
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit 
79
+                                 Segment 2.
80
+                                 This parameter can be a value of 
81
+                                 @ref CAN_time_quantum_in_bit_segment_2 */
82
+  
83
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered 
84
+                                 communication mode. This parameter can be set 
85
+                                 either to ENABLE or DISABLE. */
86
+  
87
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off 
88
+                                  management. This parameter can be set either 
89
+                                  to ENABLE or DISABLE. */
90
+
91
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
92
+                                  This parameter can be set either to ENABLE or 
93
+                                  DISABLE. */
94
+
95
+  FunctionalState CAN_NART;  /*!< Enable or disable the no-automatic 
96
+                                  retransmission mode. This parameter can be 
97
+                                  set either to ENABLE or DISABLE. */
98
+
99
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
100
+                                  This parameter can be set either to ENABLE 
101
+                                  or DISABLE. */
102
+
103
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
104
+                                  This parameter can be set either to ENABLE 
105
+                                  or DISABLE. */
106
+} CAN_InitTypeDef;
107
+
108
+/** 
109
+  * @brief  CAN filter init structure definition
110
+  */
111
+
112
+typedef struct
113
+{
114
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
115
+                                              configuration, first one for a 16-bit configuration).
116
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
117
+
118
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
119
+                                              configuration, second one for a 16-bit configuration).
120
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
121
+
122
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
123
+                                              according to the mode (MSBs for a 32-bit configuration,
124
+                                              first one for a 16-bit configuration).
125
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
126
+
127
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
128
+                                              according to the mode (LSBs for a 32-bit configuration,
129
+                                              second one for a 16-bit configuration).
130
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
131
+
132
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
133
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
134
+  
135
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
136
+
137
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
138
+                                              This parameter can be a value of @ref CAN_filter_mode */
139
+
140
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
141
+                                              This parameter can be a value of @ref CAN_filter_scale */
142
+
143
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
144
+                                              This parameter can be set either to ENABLE or DISABLE. */
145
+} CAN_FilterInitTypeDef;
146
+
147
+/** 
148
+  * @brief  CAN Tx message structure definition  
149
+  */
150
+
151
+typedef struct
152
+{
153
+  uint32_t StdId;  /*!< Specifies the standard identifier.
154
+                        This parameter can be a value between 0 to 0x7FF. */
155
+
156
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
157
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
158
+
159
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
160
+                        will be transmitted. This parameter can be a value 
161
+                        of @ref CAN_identifier_type */
162
+
163
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
164
+                        be transmitted. This parameter can be a value of 
165
+                        @ref CAN_remote_transmission_request */
166
+
167
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
168
+                        transmitted. This parameter can be a value between 
169
+                        0 to 8 */
170
+
171
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
172
+                        to 0xFF. */
173
+} CanTxMsg;
174
+
175
+/** 
176
+  * @brief  CAN Rx message structure definition  
177
+  */
178
+
179
+typedef struct
180
+{
181
+  uint32_t StdId;  /*!< Specifies the standard identifier.
182
+                        This parameter can be a value between 0 to 0x7FF. */
183
+
184
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
185
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
186
+
187
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
188
+                        will be received. This parameter can be a value of 
189
+                        @ref CAN_identifier_type */
190
+
191
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
192
+                        This parameter can be a value of 
193
+                        @ref CAN_remote_transmission_request */
194
+
195
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
196
+                        This parameter can be a value between 0 to 8 */
197
+
198
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
199
+                        0xFF. */
200
+
201
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
202
+                        the mailbox passes through. This parameter can be a 
203
+                        value between 0 to 0xFF */
204
+} CanRxMsg;
205
+
206
+/**
207
+  * @}
208
+  */
209
+
210
+/** @defgroup CAN_Exported_Constants
211
+  * @{
212
+  */
213
+
214
+/** @defgroup CAN_sleep_constants 
215
+  * @{
216
+  */
217
+
218
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
219
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
220
+
221
+/**
222
+  * @}
223
+  */
224
+
225
+/** @defgroup CAN_Mode 
226
+  * @{
227
+  */
228
+
229
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
230
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
231
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
232
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
233
+
234
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
235
+                           ((MODE) == CAN_Mode_LoopBack)|| \
236
+                           ((MODE) == CAN_Mode_Silent) || \
237
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
238
+/**
239
+  * @}
240
+  */
241
+
242
+
243
+/**
244
+  * @defgroup CAN_Operating_Mode 
245
+  * @{
246
+  */  
247
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
248
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
249
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
250
+
251
+
252
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
253
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
254
+																		((MODE) == CAN_OperatingMode_Sleep))
255
+/**
256
+  * @}
257
+  */
258
+  
259
+/**
260
+  * @defgroup CAN_Mode_Status
261
+  * @{
262
+  */  
263
+
264
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
265
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
266
+
267
+
268
+/**
269
+  * @}
270
+  */
271
+
272
+/** @defgroup CAN_synchronisation_jump_width 
273
+  * @{
274
+  */
275
+
276
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
277
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
278
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
279
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
280
+
281
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
282
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
283
+/**
284
+  * @}
285
+  */
286
+
287
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
288
+  * @{
289
+  */
290
+
291
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
292
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
293
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
294
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
295
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
296
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
297
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
298
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
299
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
300
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
301
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
302
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
303
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
304
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
305
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
306
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
307
+
308
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
309
+/**
310
+  * @}
311
+  */
312
+
313
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
314
+  * @{
315
+  */
316
+
317
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
318
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
319
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
320
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
321
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
322
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
323
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
324
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
325
+
326
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
327
+
328
+/**
329
+  * @}
330
+  */
331
+
332
+/** @defgroup CAN_clock_prescaler 
333
+  * @{
334
+  */
335
+
336
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
337
+
338
+/**
339
+  * @}
340
+  */
341
+
342
+/** @defgroup CAN_filter_number 
343
+  * @{
344
+  */
345
+#ifndef STM32F10X_CL
346
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
347
+#else
348
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
349
+#endif /* STM32F10X_CL */ 
350
+/**
351
+  * @}
352
+  */
353
+
354
+/** @defgroup CAN_filter_mode 
355
+  * @{
356
+  */
357
+
358
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
359
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
360
+
361
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
362
+                                  ((MODE) == CAN_FilterMode_IdList))
363
+/**
364
+  * @}
365
+  */
366
+
367
+/** @defgroup CAN_filter_scale 
368
+  * @{
369
+  */
370
+
371
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
372
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
373
+
374
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
375
+                                    ((SCALE) == CAN_FilterScale_32bit))
376
+
377
+/**
378
+  * @}
379
+  */
380
+
381
+/** @defgroup CAN_filter_FIFO
382
+  * @{
383
+  */
384
+
385
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
386
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
387
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
388
+                                  ((FIFO) == CAN_FilterFIFO1))
389
+/**
390
+  * @}
391
+  */
392
+
393
+/** @defgroup Start_bank_filter_for_slave_CAN 
394
+  * @{
395
+  */
396
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
397
+/**
398
+  * @}
399
+  */
400
+
401
+/** @defgroup CAN_Tx 
402
+  * @{
403
+  */
404
+
405
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
406
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
407
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
408
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
409
+
410
+/**
411
+  * @}
412
+  */
413
+
414
+/** @defgroup CAN_identifier_type 
415
+  * @{
416
+  */
417
+
418
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
419
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
420
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
421
+                               ((IDTYPE) == CAN_Id_Extended))
422
+/**
423
+  * @}
424
+  */
425
+
426
+/** @defgroup CAN_remote_transmission_request 
427
+  * @{
428
+  */
429
+
430
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
431
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
432
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
433
+
434
+/**
435
+  * @}
436
+  */
437
+
438
+/** @defgroup CAN_transmit_constants 
439
+  * @{
440
+  */
441
+
442
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
443
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
444
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
445
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
446
+
447
+/**
448
+  * @}
449
+  */
450
+
451
+/** @defgroup CAN_receive_FIFO_number_constants 
452
+  * @{
453
+  */
454
+
455
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
456
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
457
+
458
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
459
+
460
+/**
461
+  * @}
462
+  */
463
+
464
+/** @defgroup CAN_sleep_constants 
465
+  * @{
466
+  */
467
+
468
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
469
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
470
+
471
+/**
472
+  * @}
473
+  */
474
+
475
+/** @defgroup CAN_wake_up_constants 
476
+  * @{
477
+  */
478
+
479
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
480
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
481
+
482
+/**
483
+  * @}
484
+  */
485
+
486
+/**
487
+  * @defgroup   CAN_Error_Code_constants
488
+  * @{
489
+  */  
490
+                                                                
491
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
492
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
493
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
494
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
495
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
496
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
497
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
498
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
499
+
500
+
501
+/**
502
+  * @}
503
+  */
504
+
505
+/** @defgroup CAN_flags 
506
+  * @{
507
+  */
508
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
509
+   and CAN_ClearFlag() functions. */
510
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
511
+
512
+/* Transmit Flags */
513
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
514
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
515
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
516
+
517
+/* Receive Flags */
518
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
519
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
520
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
521
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
522
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
523
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
524
+
525
+/* Operating Mode Flags */
526
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
527
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
528
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
529
+         In this case the SLAK bit can be polled.*/
530
+
531
+/* Error Flags */
532
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
533
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
534
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
535
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
536
+
537
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
538
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
539
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
540
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
541
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
542
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
543
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
544
+                               ((FLAG) == CAN_FLAG_SLAK ))
545
+
546
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
547
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
548
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
549
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
550
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
551
+/**
552
+  * @}
553
+  */
554
+
555
+  
556
+/** @defgroup CAN_interrupts 
557
+  * @{
558
+  */
559
+
560
+
561
+  
562
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
563
+
564
+/* Receive Interrupts */
565
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
566
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
567
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
568
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
569
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
570
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
571
+
572
+/* Operating Mode Interrupts */
573
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
574
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
575
+
576
+/* Error Interrupts */
577
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
578
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
579
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
580
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
581
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
582
+
583
+/* Flags named as Interrupts : kept only for FW compatibility */
584
+#define CAN_IT_RQCP0   CAN_IT_TME
585
+#define CAN_IT_RQCP1   CAN_IT_TME
586
+#define CAN_IT_RQCP2   CAN_IT_TME
587
+
588
+
589
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
590
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
591
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
592
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
593
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
594
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
595
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
596
+
597
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
598
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
599
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
600
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
601
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
602
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
603
+
604
+/**
605
+  * @}
606
+  */
607
+
608
+/** @defgroup CAN_Legacy 
609
+  * @{
610
+  */
611
+#define CANINITFAILED               CAN_InitStatus_Failed
612
+#define CANINITOK                   CAN_InitStatus_Success
613
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
614
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
615
+#define CAN_ID_STD                  CAN_Id_Standard           
616
+#define CAN_ID_EXT                  CAN_Id_Extended
617
+#define CAN_RTR_DATA                CAN_RTR_Data         
618
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
619
+#define CANTXFAILE                  CAN_TxStatus_Failed
620
+#define CANTXOK                     CAN_TxStatus_Ok
621
+#define CANTXPENDING                CAN_TxStatus_Pending
622
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
623
+#define CANSLEEPFAILED              CAN_Sleep_Failed
624
+#define CANSLEEPOK                  CAN_Sleep_Ok
625
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
626
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
627
+
628
+/**
629
+  * @}
630
+  */
631
+
632
+/**
633
+  * @}
634
+  */
635
+
636
+/** @defgroup CAN_Exported_Macros
637
+  * @{
638
+  */
639
+
640
+/**
641
+  * @}
642
+  */
643
+
644
+/** @defgroup CAN_Exported_Functions
645
+  * @{
646
+  */
647
+/*  Function used to set the CAN configuration to the default reset state *****/ 
648
+void CAN_DeInit(CAN_TypeDef* CANx);
649
+
650
+/* Initialization and Configuration functions *********************************/ 
651
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
652
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
653
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
654
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
655
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
656
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
657
+
658
+/* Transmit functions *********************************************************/
659
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
660
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
661
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
662
+
663
+/* Receive functions **********************************************************/
664
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
665
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
666
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
667
+
668
+
669
+/* Operation modes functions **************************************************/
670
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
671
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
672
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
673
+
674
+/* Error management functions *************************************************/
675
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
676
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
677
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
678
+
679
+/* Interrupts and flags management functions **********************************/
680
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
681
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
682
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
683
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
684
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
685
+
686
+#ifdef __cplusplus
687
+}
688
+#endif
689
+
690
+#endif /* __STM32F10x_CAN_H */
691
+/**
692
+  * @}
693
+  */
694
+
695
+/**
696
+  * @}
697
+  */
698
+
699
+/**
700
+  * @}
701
+  */
702
+
703
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 216
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h View File

@@ -0,0 +1,216 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_cec.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_CEC_H
31
+#define __STM32F10x_CEC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup CEC
45
+  * @{
46
+  */
47
+  
48
+
49
+/** @defgroup CEC_Exported_Types
50
+  * @{
51
+  */
52
+   
53
+/** 
54
+  * @brief  CEC Init structure definition  
55
+  */ 
56
+typedef struct
57
+{
58
+  uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
59
+                               This parameter can be a value of @ref CEC_BitTiming_Mode */
60
+  uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
61
+                               This parameter can be a value of @ref CEC_BitPeriod_Mode */
62
+}CEC_InitTypeDef;
63
+
64
+/**
65
+  * @}
66
+  */
67
+
68
+/** @defgroup CEC_Exported_Constants
69
+  * @{
70
+  */ 
71
+  
72
+/** @defgroup CEC_BitTiming_Mode 
73
+  * @{
74
+  */ 
75
+#define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
76
+#define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
77
+
78
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
79
+                                            ((MODE) == CEC_BitTimingErrFreeMode))
80
+/**
81
+  * @}
82
+  */
83
+
84
+/** @defgroup CEC_BitPeriod_Mode 
85
+  * @{
86
+  */ 
87
+#define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
88
+#define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
89
+
90
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
91
+                                            ((MODE) == CEC_BitPeriodFlexibleMode))
92
+/**
93
+  * @}
94
+  */ 
95
+
96
+
97
+/** @defgroup CEC_interrupts_definition 
98
+  * @{
99
+  */ 
100
+#define CEC_IT_TERR                              CEC_CSR_TERR
101
+#define CEC_IT_TBTRF                             CEC_CSR_TBTRF
102
+#define CEC_IT_RERR                              CEC_CSR_RERR
103
+#define CEC_IT_RBTF                              CEC_CSR_RBTF
104
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
105
+                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
106
+/**
107
+  * @}
108
+  */ 
109
+
110
+
111
+/** @defgroup CEC_Own_Address 
112
+  * @{
113
+  */ 
114
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
115
+/**
116
+  * @}
117
+  */ 
118
+
119
+/** @defgroup CEC_Prescaler 
120
+  * @{
121
+  */ 
122
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
123
+
124
+/**
125
+  * @}
126
+  */
127
+
128
+/** @defgroup CEC_flags_definition 
129
+  * @{
130
+  */
131
+   
132
+/** 
133
+  * @brief  ESR register flags  
134
+  */ 
135
+#define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
136
+#define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
137
+#define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
138
+#define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
139
+#define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
140
+#define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
141
+#define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
142
+
143
+/** 
144
+  * @brief  CSR register flags  
145
+  */ 
146
+#define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
147
+#define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
148
+#define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
149
+#define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
150
+#define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
151
+#define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
152
+#define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
153
+
154
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
155
+                               
156
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
157
+                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
158
+                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
159
+                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
160
+                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
161
+                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
162
+                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
163
+
164
+/**
165
+  * @}
166
+  */ 
167
+
168
+/**
169
+  * @}
170
+  */ 
171
+
172
+/** @defgroup CEC_Exported_Macros
173
+  * @{
174
+  */
175
+ 
176
+/**
177
+  * @}
178
+  */
179
+
180
+/** @defgroup CEC_Exported_Functions
181
+  * @{
182
+  */ 
183
+void CEC_DeInit(void);
184
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
185
+void CEC_Cmd(FunctionalState NewState);
186
+void CEC_ITConfig(FunctionalState NewState);
187
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
188
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
189
+void CEC_SendDataByte(uint8_t Data);
190
+uint8_t CEC_ReceiveDataByte(void);
191
+void CEC_StartOfMessage(void);
192
+void CEC_EndOfMessageCmd(FunctionalState NewState);
193
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
194
+void CEC_ClearFlag(uint32_t CEC_FLAG);
195
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
196
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
197
+
198
+#ifdef __cplusplus
199
+}
200
+#endif
201
+
202
+#endif /* __STM32F10x_CEC_H */
203
+
204
+/**
205
+  * @}
206
+  */ 
207
+
208
+/**
209
+  * @}
210
+  */ 
211
+
212
+/**
213
+  * @}
214
+  */ 
215
+
216
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 100
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h View File

@@ -0,0 +1,100 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_crc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_CRC_H
31
+#define __STM32F10x_CRC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup CRC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup CRC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/** @defgroup CRC_Exported_Constants
57
+  * @{
58
+  */
59
+
60
+/**
61
+  * @}
62
+  */
63
+
64
+/** @defgroup CRC_Exported_Macros
65
+  * @{
66
+  */
67
+
68
+/**
69
+  * @}
70
+  */
71
+
72
+/** @defgroup CRC_Exported_Functions
73
+  * @{
74
+  */
75
+
76
+void CRC_ResetDR(void);
77
+uint32_t CRC_CalcCRC(uint32_t Data);
78
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
79
+uint32_t CRC_GetCRC(void);
80
+void CRC_SetIDRegister(uint8_t IDValue);
81
+uint8_t CRC_GetIDRegister(void);
82
+
83
+#ifdef __cplusplus
84
+}
85
+#endif
86
+
87
+#endif /* __STM32F10x_CRC_H */
88
+/**
89
+  * @}
90
+  */
91
+
92
+/**
93
+  * @}
94
+  */
95
+
96
+/**
97
+  * @}
98
+  */
99
+
100
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 323
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h View File

@@ -0,0 +1,323 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dac.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_DAC_H
31
+#define __STM32F10x_DAC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup DAC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup DAC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  DAC Init structure definition
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
59
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
60
+
61
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
62
+                                                  are generated, or whether no wave is generated.
63
+                                                  This parameter can be a value of @ref DAC_wave_generation */
64
+
65
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
66
+                                                  the maximum amplitude triangle generation for the DAC channel. 
67
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
68
+
69
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
70
+                                                  This parameter can be a value of @ref DAC_output_buffer */
71
+}DAC_InitTypeDef;
72
+
73
+/**
74
+  * @}
75
+  */
76
+
77
+/** @defgroup DAC_Exported_Constants
78
+  * @{
79
+  */
80
+
81
+/** @defgroup DAC_trigger_selection 
82
+  * @{
83
+  */
84
+
85
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
86
+                                                                       has been loaded, and not by external trigger */
87
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
88
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
89
+                                                                       only in High-density devices*/
90
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
91
+                                                                       only in Connectivity line, Medium-density and Low-density Value Line devices */
92
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
93
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
94
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 
95
+                                                                       only in Medium-density and Low-density Value Line devices*/
96
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
97
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
98
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
99
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
100
+
101
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
102
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
103
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
104
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
105
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
106
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
107
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
108
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
109
+                                 ((TRIGGER) == DAC_Trigger_Software))
110
+
111
+/**
112
+  * @}
113
+  */
114
+
115
+/** @defgroup DAC_wave_generation 
116
+  * @{
117
+  */
118
+
119
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
120
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
121
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
122
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
123
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
124
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
125
+/**
126
+  * @}
127
+  */
128
+
129
+/** @defgroup DAC_lfsrunmask_triangleamplitude
130
+  * @{
131
+  */
132
+
133
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
134
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
135
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
136
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
137
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
138
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
139
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
140
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
141
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
142
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
143
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
144
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
145
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
146
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
147
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
148
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
149
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
150
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
151
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
152
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
153
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
154
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
155
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
156
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
157
+
158
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
159
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
160
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
161
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
162
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
163
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
164
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
165
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
166
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
167
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
168
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
169
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
170
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
171
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
172
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
173
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
174
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
175
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
176
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
177
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
178
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
179
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
180
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
181
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
182
+/**
183
+  * @}
184
+  */
185
+
186
+/** @defgroup DAC_output_buffer 
187
+  * @{
188
+  */
189
+
190
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
191
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
192
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
193
+                                           ((STATE) == DAC_OutputBuffer_Disable))
194
+/**
195
+  * @}
196
+  */
197
+
198
+/** @defgroup DAC_Channel_selection 
199
+  * @{
200
+  */
201
+
202
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
203
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
204
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
205
+                                 ((CHANNEL) == DAC_Channel_2))
206
+/**
207
+  * @}
208
+  */
209
+
210
+/** @defgroup DAC_data_alignment 
211
+  * @{
212
+  */
213
+
214
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
215
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
216
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
217
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
218
+                             ((ALIGN) == DAC_Align_12b_L) || \
219
+                             ((ALIGN) == DAC_Align_8b_R))
220
+/**
221
+  * @}
222
+  */
223
+
224
+/** @defgroup DAC_wave_generation 
225
+  * @{
226
+  */
227
+
228
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
229
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
230
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
231
+                           ((WAVE) == DAC_Wave_Triangle))
232
+/**
233
+  * @}
234
+  */
235
+
236
+/** @defgroup DAC_data 
237
+  * @{
238
+  */
239
+
240
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
241
+/**
242
+  * @}
243
+  */
244
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)  || defined (STM32F10X_HD_VL)
245
+/** @defgroup DAC_interrupts_definition 
246
+  * @{
247
+  */ 
248
+  
249
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
250
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
251
+
252
+/**
253
+  * @}
254
+  */ 
255
+
256
+/** @defgroup DAC_flags_definition 
257
+  * @{
258
+  */ 
259
+  
260
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
261
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
262
+
263
+/**
264
+  * @}
265
+  */
266
+#endif
267
+
268
+/**
269
+  * @}
270
+  */
271
+
272
+/** @defgroup DAC_Exported_Macros
273
+  * @{
274
+  */
275
+
276
+/**
277
+  * @}
278
+  */
279
+
280
+/** @defgroup DAC_Exported_Functions
281
+  * @{
282
+  */
283
+
284
+void DAC_DeInit(void);
285
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
286
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
287
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
288
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
289
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
290
+#endif
291
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
292
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
293
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
294
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
295
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
296
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
297
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
298
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
299
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 
300
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
301
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
302
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
303
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
304
+#endif
305
+
306
+#ifdef __cplusplus
307
+}
308
+#endif
309
+
310
+#endif /*__STM32F10x_DAC_H */
311
+/**
312
+  * @}
313
+  */
314
+
315
+/**
316
+  * @}
317
+  */
318
+
319
+/**
320
+  * @}
321
+  */
322
+
323
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 125
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h View File

@@ -0,0 +1,125 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dbgmcu.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the DBGMCU 
8
+  *          firmware library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_DBGMCU_H
31
+#define __STM32F10x_DBGMCU_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup DBGMCU
45
+  * @{
46
+  */
47
+
48
+/** @defgroup DBGMCU_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/** @defgroup DBGMCU_Exported_Constants
57
+  * @{
58
+  */
59
+
60
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
61
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
62
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
63
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
64
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
65
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
66
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
67
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
68
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
69
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
70
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
71
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
72
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
73
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
74
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
75
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
76
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
77
+#define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
78
+#define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
79
+#define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
80
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
81
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
82
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
83
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
84
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
85
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
86
+                                              
87
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
88
+/**
89
+  * @}
90
+  */ 
91
+
92
+/** @defgroup DBGMCU_Exported_Macros
93
+  * @{
94
+  */
95
+
96
+/**
97
+  * @}
98
+  */
99
+
100
+/** @defgroup DBGMCU_Exported_Functions
101
+  * @{
102
+  */
103
+
104
+uint32_t DBGMCU_GetREVID(void);
105
+uint32_t DBGMCU_GetDEVID(void);
106
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
107
+
108
+#ifdef __cplusplus
109
+}
110
+#endif
111
+
112
+#endif /* __STM32F10x_DBGMCU_H */
113
+/**
114
+  * @}
115
+  */
116
+
117
+/**
118
+  * @}
119
+  */
120
+
121
+/**
122
+  * @}
123
+  */
124
+
125
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 445
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h View File

@@ -0,0 +1,445 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dma.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_DMA_H
31
+#define __STM32F10x_DMA_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup DMA
45
+  * @{
46
+  */
47
+
48
+/** @defgroup DMA_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  DMA Init structure definition
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
59
+
60
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
61
+
62
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
63
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
64
+
65
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
66
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
67
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
68
+
69
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
70
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
71
+
72
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
73
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
74
+
75
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
76
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
77
+
78
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
79
+                                        This parameter can be a value of @ref DMA_memory_data_size */
80
+
81
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
82
+                                        This parameter can be a value of @ref DMA_circular_normal_mode.
83
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
84
+                                              data transfer is configured on the selected Channel */
85
+
86
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
87
+                                        This parameter can be a value of @ref DMA_priority_level */
88
+
89
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
90
+                                        This parameter can be a value of @ref DMA_memory_to_memory */
91
+}DMA_InitTypeDef;
92
+
93
+/**
94
+  * @}
95
+  */
96
+
97
+/** @defgroup DMA_Exported_Constants
98
+  * @{
99
+  */
100
+
101
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
102
+                                   ((PERIPH) == DMA1_Channel2) || \
103
+                                   ((PERIPH) == DMA1_Channel3) || \
104
+                                   ((PERIPH) == DMA1_Channel4) || \
105
+                                   ((PERIPH) == DMA1_Channel5) || \
106
+                                   ((PERIPH) == DMA1_Channel6) || \
107
+                                   ((PERIPH) == DMA1_Channel7) || \
108
+                                   ((PERIPH) == DMA2_Channel1) || \
109
+                                   ((PERIPH) == DMA2_Channel2) || \
110
+                                   ((PERIPH) == DMA2_Channel3) || \
111
+                                   ((PERIPH) == DMA2_Channel4) || \
112
+                                   ((PERIPH) == DMA2_Channel5))
113
+
114
+/** @defgroup DMA_data_transfer_direction 
115
+  * @{
116
+  */
117
+
118
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
119
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
120
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
121
+                         ((DIR) == DMA_DIR_PeripheralSRC))
122
+/**
123
+  * @}
124
+  */
125
+
126
+/** @defgroup DMA_peripheral_incremented_mode 
127
+  * @{
128
+  */
129
+
130
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
131
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
132
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
133
+                                            ((STATE) == DMA_PeripheralInc_Disable))
134
+/**
135
+  * @}
136
+  */
137
+
138
+/** @defgroup DMA_memory_incremented_mode 
139
+  * @{
140
+  */
141
+
142
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
143
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
144
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
145
+                                        ((STATE) == DMA_MemoryInc_Disable))
146
+/**
147
+  * @}
148
+  */
149
+
150
+/** @defgroup DMA_peripheral_data_size 
151
+  * @{
152
+  */
153
+
154
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
155
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
156
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
157
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
158
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
159
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
160
+/**
161
+  * @}
162
+  */
163
+
164
+/** @defgroup DMA_memory_data_size 
165
+  * @{
166
+  */
167
+
168
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
169
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
170
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
171
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
172
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
173
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
174
+/**
175
+  * @}
176
+  */
177
+
178
+/** @defgroup DMA_circular_normal_mode 
179
+  * @{
180
+  */
181
+
182
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
183
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
184
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
185
+/**
186
+  * @}
187
+  */
188
+
189
+/** @defgroup DMA_priority_level 
190
+  * @{
191
+  */
192
+
193
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
194
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
195
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
196
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
197
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
198
+                                   ((PRIORITY) == DMA_Priority_High) || \
199
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
200
+                                   ((PRIORITY) == DMA_Priority_Low))
201
+/**
202
+  * @}
203
+  */
204
+
205
+/** @defgroup DMA_memory_to_memory 
206
+  * @{
207
+  */
208
+
209
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
210
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
211
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
212
+
213
+/**
214
+  * @}
215
+  */
216
+
217
+/** @defgroup DMA_interrupts_definition 
218
+  * @{
219
+  */
220
+
221
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
222
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
223
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
224
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
225
+
226
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
227
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
228
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
229
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
230
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
231
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
232
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
233
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
234
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
235
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
236
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
237
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
238
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
239
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
240
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
241
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
242
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
243
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
244
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
245
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
246
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
247
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
248
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
249
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
250
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
251
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
252
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
253
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
254
+
255
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
256
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
257
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
258
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
259
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
260
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
261
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
262
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
263
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
264
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
265
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
266
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
267
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
268
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
269
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
270
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
271
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
272
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
273
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
274
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
275
+
276
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
277
+
278
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
279
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
280
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
281
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
282
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
283
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
284
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
285
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
286
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
287
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
288
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
289
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
290
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
291
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
292
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
293
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
294
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
295
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
296
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
297
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
298
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
299
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
300
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
301
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
302
+
303
+/**
304
+  * @}
305
+  */
306
+
307
+/** @defgroup DMA_flags_definition 
308
+  * @{
309
+  */
310
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
311
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
312
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
313
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
314
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
315
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
316
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
317
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
318
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
319
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
320
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
321
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
322
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
323
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
324
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
325
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
326
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
327
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
328
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
329
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
330
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
331
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
332
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
333
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
334
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
335
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
336
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
337
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
338
+
339
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
340
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
341
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
342
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
343
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
344
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
345
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
346
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
347
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
348
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
349
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
350
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
351
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
352
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
353
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
354
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
355
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
356
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
357
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
358
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
359
+
360
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
361
+
362
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
363
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
364
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
365
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
366
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
367
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
368
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
369
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
370
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
371
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
372
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
373
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
374
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
375
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
376
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
377
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
378
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
379
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
380
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
381
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
382
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
383
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
384
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
385
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
386
+/**
387
+  * @}
388
+  */
389
+
390
+/** @defgroup DMA_Buffer_Size 
391
+  * @{
392
+  */
393
+
394
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
395
+
396
+/**
397
+  * @}
398
+  */
399
+
400
+/**
401
+  * @}
402
+  */
403
+
404
+/** @defgroup DMA_Exported_Macros
405
+  * @{
406
+  */
407
+
408
+/**
409
+  * @}
410
+  */
411
+
412
+/** @defgroup DMA_Exported_Functions
413
+  * @{
414
+  */
415
+
416
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
417
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
418
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
419
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
420
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
421
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
422
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
423
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
424
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
425
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
426
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
427
+
428
+#ifdef __cplusplus
429
+}
430
+#endif
431
+
432
+#endif /*__STM32F10x_DMA_H */
433
+/**
434
+  * @}
435
+  */
436
+
437
+/**
438
+  * @}
439
+  */
440
+
441
+/**
442
+  * @}
443
+  */
444
+
445
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 190
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h View File

@@ -0,0 +1,190 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_exti.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_EXTI_H
31
+#define __STM32F10x_EXTI_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup EXTI
45
+  * @{
46
+  */
47
+
48
+/** @defgroup EXTI_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  EXTI mode enumeration  
54
+  */
55
+
56
+typedef enum
57
+{
58
+  EXTI_Mode_Interrupt = 0x00,
59
+  EXTI_Mode_Event = 0x04
60
+}EXTIMode_TypeDef;
61
+
62
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
63
+
64
+/** 
65
+  * @brief  EXTI Trigger enumeration  
66
+  */
67
+
68
+typedef enum
69
+{
70
+  EXTI_Trigger_Rising = 0x08,
71
+  EXTI_Trigger_Falling = 0x0C,  
72
+  EXTI_Trigger_Rising_Falling = 0x10
73
+}EXTITrigger_TypeDef;
74
+
75
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
76
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
77
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
78
+/** 
79
+  * @brief  EXTI Init Structure definition  
80
+  */
81
+
82
+typedef struct
83
+{
84
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
85
+                                         This parameter can be any combination of @ref EXTI_Lines */
86
+   
87
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
88
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
89
+
90
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
91
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
92
+
93
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
94
+                                         This parameter can be set either to ENABLE or DISABLE */ 
95
+}EXTI_InitTypeDef;
96
+
97
+/**
98
+  * @}
99
+  */
100
+
101
+/** @defgroup EXTI_Exported_Constants
102
+  * @{
103
+  */
104
+
105
+/** @defgroup EXTI_Lines 
106
+  * @{
107
+  */
108
+
109
+#define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
110
+#define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
111
+#define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
112
+#define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
113
+#define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
114
+#define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
115
+#define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
116
+#define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
117
+#define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
118
+#define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
119
+#define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
120
+#define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
121
+#define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
122
+#define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
123
+#define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
124
+#define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
125
+#define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
126
+#define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
127
+#define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
128
+                                                   Wakeup from suspend event */                                    
129
+#define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
130
+                                          
131
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
132
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
133
+                            ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
134
+                            ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
135
+                            ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
136
+                            ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
137
+                            ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
138
+                            ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
139
+                            ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
140
+                            ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
141
+                            ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
142
+
143
+                    
144
+/**
145
+  * @}
146
+  */
147
+
148
+/**
149
+  * @}
150
+  */
151
+
152
+/** @defgroup EXTI_Exported_Macros
153
+  * @{
154
+  */
155
+
156
+/**
157
+  * @}
158
+  */
159
+
160
+/** @defgroup EXTI_Exported_Functions
161
+  * @{
162
+  */
163
+
164
+void EXTI_DeInit(void);
165
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
166
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
167
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
168
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
169
+void EXTI_ClearFlag(uint32_t EXTI_Line);
170
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
171
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
172
+
173
+#ifdef __cplusplus
174
+}
175
+#endif
176
+
177
+#endif /* __STM32F10x_EXTI_H */
178
+/**
179
+  * @}
180
+  */
181
+
182
+/**
183
+  * @}
184
+  */
185
+
186
+/**
187
+  * @}
188
+  */
189
+
190
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 432
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h View File

@@ -0,0 +1,432 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_flash.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the FLASH 
8
+  *          firmware library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_FLASH_H
31
+#define __STM32F10x_FLASH_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup FLASH
45
+  * @{
46
+  */
47
+
48
+/** @defgroup FLASH_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  FLASH Status  
54
+  */
55
+
56
+typedef enum
57
+{ 
58
+  FLASH_BUSY = 1,
59
+  FLASH_ERROR_PG,
60
+  FLASH_ERROR_WRP,
61
+  FLASH_COMPLETE,
62
+  FLASH_TIMEOUT
63
+}FLASH_Status;
64
+
65
+/**
66
+  * @}
67
+  */
68
+
69
+/** @defgroup FLASH_Exported_Constants
70
+  * @{
71
+  */
72
+
73
+/** @defgroup Flash_Latency 
74
+  * @{
75
+  */
76
+
77
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
78
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
79
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /*!< FLASH Two Latency cycles */
80
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
81
+                                   ((LATENCY) == FLASH_Latency_1) || \
82
+                                   ((LATENCY) == FLASH_Latency_2))
83
+/**
84
+  * @}
85
+  */
86
+
87
+/** @defgroup Half_Cycle_Enable_Disable 
88
+  * @{
89
+  */
90
+
91
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /*!< FLASH Half Cycle Enable */
92
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /*!< FLASH Half Cycle Disable */
93
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
94
+                                               ((STATE) == FLASH_HalfCycleAccess_Disable)) 
95
+/**
96
+  * @}
97
+  */
98
+
99
+/** @defgroup Prefetch_Buffer_Enable_Disable 
100
+  * @{
101
+  */
102
+
103
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /*!< FLASH Prefetch Buffer Enable */
104
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /*!< FLASH Prefetch Buffer Disable */
105
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
106
+                                              ((STATE) == FLASH_PrefetchBuffer_Disable)) 
107
+/**
108
+  * @}
109
+  */
110
+
111
+/** @defgroup Option_Bytes_Write_Protection 
112
+  * @{
113
+  */
114
+
115
+/* Values to be used with STM32 Low and Medium density devices */
116
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
117
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
118
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
119
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
120
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
121
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
122
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
123
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
124
+
125
+/* Values to be used with STM32 Medium-density devices */
126
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
127
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
128
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
129
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
130
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
131
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
132
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
133
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
134
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
135
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
136
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
137
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
138
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
139
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
140
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
141
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
142
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
143
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
144
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
145
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
146
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
147
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
148
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
149
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
150
+
151
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
152
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
153
+                                                                   Write protection of page 0 to 1 */
154
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
155
+                                                                   Write protection of page 2 to 3 */
156
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
157
+                                                                   Write protection of page 4 to 5 */
158
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
159
+                                                                   Write protection of page 6 to 7 */
160
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
161
+                                                                   Write protection of page 8 to 9 */
162
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
163
+                                                                   Write protection of page 10 to 11 */
164
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
165
+                                                                   Write protection of page 12 to 13 */
166
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
167
+                                                                   Write protection of page 14 to 15 */
168
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
169
+                                                                   Write protection of page 16 to 17 */
170
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
171
+                                                                   Write protection of page 18 to 19 */
172
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
173
+                                                                   Write protection of page 20 to 21 */
174
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
175
+                                                                   Write protection of page 22 to 23 */
176
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
177
+                                                                   Write protection of page 24 to 25 */
178
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
179
+                                                                   Write protection of page 26 to 27 */
180
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
181
+                                                                   Write protection of page 28 to 29 */
182
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
183
+                                                                   Write protection of page 30 to 31 */
184
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
185
+                                                                   Write protection of page 32 to 33 */
186
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
187
+                                                                   Write protection of page 34 to 35 */
188
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
189
+                                                                   Write protection of page 36 to 37 */
190
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
191
+                                                                   Write protection of page 38 to 39 */
192
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
193
+                                                                   Write protection of page 40 to 41 */
194
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
195
+                                                                   Write protection of page 42 to 43 */
196
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
197
+                                                                   Write protection of page 44 to 45 */
198
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
199
+                                                                   Write protection of page 46 to 47 */
200
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
201
+                                                                   Write protection of page 48 to 49 */
202
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
203
+                                                                   Write protection of page 50 to 51 */
204
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
205
+                                                                   Write protection of page 52 to 53 */
206
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
207
+                                                                   Write protection of page 54 to 55 */
208
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
209
+                                                                   Write protection of page 56 to 57 */
210
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
211
+                                                                   Write protection of page 58 to 59 */
212
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
213
+                                                                   Write protection of page 60 to 61 */
214
+#define FLASH_WRProt_Pages62to127      ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
215
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
216
+#define FLASH_WRProt_Pages62to511      ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
217
+
218
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
219
+
220
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
221
+
222
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
223
+
224
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
225
+
226
+/**
227
+  * @}
228
+  */
229
+
230
+/** @defgroup Option_Bytes_IWatchdog 
231
+  * @{
232
+  */
233
+
234
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /*!< Software IWDG selected */
235
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
236
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
237
+
238
+/**
239
+  * @}
240
+  */
241
+
242
+/** @defgroup Option_Bytes_nRST_STOP 
243
+  * @{
244
+  */
245
+
246
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
247
+#define OB_STOP_RST                    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
248
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
249
+
250
+/**
251
+  * @}
252
+  */
253
+
254
+/** @defgroup Option_Bytes_nRST_STDBY 
255
+  * @{
256
+  */
257
+
258
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
259
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
260
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
261
+
262
+#ifdef STM32F10X_XL
263
+/**
264
+  * @}
265
+  */
266
+/** @defgroup FLASH_Boot
267
+  * @{
268
+  */
269
+#define FLASH_BOOT_Bank1  ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
270
+                                                  and this parameter is selected the device will boot from Bank1(Default) */
271
+#define FLASH_BOOT_Bank2  ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
272
+                                                  and this parameter is selected the device will boot from Bank 2 or Bank 1,
273
+                                                  depending on the activation of the bank */
274
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
275
+#endif
276
+/**
277
+  * @}
278
+  */
279
+/** @defgroup FLASH_Interrupts 
280
+  * @{
281
+  */
282
+#ifdef STM32F10X_XL
283
+#define FLASH_IT_BANK2_ERROR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
284
+#define FLASH_IT_BANK2_EOP                   ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
285
+
286
+#define FLASH_IT_BANK1_ERROR                 FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
287
+#define FLASH_IT_BANK1_EOP                   FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
288
+
289
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC BANK1 error interrupt source */
290
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
291
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
292
+#else
293
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
294
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
295
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
296
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
297
+
298
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
299
+#endif
300
+
301
+/**
302
+  * @}
303
+  */
304
+
305
+/** @defgroup FLASH_Flags 
306
+  * @{
307
+  */
308
+#ifdef STM32F10X_XL
309
+#define FLASH_FLAG_BANK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
310
+#define FLASH_FLAG_BANK2_EOP                 ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
311
+#define FLASH_FLAG_BANK2_PGERR               ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
312
+#define FLASH_FLAG_BANK2_WRPRTERR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
313
+
314
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
315
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
316
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
317
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
318
+
319
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
320
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
321
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
322
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
323
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
324
+ 
325
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
326
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
327
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
328
+                                  ((FLAG) == FLASH_FLAG_OPTERR)|| \
329
+                                  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
330
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
331
+                                  ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
332
+                                  ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
333
+#else
334
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
335
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
336
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
337
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
338
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
339
+
340
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
341
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
342
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
343
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
344
+ 
345
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
346
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
347
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
348
+								  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
349
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
350
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
351
+#endif
352
+
353
+/**
354
+  * @}
355
+  */
356
+
357
+/**
358
+  * @}
359
+  */
360
+
361
+/** @defgroup FLASH_Exported_Macros
362
+  * @{
363
+  */
364
+
365
+/**
366
+  * @}
367
+  */
368
+
369
+/** @defgroup FLASH_Exported_Functions
370
+  * @{
371
+  */
372
+
373
+/*------------ Functions used for all STM32F10x devices -----*/
374
+void FLASH_SetLatency(uint32_t FLASH_Latency);
375
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
376
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
377
+void FLASH_Unlock(void);
378
+void FLASH_Lock(void);
379
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
380
+FLASH_Status FLASH_EraseAllPages(void);
381
+FLASH_Status FLASH_EraseOptionBytes(void);
382
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
383
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
384
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
385
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
386
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
387
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
388
+uint32_t FLASH_GetUserOptionByte(void);
389
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
390
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
391
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
392
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
393
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
394
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
395
+FLASH_Status FLASH_GetStatus(void);
396
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
397
+
398
+/*------------ New function used for all STM32F10x devices -----*/
399
+void FLASH_UnlockBank1(void);
400
+void FLASH_LockBank1(void);
401
+FLASH_Status FLASH_EraseAllBank1Pages(void);
402
+FLASH_Status FLASH_GetBank1Status(void);
403
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
404
+
405
+#ifdef STM32F10X_XL
406
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
407
+void FLASH_UnlockBank2(void);
408
+void FLASH_LockBank2(void);
409
+FLASH_Status FLASH_EraseAllBank2Pages(void);
410
+FLASH_Status FLASH_GetBank2Status(void);
411
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
412
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
413
+#endif
414
+
415
+#ifdef __cplusplus
416
+}
417
+#endif
418
+
419
+#endif /* __STM32F10x_FLASH_H */
420
+/**
421
+  * @}
422
+  */
423
+
424
+/**
425
+  * @}
426
+  */
427
+
428
+/**
429
+  * @}
430
+  */
431
+
432
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 739
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h View File

@@ -0,0 +1,739 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_fsmc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_FSMC_H
31
+#define __STM32F10x_FSMC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup FSMC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup FSMC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  Timing parameters For NOR/SRAM Banks  
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
59
+                                             the duration of the address setup time. 
60
+                                             This parameter can be a value between 0 and 0xF.
61
+                                             @note: It is not used with synchronous NOR Flash memories. */
62
+
63
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
64
+                                             the duration of the address hold time.
65
+                                             This parameter can be a value between 0 and 0xF. 
66
+                                             @note: It is not used with synchronous NOR Flash memories.*/
67
+
68
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
69
+                                             the duration of the data setup time.
70
+                                             This parameter can be a value between 0 and 0xFF.
71
+                                             @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
72
+
73
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
74
+                                             the duration of the bus turnaround.
75
+                                             This parameter can be a value between 0 and 0xF.
76
+                                             @note: It is only used for multiplexed NOR Flash memories. */
77
+
78
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
79
+                                             This parameter can be a value between 1 and 0xF.
80
+                                             @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
81
+
82
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
83
+                                             to the memory before getting the first data.
84
+                                             The value of this parameter depends on the memory type as shown below:
85
+                                              - It must be set to 0 in case of a CRAM
86
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
87
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
88
+                                                with synchronous burst mode enable */
89
+
90
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
91
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
92
+}FSMC_NORSRAMTimingInitTypeDef;
93
+
94
+/** 
95
+  * @brief  FSMC NOR/SRAM Init structure definition
96
+  */
97
+
98
+typedef struct
99
+{
100
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
101
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
102
+
103
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
104
+                                          multiplexed on the databus or not. 
105
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
106
+
107
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
108
+                                          the corresponding memory bank.
109
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
110
+
111
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
112
+                                          This parameter can be a value of @ref FSMC_Data_Width */
113
+
114
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
115
+                                          valid only with synchronous burst Flash memories.
116
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
117
+                                       
118
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
119
+                                          valid only with asynchronous Flash memories.
120
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */
121
+
122
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
123
+                                          the Flash memory in burst mode.
124
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
125
+
126
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
127
+                                          memory, valid only when accessing Flash memories in burst mode.
128
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
129
+
130
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
131
+                                          clock cycle before the wait state or during the wait state,
132
+                                          valid only when accessing memories in burst mode. 
133
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
134
+
135
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
136
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
137
+
138
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
139
+                                          signal, valid for Flash memory access in burst mode. 
140
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
141
+
142
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
143
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
144
+
145
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
146
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
147
+
148
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
149
+
150
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
151
+}FSMC_NORSRAMInitTypeDef;
152
+
153
+/** 
154
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
155
+  */
156
+
157
+typedef struct
158
+{
159
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
160
+                                     the command assertion for NAND-Flash read or write access
161
+                                     to common/Attribute or I/O memory space (depending on
162
+                                     the memory space timing to be configured).
163
+                                     This parameter can be a value between 0 and 0xFF.*/
164
+
165
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
166
+                                     command for NAND-Flash read or write access to
167
+                                     common/Attribute or I/O memory space (depending on the
168
+                                     memory space timing to be configured). 
169
+                                     This parameter can be a number between 0x00 and 0xFF */
170
+
171
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
172
+                                     (and data for write access) after the command deassertion
173
+                                     for NAND-Flash read or write access to common/Attribute
174
+                                     or I/O memory space (depending on the memory space timing
175
+                                     to be configured).
176
+                                     This parameter can be a number between 0x00 and 0xFF */
177
+
178
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
179
+                                     databus is kept in HiZ after the start of a NAND-Flash
180
+                                     write access to common/Attribute or I/O memory space (depending
181
+                                     on the memory space timing to be configured).
182
+                                     This parameter can be a number between 0x00 and 0xFF */
183
+}FSMC_NAND_PCCARDTimingInitTypeDef;
184
+
185
+/** 
186
+  * @brief  FSMC NAND Init structure definition
187
+  */
188
+
189
+typedef struct
190
+{
191
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
192
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
193
+
194
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
195
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
196
+
197
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
198
+                                       This parameter can be any value of @ref FSMC_Data_Width */
199
+
200
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
201
+                                       This parameter can be any value of @ref FSMC_ECC */
202
+
203
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
204
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
205
+
206
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
207
+                                       delay between CLE low and RE low.
208
+                                       This parameter can be a value between 0 and 0xFF. */
209
+
210
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
211
+                                       delay between ALE low and RE low.
212
+                                       This parameter can be a number between 0x0 and 0xFF */ 
213
+
214
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
215
+
216
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
217
+}FSMC_NANDInitTypeDef;
218
+
219
+/** 
220
+  * @brief  FSMC PCCARD Init structure definition
221
+  */
222
+
223
+typedef struct
224
+{
225
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
226
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
227
+
228
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
229
+                                     delay between CLE low and RE low.
230
+                                     This parameter can be a value between 0 and 0xFF. */
231
+
232
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
233
+                                     delay between ALE low and RE low.
234
+                                     This parameter can be a number between 0x0 and 0xFF */ 
235
+
236
+  
237
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
238
+
239
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
240
+  
241
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
242
+}FSMC_PCCARDInitTypeDef;
243
+
244
+/**
245
+  * @}
246
+  */
247
+
248
+/** @defgroup FSMC_Exported_Constants
249
+  * @{
250
+  */
251
+
252
+/** @defgroup FSMC_NORSRAM_Bank 
253
+  * @{
254
+  */
255
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
256
+#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
257
+#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
258
+#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
259
+/**
260
+  * @}
261
+  */
262
+
263
+/** @defgroup FSMC_NAND_Bank 
264
+  * @{
265
+  */  
266
+#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
267
+#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
268
+/**
269
+  * @}
270
+  */
271
+
272
+/** @defgroup FSMC_PCCARD_Bank 
273
+  * @{
274
+  */    
275
+#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
276
+/**
277
+  * @}
278
+  */
279
+
280
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
281
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
282
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
283
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
284
+
285
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
286
+                                 ((BANK) == FSMC_Bank3_NAND))
287
+
288
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
289
+                                    ((BANK) == FSMC_Bank3_NAND) || \
290
+                                    ((BANK) == FSMC_Bank4_PCCARD))
291
+
292
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
293
+                               ((BANK) == FSMC_Bank3_NAND) || \
294
+                               ((BANK) == FSMC_Bank4_PCCARD))
295
+
296
+/** @defgroup NOR_SRAM_Controller 
297
+  * @{
298
+  */
299
+
300
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
301
+  * @{
302
+  */
303
+
304
+#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
305
+#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
306
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
307
+                          ((MUX) == FSMC_DataAddressMux_Enable))
308
+
309
+/**
310
+  * @}
311
+  */
312
+
313
+/** @defgroup FSMC_Memory_Type 
314
+  * @{
315
+  */
316
+
317
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
318
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
319
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
320
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
321
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
322
+                                ((MEMORY) == FSMC_MemoryType_NOR))
323
+
324
+/**
325
+  * @}
326
+  */
327
+
328
+/** @defgroup FSMC_Data_Width 
329
+  * @{
330
+  */
331
+
332
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
333
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
334
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
335
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
336
+
337
+/**
338
+  * @}
339
+  */
340
+
341
+/** @defgroup FSMC_Burst_Access_Mode 
342
+  * @{
343
+  */
344
+
345
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
346
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
347
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
348
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
349
+/**
350
+  * @}
351
+  */
352
+  
353
+/** @defgroup FSMC_AsynchronousWait 
354
+  * @{
355
+  */
356
+#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
357
+#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
358
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
359
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
360
+
361
+/**
362
+  * @}
363
+  */
364
+  
365
+/** @defgroup FSMC_Wait_Signal_Polarity 
366
+  * @{
367
+  */
368
+
369
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
370
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
371
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
372
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
373
+
374
+/**
375
+  * @}
376
+  */
377
+
378
+/** @defgroup FSMC_Wrap_Mode 
379
+  * @{
380
+  */
381
+
382
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
383
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
384
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
385
+                                 ((MODE) == FSMC_WrapMode_Enable))
386
+
387
+/**
388
+  * @}
389
+  */
390
+
391
+/** @defgroup FSMC_Wait_Timing 
392
+  * @{
393
+  */
394
+
395
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
396
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
397
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
398
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
399
+
400
+/**
401
+  * @}
402
+  */
403
+
404
+/** @defgroup FSMC_Write_Operation 
405
+  * @{
406
+  */
407
+
408
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
409
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
410
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
411
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))
412
+                              
413
+/**
414
+  * @}
415
+  */
416
+
417
+/** @defgroup FSMC_Wait_Signal 
418
+  * @{
419
+  */
420
+
421
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
422
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
423
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
424
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
425
+/**
426
+  * @}
427
+  */
428
+
429
+/** @defgroup FSMC_Extended_Mode 
430
+  * @{
431
+  */
432
+
433
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
434
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
435
+
436
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
437
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
438
+
439
+/**
440
+  * @}
441
+  */
442
+
443
+/** @defgroup FSMC_Write_Burst 
444
+  * @{
445
+  */
446
+
447
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
448
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
449
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
450
+                                    ((BURST) == FSMC_WriteBurst_Enable))
451
+/**
452
+  * @}
453
+  */
454
+
455
+/** @defgroup FSMC_Address_Setup_Time 
456
+  * @{
457
+  */
458
+
459
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
460
+
461
+/**
462
+  * @}
463
+  */
464
+
465
+/** @defgroup FSMC_Address_Hold_Time 
466
+  * @{
467
+  */
468
+
469
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
470
+
471
+/**
472
+  * @}
473
+  */
474
+
475
+/** @defgroup FSMC_Data_Setup_Time 
476
+  * @{
477
+  */
478
+
479
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
480
+
481
+/**
482
+  * @}
483
+  */
484
+
485
+/** @defgroup FSMC_Bus_Turn_around_Duration 
486
+  * @{
487
+  */
488
+
489
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
490
+
491
+/**
492
+  * @}
493
+  */
494
+
495
+/** @defgroup FSMC_CLK_Division 
496
+  * @{
497
+  */
498
+
499
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
500
+
501
+/**
502
+  * @}
503
+  */
504
+
505
+/** @defgroup FSMC_Data_Latency 
506
+  * @{
507
+  */
508
+
509
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
510
+
511
+/**
512
+  * @}
513
+  */
514
+
515
+/** @defgroup FSMC_Access_Mode 
516
+  * @{
517
+  */
518
+
519
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
520
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
521
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
522
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
523
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
524
+                                   ((MODE) == FSMC_AccessMode_B) || \
525
+                                   ((MODE) == FSMC_AccessMode_C) || \
526
+                                   ((MODE) == FSMC_AccessMode_D)) 
527
+
528
+/**
529
+  * @}
530
+  */
531
+
532
+/**
533
+  * @}
534
+  */
535
+  
536
+/** @defgroup NAND_PCCARD_Controller 
537
+  * @{
538
+  */
539
+
540
+/** @defgroup FSMC_Wait_feature 
541
+  * @{
542
+  */
543
+
544
+#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
545
+#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
546
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
547
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
548
+
549
+/**
550
+  * @}
551
+  */
552
+
553
+
554
+/** @defgroup FSMC_ECC 
555
+  * @{
556
+  */
557
+
558
+#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
559
+#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
560
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
561
+                                  ((STATE) == FSMC_ECC_Enable))
562
+
563
+/**
564
+  * @}
565
+  */
566
+
567
+/** @defgroup FSMC_ECC_Page_Size 
568
+  * @{
569
+  */
570
+
571
+#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
572
+#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
573
+#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
574
+#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
575
+#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
576
+#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
577
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
578
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
579
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
580
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
581
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
582
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
583
+
584
+/**
585
+  * @}
586
+  */
587
+
588
+/** @defgroup FSMC_TCLR_Setup_Time 
589
+  * @{
590
+  */
591
+
592
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
593
+
594
+/**
595
+  * @}
596
+  */
597
+
598
+/** @defgroup FSMC_TAR_Setup_Time 
599
+  * @{
600
+  */
601
+
602
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
603
+
604
+/**
605
+  * @}
606
+  */
607
+
608
+/** @defgroup FSMC_Setup_Time 
609
+  * @{
610
+  */
611
+
612
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
613
+
614
+/**
615
+  * @}
616
+  */
617
+
618
+/** @defgroup FSMC_Wait_Setup_Time 
619
+  * @{
620
+  */
621
+
622
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
623
+
624
+/**
625
+  * @}
626
+  */
627
+
628
+/** @defgroup FSMC_Hold_Setup_Time 
629
+  * @{
630
+  */
631
+
632
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
633
+
634
+/**
635
+  * @}
636
+  */
637
+
638
+/** @defgroup FSMC_HiZ_Setup_Time 
639
+  * @{
640
+  */
641
+
642
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
643
+
644
+/**
645
+  * @}
646
+  */
647
+
648
+/** @defgroup FSMC_Interrupt_sources 
649
+  * @{
650
+  */
651
+
652
+#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
653
+#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
654
+#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
655
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
656
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
657
+                            ((IT) == FSMC_IT_Level) || \
658
+                            ((IT) == FSMC_IT_FallingEdge)) 
659
+/**
660
+  * @}
661
+  */
662
+
663
+/** @defgroup FSMC_Flags 
664
+  * @{
665
+  */
666
+
667
+#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
668
+#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
669
+#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
670
+#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
671
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
672
+                                ((FLAG) == FSMC_FLAG_Level) || \
673
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
674
+                                ((FLAG) == FSMC_FLAG_FEMPT))
675
+
676
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
677
+
678
+/**
679
+  * @}
680
+  */
681
+
682
+/**
683
+  * @}
684
+  */
685
+
686
+/**
687
+  * @}
688
+  */
689
+
690
+/** @defgroup FSMC_Exported_Macros
691
+  * @{
692
+  */
693
+
694
+/**
695
+  * @}
696
+  */
697
+
698
+/** @defgroup FSMC_Exported_Functions
699
+  * @{
700
+  */
701
+
702
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
703
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
704
+void FSMC_PCCARDDeInit(void);
705
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
706
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
707
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
708
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
709
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
710
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
711
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
712
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
713
+void FSMC_PCCARDCmd(FunctionalState NewState);
714
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
715
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
716
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
717
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
718
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
719
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
720
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
721
+
722
+#ifdef __cplusplus
723
+}
724
+#endif
725
+
726
+#endif /*__STM32F10x_FSMC_H */
727
+/**
728
+  * @}
729
+  */
730
+
731
+/**
732
+  * @}
733
+  */
734
+
735
+/**
736
+  * @}
737
+  */ 
738
+
739
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 391
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h View File

@@ -0,0 +1,391 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_gpio.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the GPIO 
8
+  *          firmware library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_GPIO_H
31
+#define __STM32F10x_GPIO_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup GPIO
45
+  * @{
46
+  */
47
+
48
+/** @defgroup GPIO_Exported_Types
49
+  * @{
50
+  */
51
+
52
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
53
+                                    ((PERIPH) == GPIOB) || \
54
+                                    ((PERIPH) == GPIOC) || \
55
+                                    ((PERIPH) == GPIOD) || \
56
+                                    ((PERIPH) == GPIOE) || \
57
+                                    ((PERIPH) == GPIOF) || \
58
+                                    ((PERIPH) == GPIOG))
59
+                                     
60
+/** 
61
+  * @brief  Output Maximum frequency selection  
62
+  */
63
+
64
+typedef enum
65
+{ 
66
+  GPIO_Speed_10MHz = 1,
67
+  GPIO_Speed_2MHz, 
68
+  GPIO_Speed_50MHz
69
+}GPIOSpeed_TypeDef;
70
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
71
+                              ((SPEED) == GPIO_Speed_50MHz))
72
+
73
+/** 
74
+  * @brief  Configuration Mode enumeration  
75
+  */
76
+
77
+typedef enum
78
+{ GPIO_Mode_AIN = 0x0,
79
+  GPIO_Mode_IN_FLOATING = 0x04,
80
+  GPIO_Mode_IPD = 0x28,
81
+  GPIO_Mode_IPU = 0x48,
82
+  GPIO_Mode_Out_OD = 0x14,
83
+  GPIO_Mode_Out_PP = 0x10,
84
+  GPIO_Mode_AF_OD = 0x1C,
85
+  GPIO_Mode_AF_PP = 0x18
86
+}GPIOMode_TypeDef;
87
+
88
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
89
+                            ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
90
+                            ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
91
+                            ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
92
+
93
+/** 
94
+  * @brief  GPIO Init structure definition  
95
+  */
96
+
97
+typedef struct
98
+{
99
+  uint16_t GPIO_Pin;             /*!< Specifies the GPIO pins to be configured.
100
+                                      This parameter can be any value of @ref GPIO_pins_define */
101
+
102
+  GPIOSpeed_TypeDef GPIO_Speed;  /*!< Specifies the speed for the selected pins.
103
+                                      This parameter can be a value of @ref GPIOSpeed_TypeDef */
104
+
105
+  GPIOMode_TypeDef GPIO_Mode;    /*!< Specifies the operating mode for the selected pins.
106
+                                      This parameter can be a value of @ref GPIOMode_TypeDef */
107
+}GPIO_InitTypeDef;
108
+
109
+
110
+/** 
111
+  * @brief  Bit_SET and Bit_RESET enumeration  
112
+  */
113
+
114
+typedef enum
115
+{ Bit_RESET = 0,
116
+  Bit_SET
117
+}BitAction;
118
+
119
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
120
+
121
+/**
122
+  * @}
123
+  */
124
+
125
+/** @defgroup GPIO_Exported_Constants
126
+  * @{
127
+  */
128
+
129
+/** @defgroup GPIO_pins_define 
130
+  * @{
131
+  */
132
+
133
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
134
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
135
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
136
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
137
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
138
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
139
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
140
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
141
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
142
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
143
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
144
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
145
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
146
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
147
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
148
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
149
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
150
+
151
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
152
+
153
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
154
+                              ((PIN) == GPIO_Pin_1) || \
155
+                              ((PIN) == GPIO_Pin_2) || \
156
+                              ((PIN) == GPIO_Pin_3) || \
157
+                              ((PIN) == GPIO_Pin_4) || \
158
+                              ((PIN) == GPIO_Pin_5) || \
159
+                              ((PIN) == GPIO_Pin_6) || \
160
+                              ((PIN) == GPIO_Pin_7) || \
161
+                              ((PIN) == GPIO_Pin_8) || \
162
+                              ((PIN) == GPIO_Pin_9) || \
163
+                              ((PIN) == GPIO_Pin_10) || \
164
+                              ((PIN) == GPIO_Pin_11) || \
165
+                              ((PIN) == GPIO_Pin_12) || \
166
+                              ((PIN) == GPIO_Pin_13) || \
167
+                              ((PIN) == GPIO_Pin_14) || \
168
+                              ((PIN) == GPIO_Pin_15))
169
+
170
+/**
171
+  * @}
172
+  */
173
+
174
+/** @defgroup GPIO_Remap_define 
175
+  * @{
176
+  */
177
+
178
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping */
179
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
180
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
181
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
182
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /*!< USART3 Partial Alternate Function mapping */
183
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /*!< USART3 Full Alternate Function mapping */
184
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /*!< TIM1 Partial Alternate Function mapping */
185
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /*!< TIM1 Full Alternate Function mapping */
186
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /*!< TIM2 Partial1 Alternate Function mapping */
187
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /*!< TIM2 Partial2 Alternate Function mapping */
188
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /*!< TIM2 Full Alternate Function mapping */
189
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /*!< TIM3 Partial Alternate Function mapping */
190
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /*!< TIM3 Full Alternate Function mapping */
191
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /*!< TIM4 Alternate Function mapping */
192
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /*!< CAN1 Alternate Function mapping */
193
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /*!< CAN1 Alternate Function mapping */
194
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
195
+#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /*!< LSI connected to TIM5 Channel4 input capture for calibration */
196
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /*!< ADC1 External Trigger Injected Conversion remapping */
197
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /*!< ADC1 External Trigger Regular Conversion remapping */
198
+#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /*!< ADC2 External Trigger Injected Conversion remapping */
199
+#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /*!< ADC2 External Trigger Regular Conversion remapping */
200
+#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /*!< Ethernet remapping (only for Connectivity line devices) */
201
+#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /*!< CAN2 remapping (only for Connectivity line devices) */
202
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
203
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /*!< JTAG-DP Disabled and SW-DP Enabled */
204
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
205
+#define GPIO_Remap_SPI3             ((uint32_t)0x00201100)  /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
206
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
207
+                                                                 to TIM2 Internal Trigger 1 for calibration
208
+                                                                 (only for Connectivity line devices) */
209
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
210
+
211
+#define GPIO_Remap_TIM15            ((uint32_t)0x80000001)  /*!< TIM15 Alternate Function mapping (only for Value line devices) */
212
+#define GPIO_Remap_TIM16            ((uint32_t)0x80000002)  /*!< TIM16 Alternate Function mapping (only for Value line devices) */
213
+#define GPIO_Remap_TIM17            ((uint32_t)0x80000004)  /*!< TIM17 Alternate Function mapping (only for Value line devices) */
214
+#define GPIO_Remap_CEC              ((uint32_t)0x80000008)  /*!< CEC Alternate Function mapping (only for Value line devices) */
215
+#define GPIO_Remap_TIM1_DMA         ((uint32_t)0x80000010)  /*!< TIM1 DMA requests mapping (only for Value line devices) */
216
+
217
+#define GPIO_Remap_TIM9             ((uint32_t)0x80000020)  /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
218
+#define GPIO_Remap_TIM10            ((uint32_t)0x80000040)  /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
219
+#define GPIO_Remap_TIM11            ((uint32_t)0x80000080)  /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
220
+#define GPIO_Remap_TIM13            ((uint32_t)0x80000100)  /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
221
+#define GPIO_Remap_TIM14            ((uint32_t)0x80000200)  /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
222
+#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
223
+
224
+#define GPIO_Remap_TIM67_DAC_DMA    ((uint32_t)0x80000800)  /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
225
+#define GPIO_Remap_TIM12            ((uint32_t)0x80001000)  /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
226
+#define GPIO_Remap_MISC             ((uint32_t)0x80002000)  /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
227
+                                                                 only for High density Value line devices) */                                                       
228
+
229
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
230
+                              ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
231
+                              ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
232
+                              ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
233
+                              ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
234
+                              ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
235
+                              ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
236
+                              ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
237
+                              ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
238
+                              ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
239
+                              ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
240
+                              ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
241
+                              ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
242
+                              ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
243
+                              ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
244
+                              ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
245
+                              ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
246
+                              ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
247
+                              ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
248
+                              ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
249
+                              ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
250
+                              ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
251
+                              
252
+/**
253
+  * @}
254
+  */ 
255
+
256
+/** @defgroup GPIO_Port_Sources 
257
+  * @{
258
+  */
259
+
260
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
261
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
262
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
263
+#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
264
+#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
265
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
266
+#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
267
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
268
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
269
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
270
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
271
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))
272
+
273
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
274
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
275
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
276
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
277
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
278
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
279
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOG))
280
+
281
+/**
282
+  * @}
283
+  */
284
+
285
+/** @defgroup GPIO_Pin_sources 
286
+  * @{
287
+  */
288
+
289
+#define GPIO_PinSource0            ((uint8_t)0x00)
290
+#define GPIO_PinSource1            ((uint8_t)0x01)
291
+#define GPIO_PinSource2            ((uint8_t)0x02)
292
+#define GPIO_PinSource3            ((uint8_t)0x03)
293
+#define GPIO_PinSource4            ((uint8_t)0x04)
294
+#define GPIO_PinSource5            ((uint8_t)0x05)
295
+#define GPIO_PinSource6            ((uint8_t)0x06)
296
+#define GPIO_PinSource7            ((uint8_t)0x07)
297
+#define GPIO_PinSource8            ((uint8_t)0x08)
298
+#define GPIO_PinSource9            ((uint8_t)0x09)
299
+#define GPIO_PinSource10           ((uint8_t)0x0A)
300
+#define GPIO_PinSource11           ((uint8_t)0x0B)
301
+#define GPIO_PinSource12           ((uint8_t)0x0C)
302
+#define GPIO_PinSource13           ((uint8_t)0x0D)
303
+#define GPIO_PinSource14           ((uint8_t)0x0E)
304
+#define GPIO_PinSource15           ((uint8_t)0x0F)
305
+
306
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
307
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
308
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
309
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
310
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
311
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
312
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
313
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
314
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
315
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
316
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
317
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
318
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
319
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
320
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
321
+                                       ((PINSOURCE) == GPIO_PinSource15))
322
+
323
+/**
324
+  * @}
325
+  */
326
+
327
+/** @defgroup Ethernet_Media_Interface 
328
+  * @{
329
+  */ 
330
+#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000) 
331
+#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)                                       
332
+
333
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
334
+                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
335
+
336
+/**
337
+  * @}
338
+  */                                                
339
+/**
340
+  * @}
341
+  */
342
+
343
+/** @defgroup GPIO_Exported_Macros
344
+  * @{
345
+  */
346
+
347
+/**
348
+  * @}
349
+  */
350
+
351
+/** @defgroup GPIO_Exported_Functions
352
+  * @{
353
+  */
354
+
355
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
356
+void GPIO_AFIODeInit(void);
357
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
358
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
359
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
360
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
361
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
362
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
363
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
364
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
365
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
366
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
367
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
368
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
369
+void GPIO_EventOutputCmd(FunctionalState NewState);
370
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
371
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
372
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
373
+
374
+#ifdef __cplusplus
375
+}
376
+#endif
377
+
378
+#endif /* __STM32F10x_GPIO_H */
379
+/**
380
+  * @}
381
+  */
382
+
383
+/**
384
+  * @}
385
+  */
386
+
387
+/**
388
+  * @}
389
+  */
390
+
391
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 690
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h View File

@@ -0,0 +1,690 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_i2c.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_I2C_H
31
+#define __STM32F10x_I2C_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup I2C
45
+  * @{
46
+  */
47
+
48
+/** @defgroup I2C_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  I2C Init structure definition  
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
59
+                                         This parameter must be set to a value lower than 400kHz */
60
+
61
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
62
+                                         This parameter can be a value of @ref I2C_mode */
63
+
64
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
65
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
66
+
67
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
68
+                                         This parameter can be a 7-bit or 10-bit address. */
69
+
70
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
71
+                                         This parameter can be a value of @ref I2C_acknowledgement */
72
+
73
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
74
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
75
+}I2C_InitTypeDef;
76
+
77
+/**
78
+  * @}
79
+  */ 
80
+
81
+
82
+/** @defgroup I2C_Exported_Constants
83
+  * @{
84
+  */
85
+
86
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
87
+                                   ((PERIPH) == I2C2))
88
+/** @defgroup I2C_mode 
89
+  * @{
90
+  */
91
+
92
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
93
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
94
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
95
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
96
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
97
+                           ((MODE) == I2C_Mode_SMBusHost))
98
+/**
99
+  * @}
100
+  */
101
+
102
+/** @defgroup I2C_duty_cycle_in_fast_mode 
103
+  * @{
104
+  */
105
+
106
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
107
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
108
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
109
+                                  ((CYCLE) == I2C_DutyCycle_2))
110
+/**
111
+  * @}
112
+  */ 
113
+
114
+/** @defgroup I2C_acknowledgement
115
+  * @{
116
+  */
117
+
118
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
119
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
120
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
121
+                                 ((STATE) == I2C_Ack_Disable))
122
+/**
123
+  * @}
124
+  */
125
+
126
+/** @defgroup I2C_transfer_direction 
127
+  * @{
128
+  */
129
+
130
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
131
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
132
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
133
+                                     ((DIRECTION) == I2C_Direction_Receiver))
134
+/**
135
+  * @}
136
+  */
137
+
138
+/** @defgroup I2C_acknowledged_address 
139
+  * @{
140
+  */
141
+
142
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
143
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
144
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
145
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
146
+/**
147
+  * @}
148
+  */ 
149
+
150
+/** @defgroup I2C_registers 
151
+  * @{
152
+  */
153
+
154
+#define I2C_Register_CR1                ((uint8_t)0x00)
155
+#define I2C_Register_CR2                ((uint8_t)0x04)
156
+#define I2C_Register_OAR1               ((uint8_t)0x08)
157
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
158
+#define I2C_Register_DR                 ((uint8_t)0x10)
159
+#define I2C_Register_SR1                ((uint8_t)0x14)
160
+#define I2C_Register_SR2                ((uint8_t)0x18)
161
+#define I2C_Register_CCR                ((uint8_t)0x1C)
162
+#define I2C_Register_TRISE              ((uint8_t)0x20)
163
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
164
+                                   ((REGISTER) == I2C_Register_CR2) || \
165
+                                   ((REGISTER) == I2C_Register_OAR1) || \
166
+                                   ((REGISTER) == I2C_Register_OAR2) || \
167
+                                   ((REGISTER) == I2C_Register_DR) || \
168
+                                   ((REGISTER) == I2C_Register_SR1) || \
169
+                                   ((REGISTER) == I2C_Register_SR2) || \
170
+                                   ((REGISTER) == I2C_Register_CCR) || \
171
+                                   ((REGISTER) == I2C_Register_TRISE))
172
+/**
173
+  * @}
174
+  */
175
+
176
+/** @defgroup I2C_SMBus_alert_pin_level 
177
+  * @{
178
+  */
179
+
180
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
181
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
182
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
183
+                                   ((ALERT) == I2C_SMBusAlert_High))
184
+/**
185
+  * @}
186
+  */
187
+
188
+/** @defgroup I2C_PEC_position 
189
+  * @{
190
+  */
191
+
192
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
193
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
194
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
195
+                                       ((POSITION) == I2C_PECPosition_Current))
196
+/**
197
+  * @}
198
+  */ 
199
+
200
+/** @defgroup I2C_NCAK_position 
201
+  * @{
202
+  */
203
+
204
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
205
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
206
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
207
+                                         ((POSITION) == I2C_NACKPosition_Current))
208
+/**
209
+  * @}
210
+  */ 
211
+
212
+/** @defgroup I2C_interrupts_definition 
213
+  * @{
214
+  */
215
+
216
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
217
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
218
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
219
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
220
+/**
221
+  * @}
222
+  */ 
223
+
224
+/** @defgroup I2C_interrupts_definition 
225
+  * @{
226
+  */
227
+
228
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
229
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
230
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
231
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
232
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
233
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
234
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
235
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
236
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
237
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
238
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
239
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
240
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
241
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
242
+
243
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
244
+
245
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
246
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
247
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
248
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
249
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
250
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
251
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
252
+/**
253
+  * @}
254
+  */
255
+
256
+/** @defgroup I2C_flags_definition 
257
+  * @{
258
+  */
259
+
260
+/** 
261
+  * @brief  SR2 register flags  
262
+  */
263
+
264
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
265
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
266
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
267
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
268
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
269
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
270
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
271
+
272
+/** 
273
+  * @brief  SR1 register flags  
274
+  */
275
+
276
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
277
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
278
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
279
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
280
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
281
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
282
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
283
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
284
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
285
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
286
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
287
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
288
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
289
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
290
+
291
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
292
+
293
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
294
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
295
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
296
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
297
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
298
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
299
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
300
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
301
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
302
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
303
+                               ((FLAG) == I2C_FLAG_SB))
304
+/**
305
+  * @}
306
+  */
307
+
308
+/** @defgroup I2C_Events 
309
+  * @{
310
+  */
311
+
312
+/*========================================
313
+     
314
+                     I2C Master Events (Events grouped in order of communication)
315
+                                                        ==========================================*/
316
+/** 
317
+  * @brief  Communication start
318
+  * 
319
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
320
+  * has to wait for this event. It means that the Start condition has been correctly 
321
+  * released on the I2C bus (the bus is free, no other devices is communicating).
322
+  * 
323
+  */
324
+/* --EV5 */
325
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
326
+
327
+/** 
328
+  * @brief  Address Acknowledge
329
+  * 
330
+  * After checking on EV5 (start condition correctly released on the bus), the 
331
+  * master sends the address of the slave(s) with which it will communicate 
332
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
333
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
334
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
335
+  * be set:
336
+  * 
337
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
338
+  *     event is set.
339
+  *  
340
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
341
+  *     is set
342
+  *  
343
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
344
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
345
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
346
+  *  header has been correctly sent on the bus. Then master should send the second part of 
347
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
348
+  *  should wait for event EV6. 
349
+  *     
350
+  */
351
+
352
+/* --EV6 */
353
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
354
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
355
+/* --EV9 */
356
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
357
+
358
+/** 
359
+  * @brief Communication events
360
+  * 
361
+  * If a communication is established (START condition generated and slave address 
362
+  * acknowledged) then the master has to check on one of the following events for 
363
+  * communication procedures:
364
+  *  
365
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
366
+  *    the data received from the slave (I2C_ReceiveData() function).
367
+  * 
368
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
369
+  *    function) then to wait on event EV8 or EV8_2.
370
+  *    These two events are similar: 
371
+  *     - EV8 means that the data has been written in the data register and is 
372
+  *       being shifted out.
373
+  *     - EV8_2 means that the data has been physically shifted out and output 
374
+  *       on the bus.
375
+  *     In most cases, using EV8 is sufficient for the application.
376
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
377
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
378
+  *     (before Stop condition generation).
379
+  *     
380
+  *  @note In case the  user software does not guarantee that this event EV7 is 
381
+  *  managed before the current byte end of transfer, then user may check on EV7 
382
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
383
+  *  In this case the communication may be slower.
384
+  * 
385
+  */
386
+
387
+/* Master RECEIVER mode -----------------------------*/ 
388
+/* --EV7 */
389
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
390
+
391
+/* Master TRANSMITTER mode --------------------------*/
392
+/* --EV8 */
393
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
394
+/* --EV8_2 */
395
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
396
+
397
+
398
+/*========================================
399
+     
400
+                     I2C Slave Events (Events grouped in order of communication)
401
+                                                        ==========================================*/
402
+
403
+/** 
404
+  * @brief  Communication start events
405
+  * 
406
+  * Wait on one of these events at the start of the communication. It means that 
407
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
408
+  * device) followed by the peripheral address. The peripheral generates an ACK 
409
+  * condition on the bus (if the acknowledge feature is enabled through function 
410
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
411
+  *  
412
+  * 1) In normal case (only one address managed by the slave), when the address 
413
+  *   sent by the master matches the own address of the peripheral (configured by 
414
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
415
+  *   (where XXX could be TRANSMITTER or RECEIVER).
416
+  *    
417
+  * 2) In case the address sent by the master matches the second address of the 
418
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
419
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
420
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
421
+  *   
422
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
423
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
424
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
425
+  * 
426
+  */
427
+
428
+/* --EV1  (all the events below are variants of EV1) */   
429
+/* 1) Case of One Single Address managed by the slave */
430
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
431
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
432
+
433
+/* 2) Case of Dual address managed by the slave */
434
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
435
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
436
+
437
+/* 3) Case of General Call enabled for the slave */
438
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
439
+
440
+/** 
441
+  * @brief  Communication events
442
+  * 
443
+  * Wait on one of these events when EV1 has already been checked and: 
444
+  * 
445
+  * - Slave RECEIVER mode:
446
+  *     - EV2: When the application is expecting a data byte to be received. 
447
+  *     - EV4: When the application is expecting the end of the communication: master 
448
+  *       sends a stop condition and data transmission is stopped.
449
+  *    
450
+  * - Slave Transmitter mode:
451
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
452
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
453
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
454
+  *      used when the user software doesn't guarantee the EV3 is managed before the
455
+  *      current byte end of transfer.
456
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
457
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
458
+  *      data bytes and expect a Stop condition on the bus.
459
+  *      
460
+  *  @note In case the  user software does not guarantee that the event EV2 is 
461
+  *  managed before the current byte end of transfer, then user may check on EV2 
462
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
463
+  * In this case the communication may be slower.
464
+  *
465
+  */
466
+
467
+/* Slave RECEIVER mode --------------------------*/ 
468
+/* --EV2 */
469
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
470
+/* --EV4  */
471
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
472
+
473
+/* Slave TRANSMITTER mode -----------------------*/
474
+/* --EV3 */
475
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
476
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
477
+/* --EV3_2 */
478
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
479
+
480
+/*===========================      End of Events Description           ==========================================*/
481
+
482
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
483
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
484
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
485
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
486
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
487
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
488
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
489
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
490
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
491
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
492
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
493
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
494
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
495
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
496
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
497
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
498
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
499
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
500
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
501
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
502
+/**
503
+  * @}
504
+  */
505
+
506
+/** @defgroup I2C_own_address1 
507
+  * @{
508
+  */
509
+
510
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
511
+/**
512
+  * @}
513
+  */
514
+
515
+/** @defgroup I2C_clock_speed 
516
+  * @{
517
+  */
518
+
519
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
520
+/**
521
+  * @}
522
+  */
523
+
524
+/**
525
+  * @}
526
+  */
527
+
528
+/** @defgroup I2C_Exported_Macros
529
+  * @{
530
+  */
531
+
532
+/**
533
+  * @}
534
+  */
535
+
536
+/** @defgroup I2C_Exported_Functions
537
+  * @{
538
+  */
539
+
540
+void I2C_DeInit(I2C_TypeDef* I2Cx);
541
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
542
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
543
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
544
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
547
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
548
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
549
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
550
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
551
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
552
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
553
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
554
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
555
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
556
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
557
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
558
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
559
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
560
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
561
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
562
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
563
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
564
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
565
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
566
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
567
+
568
+/**
569
+ * @brief
570
+ ****************************************************************************************
571
+ *
572
+ *                         I2C State Monitoring Functions
573
+ *                       
574
+ ****************************************************************************************   
575
+ * This I2C driver provides three different ways for I2C state monitoring
576
+ *  depending on the application requirements and constraints:
577
+ *        
578
+ *  
579
+ * 1) Basic state monitoring:
580
+ *    Using I2C_CheckEvent() function:
581
+ *    It compares the status registers (SR1 and SR2) content to a given event
582
+ *    (can be the combination of one or more flags).
583
+ *    It returns SUCCESS if the current status includes the given flags 
584
+ *    and returns ERROR if one or more flags are missing in the current status.
585
+ *    - When to use:
586
+ *      - This function is suitable for most applications as well as for startup 
587
+ *      activity since the events are fully described in the product reference manual 
588
+ *      (RM0008).
589
+ *      - It is also suitable for users who need to define their own events.
590
+ *    - Limitations:
591
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
592
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
593
+ *        hold or corrupted real state. 
594
+ *        In this case, it is advised to use error interrupts to monitor the error
595
+ *        events and handle them in the interrupt IRQ handler.
596
+ *        
597
+ *        @note 
598
+ *        For error management, it is advised to use the following functions:
599
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
600
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
601
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
602
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
603
+ *            in order to determine which error occurred.
604
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
605
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
606
+ *            and return to correct communication status.
607
+ *            
608
+ *
609
+ *  2) Advanced state monitoring:
610
+ *     Using the function I2C_GetLastEvent() which returns the image of both status 
611
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
612
+ *     by 16 bits and concatenated to Status Register 1).
613
+ *     - When to use:
614
+ *       - This function is suitable for the same applications above but it allows to
615
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).
616
+ *         The returned value could be compared to events already defined in the 
617
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.
618
+ *       - This function is suitable when multiple flags are monitored at the same time.
619
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
620
+ *         choose when an event is accepted (when all events flags are set and no 
621
+ *         other flags are set or just when the needed flags are set like 
622
+ *         I2C_CheckEvent() function).
623
+ *     - Limitations:
624
+ *       - User may need to define his own events.
625
+ *       - Same remark concerning the error management is applicable for this 
626
+ *         function if user decides to check only regular communication flags (and 
627
+ *         ignores error flags).
628
+ *     
629
+ *
630
+ *  3) Flag-based state monitoring:
631
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of 
632
+ *     one single flag (ie. I2C_FLAG_RXNE ...). 
633
+ *     - When to use:
634
+ *        - This function could be used for specific applications or in debug phase.
635
+ *        - It is suitable when only one flag checking is needed (most I2C events 
636
+ *          are monitored through multiple flags).
637
+ *     - Limitations: 
638
+ *        - When calling this function, the Status register is accessed. Some flags are
639
+ *          cleared when the status register is accessed. So checking the status
640
+ *          of one Flag, may clear other ones.
641
+ *        - Function may need to be called twice or more in order to monitor one 
642
+ *          single event.
643
+ *            
644
+ */
645
+
646
+/**
647
+ * 
648
+ *  1) Basic state monitoring
649
+ *******************************************************************************
650
+ */
651
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
652
+/**
653
+ * 
654
+ *  2) Advanced state monitoring
655
+ *******************************************************************************
656
+ */
657
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
658
+/**
659
+ * 
660
+ *  3) Flag-based state monitoring
661
+ *******************************************************************************
662
+ */
663
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
664
+/**
665
+ *
666
+ *******************************************************************************
667
+ */
668
+
669
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
670
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
671
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
672
+
673
+#ifdef __cplusplus
674
+}
675
+#endif
676
+
677
+#endif /*__STM32F10x_I2C_H */
678
+/**
679
+  * @}
680
+  */ 
681
+
682
+/**
683
+  * @}
684
+  */ 
685
+
686
+/**
687
+  * @}
688
+  */ 
689
+
690
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 146
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h View File

@@ -0,0 +1,146 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_iwdg.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the IWDG 
8
+  *          firmware library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_IWDG_H
31
+#define __STM32F10x_IWDG_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup IWDG
45
+  * @{
46
+  */
47
+
48
+/** @defgroup IWDG_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/** @defgroup IWDG_Exported_Constants
57
+  * @{
58
+  */
59
+
60
+/** @defgroup IWDG_WriteAccess
61
+  * @{
62
+  */
63
+
64
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
65
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
66
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
67
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
68
+/**
69
+  * @}
70
+  */
71
+
72
+/** @defgroup IWDG_prescaler 
73
+  * @{
74
+  */
75
+
76
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
77
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
78
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
79
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
80
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
81
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
82
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
83
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
84
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
85
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
86
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
87
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
88
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
89
+                                      ((PRESCALER) == IWDG_Prescaler_256))
90
+/**
91
+  * @}
92
+  */
93
+
94
+/** @defgroup IWDG_Flag 
95
+  * @{
96
+  */
97
+
98
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
99
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
100
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
101
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
102
+/**
103
+  * @}
104
+  */
105
+
106
+/**
107
+  * @}
108
+  */
109
+
110
+/** @defgroup IWDG_Exported_Macros
111
+  * @{
112
+  */
113
+
114
+/**
115
+  * @}
116
+  */
117
+
118
+/** @defgroup IWDG_Exported_Functions
119
+  * @{
120
+  */
121
+
122
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
123
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
124
+void IWDG_SetReload(uint16_t Reload);
125
+void IWDG_ReloadCounter(void);
126
+void IWDG_Enable(void);
127
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
128
+
129
+#ifdef __cplusplus
130
+}
131
+#endif
132
+
133
+#endif /* __STM32F10x_IWDG_H */
134
+/**
135
+  * @}
136
+  */
137
+
138
+/**
139
+  * @}
140
+  */
141
+
142
+/**
143
+  * @}
144
+  */
145
+
146
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 162
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h View File

@@ -0,0 +1,162 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_pwr.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_PWR_H
31
+#define __STM32F10x_PWR_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup PWR
45
+  * @{
46
+  */ 
47
+
48
+/** @defgroup PWR_Exported_Types
49
+  * @{
50
+  */ 
51
+
52
+/**
53
+  * @}
54
+  */ 
55
+
56
+/** @defgroup PWR_Exported_Constants
57
+  * @{
58
+  */ 
59
+
60
+/** @defgroup PVD_detection_level 
61
+  * @{
62
+  */ 
63
+
64
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
65
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
66
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
67
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
68
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
69
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
70
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
71
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
72
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
73
+                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
74
+                                 ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
75
+                                 ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
76
+/**
77
+  * @}
78
+  */
79
+
80
+/** @defgroup Regulator_state_is_STOP_mode 
81
+  * @{
82
+  */
83
+
84
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
85
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
86
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
87
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
88
+/**
89
+  * @}
90
+  */
91
+
92
+/** @defgroup STOP_mode_entry 
93
+  * @{
94
+  */
95
+
96
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
97
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
98
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
99
+ 
100
+/**
101
+  * @}
102
+  */
103
+
104
+/** @defgroup PWR_Flag 
105
+  * @{
106
+  */
107
+
108
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
109
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
110
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
111
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
112
+                               ((FLAG) == PWR_FLAG_PVDO))
113
+
114
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
115
+/**
116
+  * @}
117
+  */
118
+
119
+/**
120
+  * @}
121
+  */
122
+
123
+/** @defgroup PWR_Exported_Macros
124
+  * @{
125
+  */
126
+
127
+/**
128
+  * @}
129
+  */
130
+
131
+/** @defgroup PWR_Exported_Functions
132
+  * @{
133
+  */
134
+
135
+void PWR_DeInit(void);
136
+void PWR_BackupAccessCmd(FunctionalState NewState);
137
+void PWR_PVDCmd(FunctionalState NewState);
138
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
139
+void PWR_WakeUpPinCmd(FunctionalState NewState);
140
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
141
+void PWR_EnterSTANDBYMode(void);
142
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
143
+void PWR_ClearFlag(uint32_t PWR_FLAG);
144
+
145
+#ifdef __cplusplus
146
+}
147
+#endif
148
+
149
+#endif /* __STM32F10x_PWR_H */
150
+/**
151
+  * @}
152
+  */
153
+
154
+/**
155
+  * @}
156
+  */
157
+
158
+/**
159
+  * @}
160
+  */
161
+
162
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 733
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h View File

@@ -0,0 +1,733 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_rcc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the RCC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_RCC_H
31
+#define __STM32F10x_RCC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup RCC
45
+  * @{
46
+  */
47
+
48
+/** @defgroup RCC_Exported_Types
49
+  * @{
50
+  */
51
+
52
+typedef struct
53
+{
54
+  uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
55
+  uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
56
+  uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
57
+  uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
58
+  uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
59
+}RCC_ClocksTypeDef;
60
+
61
+/**
62
+  * @}
63
+  */
64
+
65
+/** @defgroup RCC_Exported_Constants
66
+  * @{
67
+  */
68
+
69
+/** @defgroup HSE_configuration 
70
+  * @{
71
+  */
72
+
73
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
74
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
75
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
76
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
77
+                         ((HSE) == RCC_HSE_Bypass))
78
+
79
+/**
80
+  * @}
81
+  */ 
82
+
83
+/** @defgroup PLL_entry_clock_source 
84
+  * @{
85
+  */
86
+
87
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
88
+
89
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
90
+ #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
91
+ #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
92
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
93
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
94
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))
95
+#else
96
+ #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
97
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
98
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
99
+#endif /* STM32F10X_CL */ 
100
+
101
+/**
102
+  * @}
103
+  */ 
104
+
105
+/** @defgroup PLL_multiplication_factor 
106
+  * @{
107
+  */
108
+#ifndef STM32F10X_CL
109
+ #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
110
+ #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
111
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
112
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
113
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
114
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
115
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
116
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
117
+ #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
118
+ #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
119
+ #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
120
+ #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
121
+ #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
122
+ #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
123
+ #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
124
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
125
+                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
126
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
127
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
128
+                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
129
+                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
130
+                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
131
+                              ((MUL) == RCC_PLLMul_16))
132
+
133
+#else
134
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
135
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
136
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
137
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
138
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
139
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
140
+ #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
141
+
142
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
143
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
144
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
145
+                              ((MUL) == RCC_PLLMul_6_5))
146
+#endif /* STM32F10X_CL */                              
147
+/**
148
+  * @}
149
+  */
150
+
151
+/** @defgroup PREDIV1_division_factor
152
+  * @{
153
+  */
154
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
155
+ #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
156
+ #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
157
+ #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
158
+ #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
159
+ #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
160
+ #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
161
+ #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
162
+ #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
163
+ #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
164
+ #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
165
+ #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
166
+ #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
167
+ #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
168
+ #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
169
+ #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
170
+ #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
171
+
172
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
173
+                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
174
+                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
175
+                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
176
+                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
177
+                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
178
+                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
179
+                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
180
+#endif
181
+/**
182
+  * @}
183
+  */
184
+
185
+
186
+/** @defgroup PREDIV1_clock_source
187
+  * @{
188
+  */
189
+#ifdef STM32F10X_CL
190
+/* PREDIV1 clock source (for STM32 connectivity line devices) */
191
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
192
+ #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000) 
193
+
194
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
195
+                                        ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 
196
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
197
+/* PREDIV1 clock source (for STM32 Value line devices) */
198
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
199
+
200
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 
201
+#endif
202
+/**
203
+  * @}
204
+  */
205
+
206
+#ifdef STM32F10X_CL
207
+/** @defgroup PREDIV2_division_factor
208
+  * @{
209
+  */
210
+  
211
+ #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
212
+ #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
213
+ #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
214
+ #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
215
+ #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
216
+ #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
217
+ #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
218
+ #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
219
+ #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
220
+ #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
221
+ #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
222
+ #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
223
+ #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
224
+ #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
225
+ #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
226
+ #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
227
+
228
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
229
+                                  ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
230
+                                  ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
231
+                                  ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
232
+                                  ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
233
+                                  ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
234
+                                  ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
235
+                                  ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
236
+/**
237
+  * @}
238
+  */
239
+
240
+
241
+/** @defgroup PLL2_multiplication_factor
242
+  * @{
243
+  */
244
+  
245
+ #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
246
+ #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
247
+ #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
248
+ #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
249
+ #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
250
+ #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
251
+ #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
252
+ #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
253
+ #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
254
+
255
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
256
+                               ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
257
+                               ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
258
+                               ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
259
+                               ((MUL) == RCC_PLL2Mul_20))
260
+/**
261
+  * @}
262
+  */
263
+
264
+
265
+/** @defgroup PLL3_multiplication_factor
266
+  * @{
267
+  */
268
+
269
+ #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
270
+ #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
271
+ #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
272
+ #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
273
+ #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
274
+ #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
275
+ #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
276
+ #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
277
+ #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
278
+
279
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
280
+                               ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
281
+                               ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
282
+                               ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
283
+                               ((MUL) == RCC_PLL3Mul_20))
284
+/**
285
+  * @}
286
+  */
287
+
288
+#endif /* STM32F10X_CL */
289
+
290
+
291
+/** @defgroup System_clock_source 
292
+  * @{
293
+  */
294
+
295
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
296
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
297
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
298
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
299
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
300
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
301
+/**
302
+  * @}
303
+  */
304
+
305
+/** @defgroup AHB_clock_source 
306
+  * @{
307
+  */
308
+
309
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
310
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
311
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
312
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
313
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
314
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
315
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
316
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
317
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
318
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
319
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
320
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
321
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
322
+                           ((HCLK) == RCC_SYSCLK_Div512))
323
+/**
324
+  * @}
325
+  */ 
326
+
327
+/** @defgroup APB1_APB2_clock_source 
328
+  * @{
329
+  */
330
+
331
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
332
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
333
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
334
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
335
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
336
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
337
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
338
+                           ((PCLK) == RCC_HCLK_Div16))
339
+/**
340
+  * @}
341
+  */
342
+
343
+/** @defgroup RCC_Interrupt_source 
344
+  * @{
345
+  */
346
+
347
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
348
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
349
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
350
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
351
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
352
+#define RCC_IT_CSS                       ((uint8_t)0x80)
353
+
354
+#ifndef STM32F10X_CL
355
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
356
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
357
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
358
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
359
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
360
+#else
361
+ #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
362
+ #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
363
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
364
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
365
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
366
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
367
+                            ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
368
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
369
+#endif /* STM32F10X_CL */ 
370
+
371
+
372
+/**
373
+  * @}
374
+  */
375
+
376
+#ifndef STM32F10X_CL
377
+/** @defgroup USB_Device_clock_source 
378
+  * @{
379
+  */
380
+
381
+ #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
382
+ #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
383
+
384
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
385
+                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
386
+/**
387
+  * @}
388
+  */
389
+#else
390
+/** @defgroup USB_OTG_FS_clock_source 
391
+  * @{
392
+  */
393
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
394
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
395
+
396
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
397
+                                         ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
398
+/**
399
+  * @}
400
+  */
401
+#endif /* STM32F10X_CL */ 
402
+
403
+
404
+#ifdef STM32F10X_CL
405
+/** @defgroup I2S2_clock_source 
406
+  * @{
407
+  */
408
+ #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
409
+ #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
410
+
411
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
412
+                                        ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
413
+/**
414
+  * @}
415
+  */
416
+
417
+/** @defgroup I2S3_clock_source 
418
+  * @{
419
+  */
420
+ #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
421
+ #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
422
+
423
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
424
+                                        ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))    
425
+/**
426
+  * @}
427
+  */
428
+#endif /* STM32F10X_CL */  
429
+  
430
+
431
+/** @defgroup ADC_clock_source 
432
+  * @{
433
+  */
434
+
435
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
436
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
437
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
438
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
439
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
440
+                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
441
+/**
442
+  * @}
443
+  */
444
+
445
+/** @defgroup LSE_configuration 
446
+  * @{
447
+  */
448
+
449
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
450
+#define RCC_LSE_ON                       ((uint8_t)0x01)
451
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
452
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
453
+                         ((LSE) == RCC_LSE_Bypass))
454
+/**
455
+  * @}
456
+  */
457
+
458
+/** @defgroup RTC_clock_source 
459
+  * @{
460
+  */
461
+
462
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
463
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
464
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
465
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
466
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
467
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
468
+/**
469
+  * @}
470
+  */
471
+
472
+/** @defgroup AHB_peripheral 
473
+  * @{
474
+  */
475
+
476
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
477
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
478
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
479
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
480
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
481
+
482
+#ifndef STM32F10X_CL
483
+ #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
484
+ #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
485
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
486
+#else
487
+ #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
488
+ #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
489
+ #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
490
+ #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
491
+
492
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
493
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
494
+#endif /* STM32F10X_CL */
495
+/**
496
+  * @}
497
+  */
498
+
499
+/** @defgroup APB2_peripheral 
500
+  * @{
501
+  */
502
+
503
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
504
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
505
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
506
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
507
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
508
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
509
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
510
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
511
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
512
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
513
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
514
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
515
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
516
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
517
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
518
+#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
519
+#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
520
+#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
521
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
522
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
523
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
524
+
525
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
526
+/**
527
+  * @}
528
+  */ 
529
+
530
+/** @defgroup APB1_peripheral 
531
+  * @{
532
+  */
533
+
534
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
535
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
536
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
537
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
538
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
539
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
540
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
541
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
542
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
543
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
544
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
545
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
546
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
547
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
548
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
549
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
550
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
551
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
552
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
553
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
554
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
555
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
556
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
557
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
558
+#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
559
+ 
560
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
561
+
562
+/**
563
+  * @}
564
+  */
565
+
566
+/** @defgroup Clock_source_to_output_on_MCO_pin 
567
+  * @{
568
+  */
569
+
570
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
571
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
572
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
573
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
574
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
575
+
576
+#ifndef STM32F10X_CL
577
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
578
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
579
+                          ((MCO) == RCC_MCO_PLLCLK_Div2))
580
+#else
581
+ #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
582
+ #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
583
+ #define RCC_MCO_XT1                     ((uint8_t)0x0A)
584
+ #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
585
+
586
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
587
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
588
+                          ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
589
+                          ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
590
+                          ((MCO) == RCC_MCO_PLL3CLK))
591
+#endif /* STM32F10X_CL */ 
592
+
593
+/**
594
+  * @}
595
+  */
596
+
597
+/** @defgroup RCC_Flag 
598
+  * @{
599
+  */
600
+
601
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
602
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
603
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
604
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
605
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
606
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
607
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
608
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
609
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
610
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
611
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
612
+
613
+#ifndef STM32F10X_CL
614
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
615
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
616
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
617
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
618
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
619
+                            ((FLAG) == RCC_FLAG_LPWRRST))
620
+#else
621
+ #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B) 
622
+ #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D) 
623
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
624
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
625
+                            ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
626
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
627
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
628
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
629
+                            ((FLAG) == RCC_FLAG_LPWRRST))
630
+#endif /* STM32F10X_CL */ 
631
+
632
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
633
+/**
634
+  * @}
635
+  */
636
+
637
+/**
638
+  * @}
639
+  */
640
+
641
+/** @defgroup RCC_Exported_Macros
642
+  * @{
643
+  */
644
+
645
+/**
646
+  * @}
647
+  */
648
+
649
+/** @defgroup RCC_Exported_Functions
650
+  * @{
651
+  */
652
+
653
+void RCC_DeInit(void);
654
+void RCC_HSEConfig(uint32_t RCC_HSE);
655
+ErrorStatus RCC_WaitForHSEStartUp(void);
656
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
657
+void RCC_HSICmd(FunctionalState NewState);
658
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
659
+void RCC_PLLCmd(FunctionalState NewState);
660
+
661
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
662
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
663
+#endif
664
+
665
+#ifdef  STM32F10X_CL
666
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
667
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
668
+ void RCC_PLL2Cmd(FunctionalState NewState);
669
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
670
+ void RCC_PLL3Cmd(FunctionalState NewState);
671
+#endif /* STM32F10X_CL */ 
672
+
673
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
674
+uint8_t RCC_GetSYSCLKSource(void);
675
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
676
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
677
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
678
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
679
+
680
+#ifndef STM32F10X_CL
681
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
682
+#else
683
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
684
+#endif /* STM32F10X_CL */ 
685
+
686
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
687
+
688
+#ifdef STM32F10X_CL
689
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);                                  
690
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
691
+#endif /* STM32F10X_CL */ 
692
+
693
+void RCC_LSEConfig(uint8_t RCC_LSE);
694
+void RCC_LSICmd(FunctionalState NewState);
695
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
696
+void RCC_RTCCLKCmd(FunctionalState NewState);
697
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
698
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
699
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
700
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
701
+
702
+#ifdef STM32F10X_CL
703
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
704
+#endif /* STM32F10X_CL */ 
705
+
706
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
707
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
708
+void RCC_BackupResetCmd(FunctionalState NewState);
709
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
710
+void RCC_MCOConfig(uint8_t RCC_MCO);
711
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
712
+void RCC_ClearFlag(void);
713
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
714
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
715
+
716
+#ifdef __cplusplus
717
+}
718
+#endif
719
+
720
+#endif /* __STM32F10x_RCC_H */
721
+/**
722
+  * @}
723
+  */
724
+
725
+/**
726
+  * @}
727
+  */
728
+
729
+/**
730
+  * @}
731
+  */ 
732
+
733
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 141
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h View File

@@ -0,0 +1,141 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_rtc.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_RTC_H
31
+#define __STM32F10x_RTC_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup RTC
45
+  * @{
46
+  */ 
47
+
48
+/** @defgroup RTC_Exported_Types
49
+  * @{
50
+  */ 
51
+
52
+/**
53
+  * @}
54
+  */ 
55
+
56
+/** @defgroup RTC_Exported_Constants
57
+  * @{
58
+  */
59
+
60
+/** @defgroup RTC_interrupts_define 
61
+  * @{
62
+  */
63
+
64
+#define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
65
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
66
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
67
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
68
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
69
+                           ((IT) == RTC_IT_SEC))
70
+/**
71
+  * @}
72
+  */ 
73
+
74
+/** @defgroup RTC_interrupts_flags 
75
+  * @{
76
+  */
77
+
78
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
79
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
80
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
81
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
82
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
83
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
84
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
85
+                               ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
86
+                               ((FLAG) == RTC_FLAG_SEC))
87
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
88
+
89
+/**
90
+  * @}
91
+  */
92
+
93
+/**
94
+  * @}
95
+  */
96
+
97
+/** @defgroup RTC_Exported_Macros
98
+  * @{
99
+  */
100
+
101
+/**
102
+  * @}
103
+  */
104
+
105
+/** @defgroup RTC_Exported_Functions
106
+  * @{
107
+  */
108
+
109
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
110
+void RTC_EnterConfigMode(void);
111
+void RTC_ExitConfigMode(void);
112
+uint32_t  RTC_GetCounter(void);
113
+void RTC_SetCounter(uint32_t CounterValue);
114
+void RTC_SetPrescaler(uint32_t PrescalerValue);
115
+void RTC_SetAlarm(uint32_t AlarmValue);
116
+uint32_t  RTC_GetDivider(void);
117
+void RTC_WaitForLastTask(void);
118
+void RTC_WaitForSynchro(void);
119
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
120
+void RTC_ClearFlag(uint16_t RTC_FLAG);
121
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
122
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
123
+
124
+#ifdef __cplusplus
125
+}
126
+#endif
127
+
128
+#endif /* __STM32F10x_RTC_H */
129
+/**
130
+  * @}
131
+  */
132
+
133
+/**
134
+  * @}
135
+  */
136
+
137
+/**
138
+  * @}
139
+  */
140
+
141
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 537
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h View File

@@ -0,0 +1,537 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_sdio.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_SDIO_H
31
+#define __STM32F10x_SDIO_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup SDIO
45
+  * @{
46
+  */
47
+
48
+/** @defgroup SDIO_Exported_Types
49
+  * @{
50
+  */
51
+
52
+typedef struct
53
+{
54
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
55
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
56
+
57
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
58
+                                           enabled or disabled.
59
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
60
+
61
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
62
+                                           disabled when the bus is idle.
63
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
64
+
65
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
66
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
67
+
68
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
69
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
70
+
71
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
72
+                                           This parameter can be a value between 0x00 and 0xFF. */
73
+                                           
74
+} SDIO_InitTypeDef;
75
+
76
+typedef struct
77
+{
78
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
79
+                                to a card as part of a command message. If a command
80
+                                contains an argument, it must be loaded into this register
81
+                                before writing the command to the command register */
82
+
83
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
84
+
85
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
86
+                                This parameter can be a value of @ref SDIO_Response_Type */
87
+
88
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
89
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
90
+
91
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
92
+                                is enabled or disabled.
93
+                                This parameter can be a value of @ref SDIO_CPSM_State */
94
+} SDIO_CmdInitTypeDef;
95
+
96
+typedef struct
97
+{
98
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
99
+
100
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
101
+ 
102
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
103
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
104
+ 
105
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
106
+                                     is a read or write.
107
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
108
+ 
109
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
110
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
111
+ 
112
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
113
+                                     is enabled or disabled.
114
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
115
+} SDIO_DataInitTypeDef;
116
+
117
+/**
118
+  * @}
119
+  */ 
120
+
121
+/** @defgroup SDIO_Exported_Constants
122
+  * @{
123
+  */
124
+
125
+/** @defgroup SDIO_Clock_Edge 
126
+  * @{
127
+  */
128
+
129
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
130
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
131
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
132
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
133
+/**
134
+  * @}
135
+  */
136
+
137
+/** @defgroup SDIO_Clock_Bypass 
138
+  * @{
139
+  */
140
+
141
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
142
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
143
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
144
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
145
+/**
146
+  * @}
147
+  */ 
148
+
149
+/** @defgroup SDIO_Clock_Power_Save 
150
+  * @{
151
+  */
152
+
153
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
154
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
155
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
156
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
157
+/**
158
+  * @}
159
+  */
160
+
161
+/** @defgroup SDIO_Bus_Wide 
162
+  * @{
163
+  */
164
+
165
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
166
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
167
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
168
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
169
+                                ((WIDE) == SDIO_BusWide_8b))
170
+
171
+/**
172
+  * @}
173
+  */
174
+
175
+/** @defgroup SDIO_Hardware_Flow_Control 
176
+  * @{
177
+  */
178
+
179
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
180
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
181
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
182
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
183
+/**
184
+  * @}
185
+  */
186
+
187
+/** @defgroup SDIO_Power_State 
188
+  * @{
189
+  */
190
+
191
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
192
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
193
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
194
+/**
195
+  * @}
196
+  */ 
197
+
198
+
199
+/** @defgroup SDIO_Interrupt_sources 
200
+  * @{
201
+  */
202
+
203
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
204
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
205
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
206
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
207
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
208
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
209
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
210
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
211
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
212
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
213
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
214
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
215
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
216
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
217
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
218
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
219
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
220
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
221
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
222
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
223
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
224
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
225
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
226
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
227
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
228
+/**
229
+  * @}
230
+  */ 
231
+
232
+/** @defgroup SDIO_Command_Index
233
+  * @{
234
+  */
235
+
236
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
237
+/**
238
+  * @}
239
+  */
240
+
241
+/** @defgroup SDIO_Response_Type 
242
+  * @{
243
+  */
244
+
245
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
246
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
247
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
248
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
249
+                                    ((RESPONSE) == SDIO_Response_Short) || \
250
+                                    ((RESPONSE) == SDIO_Response_Long))
251
+/**
252
+  * @}
253
+  */
254
+
255
+/** @defgroup SDIO_Wait_Interrupt_State 
256
+  * @{
257
+  */
258
+
259
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
260
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
261
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
262
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
263
+                            ((WAIT) == SDIO_Wait_Pend))
264
+/**
265
+  * @}
266
+  */
267
+
268
+/** @defgroup SDIO_CPSM_State 
269
+  * @{
270
+  */
271
+
272
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
273
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
274
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
275
+/**
276
+  * @}
277
+  */ 
278
+
279
+/** @defgroup SDIO_Response_Registers 
280
+  * @{
281
+  */
282
+
283
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
284
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
285
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
286
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
287
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
288
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
289
+/**
290
+  * @}
291
+  */
292
+
293
+/** @defgroup SDIO_Data_Length 
294
+  * @{
295
+  */
296
+
297
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
298
+/**
299
+  * @}
300
+  */
301
+
302
+/** @defgroup SDIO_Data_Block_Size 
303
+  * @{
304
+  */
305
+
306
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
307
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
308
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
309
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
310
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
311
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
312
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
313
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
314
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
315
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
316
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
317
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
318
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
319
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
320
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
321
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
322
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
323
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
324
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
325
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
326
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
327
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
328
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
329
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
330
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
331
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
332
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
333
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
334
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
335
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
336
+/**
337
+  * @}
338
+  */
339
+
340
+/** @defgroup SDIO_Transfer_Direction 
341
+  * @{
342
+  */
343
+
344
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
345
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
346
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
347
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
348
+/**
349
+  * @}
350
+  */
351
+
352
+/** @defgroup SDIO_Transfer_Type 
353
+  * @{
354
+  */
355
+
356
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
357
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
358
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
359
+                                     ((MODE) == SDIO_TransferMode_Block))
360
+/**
361
+  * @}
362
+  */
363
+
364
+/** @defgroup SDIO_DPSM_State 
365
+  * @{
366
+  */
367
+
368
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
369
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
370
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
371
+/**
372
+  * @}
373
+  */
374
+
375
+/** @defgroup SDIO_Flags 
376
+  * @{
377
+  */
378
+
379
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
380
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
381
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
382
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
383
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
384
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
385
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
386
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
387
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
388
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
389
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
390
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
391
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
392
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
393
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
394
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
395
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
396
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
397
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
398
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
399
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
400
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
401
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
402
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
403
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
404
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
405
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
406
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
407
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
408
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
409
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
410
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
411
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
412
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
413
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
414
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
415
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
416
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
417
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
418
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
419
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
420
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
421
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
422
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
423
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
424
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
425
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
426
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
427
+
428
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
429
+
430
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
431
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
432
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
433
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
434
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
435
+                            ((IT)  == SDIO_IT_RXOVERR) || \
436
+                            ((IT)  == SDIO_IT_CMDREND) || \
437
+                            ((IT)  == SDIO_IT_CMDSENT) || \
438
+                            ((IT)  == SDIO_IT_DATAEND) || \
439
+                            ((IT)  == SDIO_IT_STBITERR) || \
440
+                            ((IT)  == SDIO_IT_DBCKEND) || \
441
+                            ((IT)  == SDIO_IT_CMDACT) || \
442
+                            ((IT)  == SDIO_IT_TXACT) || \
443
+                            ((IT)  == SDIO_IT_RXACT) || \
444
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
445
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
446
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
447
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
448
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
449
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
450
+                            ((IT)  == SDIO_IT_TXDAVL) || \
451
+                            ((IT)  == SDIO_IT_RXDAVL) || \
452
+                            ((IT)  == SDIO_IT_SDIOIT) || \
453
+                            ((IT)  == SDIO_IT_CEATAEND))
454
+
455
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
456
+
457
+/**
458
+  * @}
459
+  */
460
+
461
+/** @defgroup SDIO_Read_Wait_Mode 
462
+  * @{
463
+  */
464
+
465
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
466
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
467
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
468
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
469
+/**
470
+  * @}
471
+  */
472
+
473
+/**
474
+  * @}
475
+  */
476
+
477
+/** @defgroup SDIO_Exported_Macros
478
+  * @{
479
+  */
480
+
481
+/**
482
+  * @}
483
+  */
484
+
485
+/** @defgroup SDIO_Exported_Functions
486
+  * @{
487
+  */
488
+
489
+void SDIO_DeInit(void);
490
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
491
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
492
+void SDIO_ClockCmd(FunctionalState NewState);
493
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
494
+uint32_t SDIO_GetPowerState(void);
495
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
496
+void SDIO_DMACmd(FunctionalState NewState);
497
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
498
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
499
+uint8_t SDIO_GetCommandResponse(void);
500
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
501
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
502
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
503
+uint32_t SDIO_GetDataCounter(void);
504
+uint32_t SDIO_ReadData(void);
505
+void SDIO_WriteData(uint32_t Data);
506
+uint32_t SDIO_GetFIFOCount(void);
507
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
508
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
509
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
510
+void SDIO_SetSDIOOperation(FunctionalState NewState);
511
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
512
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
513
+void SDIO_CEATAITCmd(FunctionalState NewState);
514
+void SDIO_SendCEATACmd(FunctionalState NewState);
515
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
516
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
517
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
518
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
519
+
520
+#ifdef __cplusplus
521
+}
522
+#endif
523
+
524
+#endif /* __STM32F10x_SDIO_H */
525
+/**
526
+  * @}
527
+  */
528
+
529
+/**
530
+  * @}
531
+  */
532
+
533
+/**
534
+  * @}
535
+  */
536
+
537
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 493
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h View File

@@ -0,0 +1,493 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_spi.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the SPI firmware 
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_SPI_H
31
+#define __STM32F10x_SPI_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup SPI
45
+  * @{
46
+  */ 
47
+
48
+/** @defgroup SPI_Exported_Types
49
+  * @{
50
+  */
51
+
52
+/** 
53
+  * @brief  SPI Init structure definition  
54
+  */
55
+
56
+typedef struct
57
+{
58
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
59
+                                         This parameter can be a value of @ref SPI_data_direction */
60
+
61
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
62
+                                         This parameter can be a value of @ref SPI_mode */
63
+
64
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
65
+                                         This parameter can be a value of @ref SPI_data_size */
66
+
67
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
68
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
69
+
70
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
71
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
72
+
73
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
74
+                                         hardware (NSS pin) or by software using the SSI bit.
75
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
76
+ 
77
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
78
+                                         used to configure the transmit and receive SCK clock.
79
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
80
+                                         @note The communication clock is derived from the master
81
+                                               clock. The slave clock does not need to be set. */
82
+
83
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
84
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
85
+
86
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
87
+}SPI_InitTypeDef;
88
+
89
+/** 
90
+  * @brief  I2S Init structure definition  
91
+  */
92
+
93
+typedef struct
94
+{
95
+
96
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
97
+                                  This parameter can be a value of @ref I2S_Mode */
98
+
99
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
100
+                                  This parameter can be a value of @ref I2S_Standard */
101
+
102
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
103
+                                  This parameter can be a value of @ref I2S_Data_Format */
104
+
105
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
106
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
107
+
108
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
109
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
110
+
111
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
112
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
113
+}I2S_InitTypeDef;
114
+
115
+/**
116
+  * @}
117
+  */
118
+
119
+/** @defgroup SPI_Exported_Constants
120
+  * @{
121
+  */
122
+
123
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
124
+                                   ((PERIPH) == SPI2) || \
125
+                                   ((PERIPH) == SPI3))
126
+
127
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
128
+                                  ((PERIPH) == SPI3))
129
+
130
+/** @defgroup SPI_data_direction 
131
+  * @{
132
+  */
133
+  
134
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
135
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
136
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
137
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
138
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
139
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
140
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
141
+                                     ((MODE) == SPI_Direction_1Line_Tx))
142
+/**
143
+  * @}
144
+  */
145
+
146
+/** @defgroup SPI_mode 
147
+  * @{
148
+  */
149
+
150
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
151
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
152
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
153
+                           ((MODE) == SPI_Mode_Slave))
154
+/**
155
+  * @}
156
+  */
157
+
158
+/** @defgroup SPI_data_size 
159
+  * @{
160
+  */
161
+
162
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
163
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
164
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
165
+                                   ((DATASIZE) == SPI_DataSize_8b))
166
+/**
167
+  * @}
168
+  */ 
169
+
170
+/** @defgroup SPI_Clock_Polarity 
171
+  * @{
172
+  */
173
+
174
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
175
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
176
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
177
+                           ((CPOL) == SPI_CPOL_High))
178
+/**
179
+  * @}
180
+  */
181
+
182
+/** @defgroup SPI_Clock_Phase 
183
+  * @{
184
+  */
185
+
186
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
187
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
188
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
189
+                           ((CPHA) == SPI_CPHA_2Edge))
190
+/**
191
+  * @}
192
+  */
193
+
194
+/** @defgroup SPI_Slave_Select_management 
195
+  * @{
196
+  */
197
+
198
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
199
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
200
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
201
+                         ((NSS) == SPI_NSS_Hard))
202
+/**
203
+  * @}
204
+  */ 
205
+
206
+/** @defgroup SPI_BaudRate_Prescaler 
207
+  * @{
208
+  */
209
+
210
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
211
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
212
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
213
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
214
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
215
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
216
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
217
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
218
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
219
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
220
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
221
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
222
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
223
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
224
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
225
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
226
+/**
227
+  * @}
228
+  */ 
229
+
230
+/** @defgroup SPI_MSB_LSB_transmission 
231
+  * @{
232
+  */
233
+
234
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
235
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
236
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
237
+                               ((BIT) == SPI_FirstBit_LSB))
238
+/**
239
+  * @}
240
+  */
241
+
242
+/** @defgroup I2S_Mode 
243
+  * @{
244
+  */
245
+
246
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
247
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
248
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
249
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
250
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
251
+                           ((MODE) == I2S_Mode_SlaveRx) || \
252
+                           ((MODE) == I2S_Mode_MasterTx) || \
253
+                           ((MODE) == I2S_Mode_MasterRx) )
254
+/**
255
+  * @}
256
+  */
257
+
258
+/** @defgroup I2S_Standard 
259
+  * @{
260
+  */
261
+
262
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
263
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
264
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
265
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
266
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
267
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
268
+                                   ((STANDARD) == I2S_Standard_MSB) || \
269
+                                   ((STANDARD) == I2S_Standard_LSB) || \
270
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
271
+                                   ((STANDARD) == I2S_Standard_PCMLong))
272
+/**
273
+  * @}
274
+  */
275
+
276
+/** @defgroup I2S_Data_Format 
277
+  * @{
278
+  */
279
+
280
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
281
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
282
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
283
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
284
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
285
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
286
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
287
+                                    ((FORMAT) == I2S_DataFormat_32b))
288
+/**
289
+  * @}
290
+  */ 
291
+
292
+/** @defgroup I2S_MCLK_Output 
293
+  * @{
294
+  */
295
+
296
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
297
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
298
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
299
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
300
+/**
301
+  * @}
302
+  */
303
+
304
+/** @defgroup I2S_Audio_Frequency 
305
+  * @{
306
+  */
307
+
308
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
309
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
310
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
311
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
312
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
313
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
314
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
315
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
316
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
317
+#define I2S_AudioFreq_Default            ((uint32_t)2)
318
+
319
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
320
+                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
321
+                                 ((FREQ) == I2S_AudioFreq_Default))
322
+/**
323
+  * @}
324
+  */ 
325
+
326
+/** @defgroup I2S_Clock_Polarity 
327
+  * @{
328
+  */
329
+
330
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
331
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
332
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
333
+                           ((CPOL) == I2S_CPOL_High))
334
+/**
335
+  * @}
336
+  */
337
+
338
+/** @defgroup SPI_I2S_DMA_transfer_requests 
339
+  * @{
340
+  */
341
+
342
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
343
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
344
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
345
+/**
346
+  * @}
347
+  */
348
+
349
+/** @defgroup SPI_NSS_internal_software_management 
350
+  * @{
351
+  */
352
+
353
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
354
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
355
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
356
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
357
+/**
358
+  * @}
359
+  */
360
+
361
+/** @defgroup SPI_CRC_Transmit_Receive 
362
+  * @{
363
+  */
364
+
365
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
366
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
367
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
368
+/**
369
+  * @}
370
+  */
371
+
372
+/** @defgroup SPI_direction_transmit_receive 
373
+  * @{
374
+  */
375
+
376
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
377
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
378
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
379
+                                     ((DIRECTION) == SPI_Direction_Tx))
380
+/**
381
+  * @}
382
+  */
383
+
384
+/** @defgroup SPI_I2S_interrupts_definition 
385
+  * @{
386
+  */
387
+
388
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
389
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
390
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
391
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
392
+                                 ((IT) == SPI_I2S_IT_RXNE) || \
393
+                                 ((IT) == SPI_I2S_IT_ERR))
394
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
395
+#define SPI_IT_MODF                     ((uint8_t)0x55)
396
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
397
+#define I2S_IT_UDR                      ((uint8_t)0x53)
398
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
399
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
400
+                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
401
+                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
402
+/**
403
+  * @}
404
+  */
405
+
406
+/** @defgroup SPI_I2S_flags_definition 
407
+  * @{
408
+  */
409
+
410
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
411
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
412
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
413
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
414
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
415
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
416
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
417
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
418
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
419
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
420
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
421
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
422
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
423
+/**
424
+  * @}
425
+  */
426
+
427
+/** @defgroup SPI_CRC_polynomial 
428
+  * @{
429
+  */
430
+
431
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
432
+/**
433
+  * @}
434
+  */
435
+
436
+/**
437
+  * @}
438
+  */
439
+
440
+/** @defgroup SPI_Exported_Macros
441
+  * @{
442
+  */
443
+
444
+/**
445
+  * @}
446
+  */
447
+
448
+/** @defgroup SPI_Exported_Functions
449
+  * @{
450
+  */
451
+
452
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
453
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
454
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
455
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
456
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
457
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
458
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
459
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
460
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
461
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
462
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
463
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
464
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
465
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
466
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
467
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
468
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
469
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
470
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
471
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
472
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
473
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
474
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
475
+
476
+#ifdef __cplusplus
477
+}
478
+#endif
479
+
480
+#endif /*__STM32F10x_SPI_H */
481
+/**
482
+  * @}
483
+  */
484
+
485
+/**
486
+  * @}
487
+  */
488
+
489
+/**
490
+  * @}
491
+  */
492
+
493
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1170
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
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+ 429
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h View File

@@ -0,0 +1,429 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_usart.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the USART 
8
+  *          firmware library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_USART_H
31
+#define __STM32F10x_USART_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup USART
45
+  * @{
46
+  */ 
47
+
48
+/** @defgroup USART_Exported_Types
49
+  * @{
50
+  */ 
51
+
52
+/** 
53
+  * @brief  USART Init Structure definition  
54
+  */ 
55
+  
56
+typedef struct
57
+{
58
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
59
+                                           The baud rate is computed using the following formula:
60
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
61
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
62
+
63
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
64
+                                           This parameter can be a value of @ref USART_Word_Length */
65
+
66
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
67
+                                           This parameter can be a value of @ref USART_Stop_Bits */
68
+
69
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
70
+                                           This parameter can be a value of @ref USART_Parity
71
+                                           @note When parity is enabled, the computed parity is inserted
72
+                                                 at the MSB position of the transmitted data (9th bit when
73
+                                                 the word length is set to 9 data bits; 8th bit when the
74
+                                                 word length is set to 8 data bits). */
75
+ 
76
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
77
+                                           This parameter can be a value of @ref USART_Mode */
78
+
79
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
80
+                                           or disabled.
81
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
82
+} USART_InitTypeDef;
83
+
84
+/** 
85
+  * @brief  USART Clock Init Structure definition  
86
+  */ 
87
+  
88
+typedef struct
89
+{
90
+
91
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
92
+                               This parameter can be a value of @ref USART_Clock */
93
+
94
+  uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.
95
+                               This parameter can be a value of @ref USART_Clock_Polarity */
96
+
97
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
98
+                               This parameter can be a value of @ref USART_Clock_Phase */
99
+
100
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
101
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
102
+                               This parameter can be a value of @ref USART_Last_Bit */
103
+} USART_ClockInitTypeDef;
104
+
105
+/**
106
+  * @}
107
+  */ 
108
+
109
+/** @defgroup USART_Exported_Constants
110
+  * @{
111
+  */ 
112
+  
113
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
114
+                                     ((PERIPH) == USART2) || \
115
+                                     ((PERIPH) == USART3) || \
116
+                                     ((PERIPH) == UART4) || \
117
+                                     ((PERIPH) == UART5))
118
+
119
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
120
+                                     ((PERIPH) == USART2) || \
121
+                                     ((PERIPH) == USART3))
122
+
123
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
124
+                                      ((PERIPH) == USART2) || \
125
+                                      ((PERIPH) == USART3) || \
126
+                                      ((PERIPH) == UART4))
127
+/** @defgroup USART_Word_Length 
128
+  * @{
129
+  */ 
130
+  
131
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
132
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
133
+                                    
134
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
135
+                                      ((LENGTH) == USART_WordLength_9b))
136
+/**
137
+  * @}
138
+  */ 
139
+
140
+/** @defgroup USART_Stop_Bits 
141
+  * @{
142
+  */ 
143
+  
144
+#define USART_StopBits_1                     ((uint16_t)0x0000)
145
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
146
+#define USART_StopBits_2                     ((uint16_t)0x2000)
147
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
148
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
149
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
150
+                                     ((STOPBITS) == USART_StopBits_2) || \
151
+                                     ((STOPBITS) == USART_StopBits_1_5))
152
+/**
153
+  * @}
154
+  */ 
155
+
156
+/** @defgroup USART_Parity 
157
+  * @{
158
+  */ 
159
+  
160
+#define USART_Parity_No                      ((uint16_t)0x0000)
161
+#define USART_Parity_Even                    ((uint16_t)0x0400)
162
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
163
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
164
+                                 ((PARITY) == USART_Parity_Even) || \
165
+                                 ((PARITY) == USART_Parity_Odd))
166
+/**
167
+  * @}
168
+  */ 
169
+
170
+/** @defgroup USART_Mode 
171
+  * @{
172
+  */ 
173
+  
174
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
175
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
176
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
177
+/**
178
+  * @}
179
+  */ 
180
+
181
+/** @defgroup USART_Hardware_Flow_Control 
182
+  * @{
183
+  */ 
184
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
185
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
186
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
187
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
188
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
189
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
190
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
191
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
192
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
193
+/**
194
+  * @}
195
+  */ 
196
+
197
+/** @defgroup USART_Clock 
198
+  * @{
199
+  */ 
200
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
201
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
202
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
203
+                               ((CLOCK) == USART_Clock_Enable))
204
+/**
205
+  * @}
206
+  */ 
207
+
208
+/** @defgroup USART_Clock_Polarity 
209
+  * @{
210
+  */
211
+  
212
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
213
+#define USART_CPOL_High                      ((uint16_t)0x0400)
214
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
215
+
216
+/**
217
+  * @}
218
+  */ 
219
+
220
+/** @defgroup USART_Clock_Phase
221
+  * @{
222
+  */
223
+
224
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
225
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
226
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
227
+
228
+/**
229
+  * @}
230
+  */
231
+
232
+/** @defgroup USART_Last_Bit
233
+  * @{
234
+  */
235
+
236
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
237
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
238
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
239
+                                   ((LASTBIT) == USART_LastBit_Enable))
240
+/**
241
+  * @}
242
+  */ 
243
+
244
+/** @defgroup USART_Interrupt_definition 
245
+  * @{
246
+  */
247
+  
248
+#define USART_IT_PE                          ((uint16_t)0x0028)
249
+#define USART_IT_TXE                         ((uint16_t)0x0727)
250
+#define USART_IT_TC                          ((uint16_t)0x0626)
251
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
252
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
253
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
254
+#define USART_IT_LBD                         ((uint16_t)0x0846)
255
+#define USART_IT_CTS                         ((uint16_t)0x096A)
256
+#define USART_IT_ERR                         ((uint16_t)0x0060)
257
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
258
+#define USART_IT_NE                          ((uint16_t)0x0260)
259
+#define USART_IT_FE                          ((uint16_t)0x0160)
260
+
261
+/** @defgroup USART_Legacy 
262
+  * @{
263
+  */
264
+#define USART_IT_ORE                          USART_IT_ORE_ER               
265
+/**
266
+  * @}
267
+  */
268
+  
269
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
270
+                               ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
271
+                               ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
272
+                               ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
273
+
274
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
275
+                            ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
276
+                            ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
277
+                            ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
278
+                            ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
279
+                            ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
280
+
281
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
282
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
283
+/**
284
+  * @}
285
+  */
286
+
287
+/** @defgroup USART_DMA_Requests 
288
+  * @{
289
+  */
290
+
291
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
292
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
293
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
294
+
295
+/**
296
+  * @}
297
+  */ 
298
+
299
+/** @defgroup USART_WakeUp_methods
300
+  * @{
301
+  */
302
+
303
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
304
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
305
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
306
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
307
+/**
308
+  * @}
309
+  */
310
+
311
+/** @defgroup USART_LIN_Break_Detection_Length 
312
+  * @{
313
+  */
314
+  
315
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
316
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
317
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
318
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
319
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
320
+/**
321
+  * @}
322
+  */
323
+
324
+/** @defgroup USART_IrDA_Low_Power 
325
+  * @{
326
+  */
327
+
328
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
329
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
330
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
331
+                                  ((MODE) == USART_IrDAMode_Normal))
332
+/**
333
+  * @}
334
+  */ 
335
+
336
+/** @defgroup USART_Flags 
337
+  * @{
338
+  */
339
+
340
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
341
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
342
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
343
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
344
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
345
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
346
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
347
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
348
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
349
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
350
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
351
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
352
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
353
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
354
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
355
+                              
356
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
357
+
358
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
359
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
360
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
361
+
362
+/**
363
+  * @}
364
+  */ 
365
+
366
+/**
367
+  * @}
368
+  */ 
369
+
370
+/** @defgroup USART_Exported_Macros
371
+  * @{
372
+  */ 
373
+
374
+/**
375
+  * @}
376
+  */ 
377
+
378
+/** @defgroup USART_Exported_Functions
379
+  * @{
380
+  */
381
+
382
+void USART_DeInit(USART_TypeDef* USARTx);
383
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
384
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
385
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
386
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
387
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
388
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
389
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
390
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
391
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
392
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
393
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
394
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
395
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
396
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
397
+void USART_SendBreak(USART_TypeDef* USARTx);
398
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
399
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
400
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
401
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
402
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
403
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
404
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
405
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
406
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
407
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
408
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
409
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
410
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
411
+
412
+#ifdef __cplusplus
413
+}
414
+#endif
415
+
416
+#endif /* __STM32F10x_USART_H */
417
+/**
418
+  * @}
419
+  */ 
420
+
421
+/**
422
+  * @}
423
+  */ 
424
+
425
+/**
426
+  * @}
427
+  */ 
428
+
429
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 121
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h View File

@@ -0,0 +1,121 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_wwdg.h
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
8
+  *          library.
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Define to prevent recursive inclusion -------------------------------------*/
30
+#ifndef __STM32F10x_WWDG_H
31
+#define __STM32F10x_WWDG_H
32
+
33
+#ifdef __cplusplus
34
+ extern "C" {
35
+#endif
36
+
37
+/* Includes ------------------------------------------------------------------*/
38
+#include "stm32f10x.h"
39
+
40
+/** @addtogroup STM32F10x_StdPeriph_Driver
41
+  * @{
42
+  */
43
+
44
+/** @addtogroup WWDG
45
+  * @{
46
+  */ 
47
+
48
+/** @defgroup WWDG_Exported_Types
49
+  * @{
50
+  */ 
51
+  
52
+/**
53
+  * @}
54
+  */ 
55
+
56
+/** @defgroup WWDG_Exported_Constants
57
+  * @{
58
+  */ 
59
+  
60
+/** @defgroup WWDG_Prescaler 
61
+  * @{
62
+  */ 
63
+  
64
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
65
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
66
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
67
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
68
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
69
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
70
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
71
+                                      ((PRESCALER) == WWDG_Prescaler_8))
72
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
73
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
74
+
75
+/**
76
+  * @}
77
+  */ 
78
+
79
+/**
80
+  * @}
81
+  */ 
82
+
83
+/** @defgroup WWDG_Exported_Macros
84
+  * @{
85
+  */ 
86
+/**
87
+  * @}
88
+  */ 
89
+
90
+/** @defgroup WWDG_Exported_Functions
91
+  * @{
92
+  */ 
93
+  
94
+void WWDG_DeInit(void);
95
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
96
+void WWDG_SetWindowValue(uint8_t WindowValue);
97
+void WWDG_EnableIT(void);
98
+void WWDG_SetCounter(uint8_t Counter);
99
+void WWDG_Enable(uint8_t Counter);
100
+FlagStatus WWDG_GetFlagStatus(void);
101
+void WWDG_ClearFlag(void);
102
+
103
+#ifdef __cplusplus
104
+}
105
+#endif
106
+
107
+#endif /* __STM32F10x_WWDG_H */
108
+
109
+/**
110
+  * @}
111
+  */ 
112
+
113
+/**
114
+  * @}
115
+  */ 
116
+
117
+/**
118
+  * @}
119
+  */ 
120
+
121
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 231
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c View File

@@ -0,0 +1,231 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    misc.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
8
+  *          to CMSIS functions).
9
+  ******************************************************************************
10
+  * @attention
11
+  *
12
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
13
+  *
14
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+  * You may not use this file except in compliance with the License.
16
+  * You may obtain a copy of the License at:
17
+  *
18
+  *        http://www.st.com/software_license_agreement_liberty_v2
19
+  *
20
+  * Unless required by applicable law or agreed to in writing, software 
21
+  * distributed under the License is distributed on an "AS IS" BASIS, 
22
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+  * See the License for the specific language governing permissions and
24
+  * limitations under the License.
25
+  *
26
+  ******************************************************************************
27
+  */
28
+
29
+/* Includes ------------------------------------------------------------------*/
30
+#include "misc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup MISC 
37
+  * @brief MISC driver modules
38
+  * @{
39
+  */
40
+
41
+/** @defgroup MISC_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */ 
48
+
49
+/** @defgroup MISC_Private_Defines
50
+  * @{
51
+  */
52
+
53
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
54
+/**
55
+  * @}
56
+  */
57
+
58
+/** @defgroup MISC_Private_Macros
59
+  * @{
60
+  */
61
+
62
+/**
63
+  * @}
64
+  */
65
+
66
+/** @defgroup MISC_Private_Variables
67
+  * @{
68
+  */
69
+
70
+/**
71
+  * @}
72
+  */
73
+
74
+/** @defgroup MISC_Private_FunctionPrototypes
75
+  * @{
76
+  */
77
+
78
+/**
79
+  * @}
80
+  */
81
+
82
+/** @defgroup MISC_Private_Functions
83
+  * @{
84
+  */
85
+
86
+/**
87
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
88
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
89
+  *   This parameter can be one of the following values:
90
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
91
+  *                                4 bits for subpriority
92
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
93
+  *                                3 bits for subpriority
94
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
95
+  *                                2 bits for subpriority
96
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
97
+  *                                1 bits for subpriority
98
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
99
+  *                                0 bits for subpriority
100
+  * @retval None
101
+  */
102
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
103
+{
104
+  /* Check the parameters */
105
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
106
+  
107
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
108
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
109
+}
110
+
111
+/**
112
+  * @brief  Initializes the NVIC peripheral according to the specified
113
+  *         parameters in the NVIC_InitStruct.
114
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
115
+  *         the configuration information for the specified NVIC peripheral.
116
+  * @retval None
117
+  */
118
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
119
+{
120
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
121
+  
122
+  /* Check the parameters */
123
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
124
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
125
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
126
+    
127
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
128
+  {
129
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
130
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
131
+    tmppre = (0x4 - tmppriority);
132
+    tmpsub = tmpsub >> tmppriority;
133
+
134
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
135
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
136
+    tmppriority = tmppriority << 0x04;
137
+        
138
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
139
+    
140
+    /* Enable the Selected IRQ Channels --------------------------------------*/
141
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143
+  }
144
+  else
145
+  {
146
+    /* Disable the Selected IRQ Channels -------------------------------------*/
147
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
148
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
149
+  }
150
+}
151
+
152
+/**
153
+  * @brief  Sets the vector table location and Offset.
154
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
155
+  *   This parameter can be one of the following values:
156
+  *     @arg NVIC_VectTab_RAM
157
+  *     @arg NVIC_VectTab_FLASH
158
+  * @param  Offset: Vector Table base offset field. This value must be a multiple 
159
+  *         of 0x200.
160
+  * @retval None
161
+  */
162
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
163
+{ 
164
+  /* Check the parameters */
165
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
166
+  assert_param(IS_NVIC_OFFSET(Offset));  
167
+   
168
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
169
+}
170
+
171
+/**
172
+  * @brief  Selects the condition for the system to enter low power mode.
173
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
174
+  *   This parameter can be one of the following values:
175
+  *     @arg NVIC_LP_SEVONPEND
176
+  *     @arg NVIC_LP_SLEEPDEEP
177
+  *     @arg NVIC_LP_SLEEPONEXIT
178
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
179
+  * @retval None
180
+  */
181
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
182
+{
183
+  /* Check the parameters */
184
+  assert_param(IS_NVIC_LP(LowPowerMode));
185
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
186
+  
187
+  if (NewState != DISABLE)
188
+  {
189
+    SCB->SCR |= LowPowerMode;
190
+  }
191
+  else
192
+  {
193
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
194
+  }
195
+}
196
+
197
+/**
198
+  * @brief  Configures the SysTick clock source.
199
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
200
+  *   This parameter can be one of the following values:
201
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
202
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
203
+  * @retval None
204
+  */
205
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
206
+{
207
+  /* Check the parameters */
208
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
209
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
210
+  {
211
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
212
+  }
213
+  else
214
+  {
215
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
216
+  }
217
+}
218
+
219
+/**
220
+  * @}
221
+  */
222
+
223
+/**
224
+  * @}
225
+  */
226
+
227
+/**
228
+  * @}
229
+  */
230
+
231
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1313
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
File diff suppressed because it is too large
View File


+ 314
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c View File

@@ -0,0 +1,314 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_bkp.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the BKP firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_bkp.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup BKP 
37
+  * @brief BKP driver modules
38
+  * @{
39
+  */
40
+
41
+/** @defgroup BKP_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+/** @defgroup BKP_Private_Defines
50
+  * @{
51
+  */
52
+
53
+/* ------------ BKP registers bit address in the alias region --------------- */
54
+#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
55
+
56
+/* --- CR Register ----*/
57
+
58
+/* Alias word address of TPAL bit */
59
+#define CR_OFFSET         (BKP_OFFSET + 0x30)
60
+#define TPAL_BitNumber    0x01
61
+#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
62
+
63
+/* Alias word address of TPE bit */
64
+#define TPE_BitNumber     0x00
65
+#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
66
+
67
+/* --- CSR Register ---*/
68
+
69
+/* Alias word address of TPIE bit */
70
+#define CSR_OFFSET        (BKP_OFFSET + 0x34)
71
+#define TPIE_BitNumber    0x02
72
+#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
73
+
74
+/* Alias word address of TIF bit */
75
+#define TIF_BitNumber     0x09
76
+#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
77
+
78
+/* Alias word address of TEF bit */
79
+#define TEF_BitNumber     0x08
80
+#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
81
+
82
+/* ---------------------- BKP registers bit mask ------------------------ */
83
+
84
+/* RTCCR register bit mask */
85
+#define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
86
+#define RTCCR_MASK        ((uint16_t)0xFC7F)
87
+
88
+/**
89
+  * @}
90
+  */ 
91
+
92
+
93
+/** @defgroup BKP_Private_Macros
94
+  * @{
95
+  */
96
+
97
+/**
98
+  * @}
99
+  */
100
+
101
+/** @defgroup BKP_Private_Variables
102
+  * @{
103
+  */
104
+
105
+/**
106
+  * @}
107
+  */
108
+
109
+/** @defgroup BKP_Private_FunctionPrototypes
110
+  * @{
111
+  */
112
+
113
+/**
114
+  * @}
115
+  */
116
+
117
+/** @defgroup BKP_Private_Functions
118
+  * @{
119
+  */
120
+
121
+/**
122
+  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
123
+  * @param  None
124
+  * @retval None
125
+  */
126
+void BKP_DeInit(void)
127
+{
128
+  RCC_BackupResetCmd(ENABLE);
129
+  RCC_BackupResetCmd(DISABLE);
130
+}
131
+
132
+/**
133
+  * @brief  Configures the Tamper Pin active level.
134
+  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
135
+  *   This parameter can be one of the following values:
136
+  *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
137
+  *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
138
+  * @retval None
139
+  */
140
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
141
+{
142
+  /* Check the parameters */
143
+  assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
144
+  *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
145
+}
146
+
147
+/**
148
+  * @brief  Enables or disables the Tamper Pin activation.
149
+  * @param  NewState: new state of the Tamper Pin activation.
150
+  *   This parameter can be: ENABLE or DISABLE.
151
+  * @retval None
152
+  */
153
+void BKP_TamperPinCmd(FunctionalState NewState)
154
+{
155
+  /* Check the parameters */
156
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
157
+  *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
158
+}
159
+
160
+/**
161
+  * @brief  Enables or disables the Tamper Pin Interrupt.
162
+  * @param  NewState: new state of the Tamper Pin Interrupt.
163
+  *   This parameter can be: ENABLE or DISABLE.
164
+  * @retval None
165
+  */
166
+void BKP_ITConfig(FunctionalState NewState)
167
+{
168
+  /* Check the parameters */
169
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
170
+  *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
171
+}
172
+
173
+/**
174
+  * @brief  Select the RTC output source to output on the Tamper pin.
175
+  * @param  BKP_RTCOutputSource: specifies the RTC output source.
176
+  *   This parameter can be one of the following values:
177
+  *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
178
+  *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
179
+  *                                          divided by 64 on the Tamper pin.
180
+  *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
181
+  *                                     the Tamper pin.
182
+  *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
183
+  *                                      the Tamper pin.  
184
+  * @retval None
185
+  */
186
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
187
+{
188
+  uint16_t tmpreg = 0;
189
+  /* Check the parameters */
190
+  assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
191
+  tmpreg = BKP->RTCCR;
192
+  /* Clear CCO, ASOE and ASOS bits */
193
+  tmpreg &= RTCCR_MASK;
194
+  
195
+  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
196
+  tmpreg |= BKP_RTCOutputSource;
197
+  /* Store the new value */
198
+  BKP->RTCCR = tmpreg;
199
+}
200
+
201
+/**
202
+  * @brief  Sets RTC Clock Calibration value.
203
+  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
204
+  *   This parameter must be a number between 0 and 0x7F.
205
+  * @retval None
206
+  */
207
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
208
+{
209
+  uint16_t tmpreg = 0;
210
+  /* Check the parameters */
211
+  assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
212
+  tmpreg = BKP->RTCCR;
213
+  /* Clear CAL[6:0] bits */
214
+  tmpreg &= RTCCR_CAL_MASK;
215
+  /* Set CAL[6:0] bits according to CalibrationValue value */
216
+  tmpreg |= CalibrationValue;
217
+  /* Store the new value */
218
+  BKP->RTCCR = tmpreg;
219
+}
220
+
221
+/**
222
+  * @brief  Writes user data to the specified Data Backup Register.
223
+  * @param  BKP_DR: specifies the Data Backup Register.
224
+  *   This parameter can be BKP_DRx where x:[1, 42]
225
+  * @param  Data: data to write
226
+  * @retval None
227
+  */
228
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
229
+{
230
+  __IO uint32_t tmp = 0;
231
+
232
+  /* Check the parameters */
233
+  assert_param(IS_BKP_DR(BKP_DR));
234
+
235
+  tmp = (uint32_t)BKP_BASE; 
236
+  tmp += BKP_DR;
237
+
238
+  *(__IO uint32_t *) tmp = Data;
239
+}
240
+
241
+/**
242
+  * @brief  Reads data from the specified Data Backup Register.
243
+  * @param  BKP_DR: specifies the Data Backup Register.
244
+  *   This parameter can be BKP_DRx where x:[1, 42]
245
+  * @retval The content of the specified Data Backup Register
246
+  */
247
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
248
+{
249
+  __IO uint32_t tmp = 0;
250
+
251
+  /* Check the parameters */
252
+  assert_param(IS_BKP_DR(BKP_DR));
253
+
254
+  tmp = (uint32_t)BKP_BASE; 
255
+  tmp += BKP_DR;
256
+
257
+  return (*(__IO uint16_t *) tmp);
258
+}
259
+
260
+/**
261
+  * @brief  Checks whether the Tamper Pin Event flag is set or not.
262
+  * @param  None
263
+  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
264
+  */
265
+FlagStatus BKP_GetFlagStatus(void)
266
+{
267
+  return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
268
+}
269
+
270
+/**
271
+  * @brief  Clears Tamper Pin Event pending flag.
272
+  * @param  None
273
+  * @retval None
274
+  */
275
+void BKP_ClearFlag(void)
276
+{
277
+  /* Set CTE bit to clear Tamper Pin Event flag */
278
+  BKP->CSR |= BKP_CSR_CTE;
279
+}
280
+
281
+/**
282
+  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
283
+  * @param  None
284
+  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
285
+  */
286
+ITStatus BKP_GetITStatus(void)
287
+{
288
+  return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
289
+}
290
+
291
+/**
292
+  * @brief  Clears Tamper Pin Interrupt pending bit.
293
+  * @param  None
294
+  * @retval None
295
+  */
296
+void BKP_ClearITPendingBit(void)
297
+{
298
+  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
299
+  BKP->CSR |= BKP_CSR_CTI;
300
+}
301
+
302
+/**
303
+  * @}
304
+  */
305
+
306
+/**
307
+  * @}
308
+  */
309
+
310
+/**
311
+  * @}
312
+  */
313
+
314
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1421
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
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+ 439
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c View File

@@ -0,0 +1,439 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_cec.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the CEC firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_cec.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup CEC 
37
+  * @brief CEC driver modules
38
+  * @{
39
+  */
40
+
41
+/** @defgroup CEC_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+
50
+/** @defgroup CEC_Private_Defines
51
+  * @{
52
+  */ 
53
+
54
+/* ------------ CEC registers bit address in the alias region ----------- */
55
+#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
56
+
57
+/* --- CFGR Register ---*/
58
+
59
+/* Alias word address of PE bit */
60
+#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
61
+#define PE_BitNumber                0x00
62
+#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
63
+
64
+/* Alias word address of IE bit */
65
+#define IE_BitNumber                0x01
66
+#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
67
+
68
+/* --- CSR Register ---*/
69
+
70
+/* Alias word address of TSOM bit */
71
+#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
72
+#define TSOM_BitNumber              0x00
73
+#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
74
+
75
+/* Alias word address of TEOM bit */
76
+#define TEOM_BitNumber              0x01
77
+#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
78
+  
79
+#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
80
+#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
81
+ 
82
+/**
83
+  * @}
84
+  */ 
85
+
86
+
87
+/** @defgroup CEC_Private_Macros
88
+  * @{
89
+  */ 
90
+
91
+/**
92
+  * @}
93
+  */ 
94
+
95
+
96
+/** @defgroup CEC_Private_Variables
97
+  * @{
98
+  */ 
99
+
100
+/**
101
+  * @}
102
+  */ 
103
+
104
+
105
+/** @defgroup CEC_Private_FunctionPrototypes
106
+  * @{
107
+  */
108
+ 
109
+/**
110
+  * @}
111
+  */ 
112
+
113
+
114
+/** @defgroup CEC_Private_Functions
115
+  * @{
116
+  */ 
117
+
118
+/**
119
+  * @brief  Deinitializes the CEC peripheral registers to their default reset 
120
+  *         values.
121
+  * @param  None
122
+  * @retval None
123
+  */
124
+void CEC_DeInit(void)
125
+{
126
+  /* Enable CEC reset state */
127
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
128
+  /* Release CEC from reset state */
129
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
130
+}
131
+
132
+
133
+/**
134
+  * @brief  Initializes the CEC peripheral according to the specified 
135
+  *         parameters in the CEC_InitStruct.
136
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
137
+  *         contains the configuration information for the specified
138
+  *         CEC peripheral.
139
+  * @retval None
140
+  */
141
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
142
+{
143
+  uint16_t tmpreg = 0;
144
+ 
145
+  /* Check the parameters */
146
+  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
147
+  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
148
+     
149
+  /*---------------------------- CEC CFGR Configuration -----------------*/
150
+  /* Get the CEC CFGR value */
151
+  tmpreg = CEC->CFGR;
152
+  
153
+  /* Clear BTEM and BPEM bits */
154
+  tmpreg &= CFGR_CLEAR_Mask;
155
+  
156
+  /* Configure CEC: Bit Timing Error and Bit Period Error */
157
+  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
158
+
159
+  /* Write to CEC CFGR  register*/
160
+  CEC->CFGR = tmpreg;
161
+  
162
+}
163
+
164
+/**
165
+  * @brief  Enables or disables the specified CEC peripheral.
166
+  * @param  NewState: new state of the CEC peripheral. 
167
+  *     This parameter can be: ENABLE or DISABLE.
168
+  * @retval None
169
+  */
170
+void CEC_Cmd(FunctionalState NewState)
171
+{
172
+  /* Check the parameters */
173
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
174
+
175
+  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
176
+
177
+  if(NewState == DISABLE)
178
+  {
179
+    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
180
+    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
181
+    {
182
+    }  
183
+  }  
184
+}
185
+
186
+/**
187
+  * @brief  Enables or disables the CEC interrupt.
188
+  * @param  NewState: new state of the CEC interrupt.
189
+  *   This parameter can be: ENABLE or DISABLE.
190
+  * @retval None
191
+  */
192
+void CEC_ITConfig(FunctionalState NewState)
193
+{
194
+  /* Check the parameters */
195
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
196
+
197
+  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
198
+}
199
+
200
+/**
201
+  * @brief  Defines the Own Address of the CEC device.
202
+  * @param  CEC_OwnAddress: The CEC own address
203
+  * @retval None
204
+  */
205
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
206
+{
207
+  /* Check the parameters */
208
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
209
+
210
+  /* Set the CEC own address */
211
+  CEC->OAR = CEC_OwnAddress;
212
+}
213
+
214
+/**
215
+  * @brief  Sets the CEC prescaler value.
216
+  * @param  CEC_Prescaler: CEC prescaler new value
217
+  * @retval None
218
+  */
219
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)
220
+{
221
+  /* Check the parameters */
222
+  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
223
+
224
+  /* Set the  Prescaler value*/
225
+  CEC->PRES = CEC_Prescaler;
226
+}
227
+
228
+/**
229
+  * @brief  Transmits single data through the CEC peripheral.
230
+  * @param  Data: the data to transmit.
231
+  * @retval None
232
+  */
233
+void CEC_SendDataByte(uint8_t Data)
234
+{  
235
+  /* Transmit Data */
236
+  CEC->TXD = Data ;
237
+}
238
+
239
+
240
+/**
241
+  * @brief  Returns the most recent received data by the CEC peripheral.
242
+  * @param  None
243
+  * @retval The received data.
244
+  */
245
+uint8_t CEC_ReceiveDataByte(void)
246
+{
247
+  /* Receive Data */
248
+  return (uint8_t)(CEC->RXD);
249
+}
250
+
251
+/**
252
+  * @brief  Starts a new message.
253
+  * @param  None
254
+  * @retval None
255
+  */
256
+void CEC_StartOfMessage(void)
257
+{  
258
+  /* Starts of new message */
259
+  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
260
+}
261
+
262
+/**
263
+  * @brief  Transmits message with or without an EOM bit.
264
+  * @param  NewState: new state of the CEC Tx End Of Message. 
265
+  *     This parameter can be: ENABLE or DISABLE.
266
+  * @retval None
267
+  */
268
+void CEC_EndOfMessageCmd(FunctionalState NewState)
269
+{   
270
+  /* Check the parameters */
271
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
272
+  
273
+  /* The data byte will be transmitted with or without an EOM bit*/
274
+  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
275
+}
276
+
277
+/**
278
+  * @brief  Gets the CEC flag status
279
+  * @param  CEC_FLAG: specifies the CEC flag to check. 
280
+  *   This parameter can be one of the following values:
281
+  *     @arg CEC_FLAG_BTE: Bit Timing Error
282
+  *     @arg CEC_FLAG_BPE: Bit Period Error
283
+  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
284
+  *     @arg CEC_FLAG_SBE: Start Bit Error
285
+  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
286
+  *     @arg CEC_FLAG_LINE: Line Error
287
+  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
288
+  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
289
+  *     @arg CEC_FLAG_TERR: Tx Error
290
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
291
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
292
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
293
+  *     @arg CEC_FLAG_RERR: Rx Error
294
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
295
+  * @retval The new state of CEC_FLAG (SET or RESET)
296
+  */
297
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
298
+{
299
+  FlagStatus bitstatus = RESET;
300
+  uint32_t cecreg = 0, cecbase = 0;
301
+  
302
+  /* Check the parameters */
303
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
304
+ 
305
+  /* Get the CEC peripheral base address */
306
+  cecbase = (uint32_t)(CEC_BASE);
307
+  
308
+  /* Read flag register index */
309
+  cecreg = CEC_FLAG >> 28;
310
+  
311
+  /* Get bit[23:0] of the flag */
312
+  CEC_FLAG &= FLAG_Mask;
313
+  
314
+  if(cecreg != 0)
315
+  {
316
+    /* Flag in CEC ESR Register */
317
+    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
318
+    
319
+    /* Get the CEC ESR register address */
320
+    cecbase += 0xC;
321
+  }
322
+  else
323
+  {
324
+    /* Get the CEC CSR register address */
325
+    cecbase += 0x10;
326
+  }
327
+  
328
+  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
329
+  {
330
+    /* CEC_FLAG is set */
331
+    bitstatus = SET;
332
+  }
333
+  else
334
+  {
335
+    /* CEC_FLAG is reset */
336
+    bitstatus = RESET;
337
+  }
338
+  
339
+  /* Return the CEC_FLAG status */
340
+  return  bitstatus;
341
+}
342
+
343
+/**
344
+  * @brief  Clears the CEC's pending flags.
345
+  * @param  CEC_FLAG: specifies the flag to clear. 
346
+  *   This parameter can be any combination of the following values:
347
+  *     @arg CEC_FLAG_TERR: Tx Error
348
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
349
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
350
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
351
+  *     @arg CEC_FLAG_RERR: Rx Error
352
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
353
+  * @retval None
354
+  */
355
+void CEC_ClearFlag(uint32_t CEC_FLAG)
356
+{ 
357
+  uint32_t tmp = 0x0;
358
+  
359
+  /* Check the parameters */
360
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
361
+
362
+  tmp = CEC->CSR & 0x2;
363
+       
364
+  /* Clear the selected CEC flags */
365
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
366
+}
367
+
368
+/**
369
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
370
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
371
+  *   This parameter can be one of the following values:
372
+  *     @arg CEC_IT_TERR: Tx Error
373
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
374
+  *     @arg CEC_IT_RERR: Rx Error
375
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
376
+  * @retval The new state of CEC_IT (SET or RESET).
377
+  */
378
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)
379
+{
380
+  ITStatus bitstatus = RESET;
381
+  uint32_t enablestatus = 0;
382
+  
383
+  /* Check the parameters */
384
+   assert_param(IS_CEC_GET_IT(CEC_IT));
385
+   
386
+  /* Get the CEC IT enable bit status */
387
+  enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
388
+  
389
+  /* Check the status of the specified CEC interrupt */
390
+  if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
391
+  {
392
+    /* CEC_IT is set */
393
+    bitstatus = SET;
394
+  }
395
+  else
396
+  {
397
+    /* CEC_IT is reset */
398
+    bitstatus = RESET;
399
+  }
400
+  /* Return the CEC_IT status */
401
+  return  bitstatus;
402
+}
403
+
404
+/**
405
+  * @brief  Clears the CEC's interrupt pending bits.
406
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
407
+  *   This parameter can be any combination of the following values:
408
+  *     @arg CEC_IT_TERR: Tx Error
409
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
410
+  *     @arg CEC_IT_RERR: Rx Error
411
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
412
+  * @retval None
413
+  */
414
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
415
+{
416
+  uint32_t tmp = 0x0;
417
+  
418
+  /* Check the parameters */
419
+  assert_param(IS_CEC_GET_IT(CEC_IT));
420
+  
421
+  tmp = CEC->CSR & 0x2;
422
+  
423
+  /* Clear the selected CEC interrupt pending bits */
424
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
425
+}
426
+
427
+/**
428
+  * @}
429
+  */ 
430
+
431
+/**
432
+  * @}
433
+  */ 
434
+
435
+/**
436
+  * @}
437
+  */ 
438
+
439
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 166
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c View File

@@ -0,0 +1,166 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_crc.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the CRC firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_crc.h"
30
+
31
+/** @addtogroup STM32F10x_StdPeriph_Driver
32
+  * @{
33
+  */
34
+
35
+/** @defgroup CRC 
36
+  * @brief CRC driver modules
37
+  * @{
38
+  */
39
+
40
+/** @defgroup CRC_Private_TypesDefinitions
41
+  * @{
42
+  */
43
+
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup CRC_Private_Defines
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/** @defgroup CRC_Private_Macros
57
+  * @{
58
+  */
59
+
60
+/**
61
+  * @}
62
+  */
63
+
64
+/** @defgroup CRC_Private_Variables
65
+  * @{
66
+  */
67
+
68
+/**
69
+  * @}
70
+  */
71
+
72
+/** @defgroup CRC_Private_FunctionPrototypes
73
+  * @{
74
+  */
75
+
76
+/**
77
+  * @}
78
+  */
79
+
80
+/** @defgroup CRC_Private_Functions
81
+  * @{
82
+  */
83
+
84
+/**
85
+  * @brief  Resets the CRC Data register (DR).
86
+  * @param  None
87
+  * @retval None
88
+  */
89
+void CRC_ResetDR(void)
90
+{
91
+  /* Reset CRC generator */
92
+  CRC->CR = CRC_CR_RESET;
93
+}
94
+
95
+/**
96
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
97
+  * @param  Data: data word(32-bit) to compute its CRC
98
+  * @retval 32-bit CRC
99
+  */
100
+uint32_t CRC_CalcCRC(uint32_t Data)
101
+{
102
+  CRC->DR = Data;
103
+  
104
+  return (CRC->DR);
105
+}
106
+
107
+/**
108
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
109
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
110
+  * @param  BufferLength: length of the buffer to be computed					
111
+  * @retval 32-bit CRC
112
+  */
113
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
114
+{
115
+  uint32_t index = 0;
116
+  
117
+  for(index = 0; index < BufferLength; index++)
118
+  {
119
+    CRC->DR = pBuffer[index];
120
+  }
121
+  return (CRC->DR);
122
+}
123
+
124
+/**
125
+  * @brief  Returns the current CRC value.
126
+  * @param  None
127
+  * @retval 32-bit CRC
128
+  */
129
+uint32_t CRC_GetCRC(void)
130
+{
131
+  return (CRC->DR);
132
+}
133
+
134
+/**
135
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
136
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
137
+  * @retval None
138
+  */
139
+void CRC_SetIDRegister(uint8_t IDValue)
140
+{
141
+  CRC->IDR = IDValue;
142
+}
143
+
144
+/**
145
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
146
+  * @param  None
147
+  * @retval 8-bit value of the ID register 
148
+  */
149
+uint8_t CRC_GetIDRegister(void)
150
+{
151
+  return (CRC->IDR);
152
+}
153
+
154
+/**
155
+  * @}
156
+  */
157
+
158
+/**
159
+  * @}
160
+  */
161
+
162
+/**
163
+  * @}
164
+  */
165
+
166
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 577
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c View File

@@ -0,0 +1,577 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dac.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the DAC firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_dac.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup DAC 
37
+  * @brief DAC driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup DAC_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+/** @defgroup DAC_Private_Defines
50
+  * @{
51
+  */
52
+
53
+/* CR register Mask */
54
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
55
+
56
+/* DAC Dual Channels SWTRIG masks */
57
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
58
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
59
+
60
+/* DHR registers offsets */
61
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
62
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
63
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
64
+
65
+/* DOR register offset */
66
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
67
+/**
68
+  * @}
69
+  */
70
+
71
+/** @defgroup DAC_Private_Macros
72
+  * @{
73
+  */
74
+
75
+/**
76
+  * @}
77
+  */
78
+
79
+/** @defgroup DAC_Private_Variables
80
+  * @{
81
+  */
82
+
83
+/**
84
+  * @}
85
+  */
86
+
87
+/** @defgroup DAC_Private_FunctionPrototypes
88
+  * @{
89
+  */
90
+
91
+/**
92
+  * @}
93
+  */
94
+
95
+/** @defgroup DAC_Private_Functions
96
+  * @{
97
+  */
98
+
99
+/**
100
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
101
+  * @param  None
102
+  * @retval None
103
+  */
104
+void DAC_DeInit(void)
105
+{
106
+  /* Enable DAC reset state */
107
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
108
+  /* Release DAC from reset state */
109
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
110
+}
111
+
112
+/**
113
+  * @brief  Initializes the DAC peripheral according to the specified 
114
+  *         parameters in the DAC_InitStruct.
115
+  * @param  DAC_Channel: the selected DAC channel. 
116
+  *   This parameter can be one of the following values:
117
+  *     @arg DAC_Channel_1: DAC Channel1 selected
118
+  *     @arg DAC_Channel_2: DAC Channel2 selected
119
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
120
+  *        contains the configuration information for the specified DAC channel.
121
+  * @retval None
122
+  */
123
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
124
+{
125
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
126
+  /* Check the DAC parameters */
127
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
128
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
129
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
130
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
131
+/*---------------------------- DAC CR Configuration --------------------------*/
132
+  /* Get the DAC CR value */
133
+  tmpreg1 = DAC->CR;
134
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
135
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
136
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
137
+     mask/amplitude for wave generation */
138
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
139
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
140
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
141
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
142
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
143
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
144
+  /* Calculate CR register value depending on DAC_Channel */
145
+  tmpreg1 |= tmpreg2 << DAC_Channel;
146
+  /* Write to DAC CR */
147
+  DAC->CR = tmpreg1;
148
+}
149
+
150
+/**
151
+  * @brief  Fills each DAC_InitStruct member with its default value.
152
+  * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
153
+  *         be initialized.
154
+  * @retval None
155
+  */
156
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
157
+{
158
+/*--------------- Reset DAC init structure parameters values -----------------*/
159
+  /* Initialize the DAC_Trigger member */
160
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
161
+  /* Initialize the DAC_WaveGeneration member */
162
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
163
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
164
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
165
+  /* Initialize the DAC_OutputBuffer member */
166
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
167
+}
168
+
169
+/**
170
+  * @brief  Enables or disables the specified DAC channel.
171
+  * @param  DAC_Channel: the selected DAC channel. 
172
+  *   This parameter can be one of the following values:
173
+  *     @arg DAC_Channel_1: DAC Channel1 selected
174
+  *     @arg DAC_Channel_2: DAC Channel2 selected
175
+  * @param  NewState: new state of the DAC channel. 
176
+  *   This parameter can be: ENABLE or DISABLE.
177
+  * @retval None
178
+  */
179
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
180
+{
181
+  /* Check the parameters */
182
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
183
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
184
+  if (NewState != DISABLE)
185
+  {
186
+    /* Enable the selected DAC channel */
187
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
188
+  }
189
+  else
190
+  {
191
+    /* Disable the selected DAC channel */
192
+    DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
193
+  }
194
+}
195
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
196
+/**
197
+  * @brief  Enables or disables the specified DAC interrupts.
198
+  * @param  DAC_Channel: the selected DAC channel. 
199
+  *   This parameter can be one of the following values:
200
+  *     @arg DAC_Channel_1: DAC Channel1 selected
201
+  *     @arg DAC_Channel_2: DAC Channel2 selected
202
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
203
+  *   This parameter can be the following values:
204
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                      
205
+  * @param  NewState: new state of the specified DAC interrupts.
206
+  *   This parameter can be: ENABLE or DISABLE.
207
+  * @retval None
208
+  */ 
209
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
210
+{
211
+  /* Check the parameters */
212
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
213
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
214
+  assert_param(IS_DAC_IT(DAC_IT)); 
215
+
216
+  if (NewState != DISABLE)
217
+  {
218
+    /* Enable the selected DAC interrupts */
219
+    DAC->CR |=  (DAC_IT << DAC_Channel);
220
+  }
221
+  else
222
+  {
223
+    /* Disable the selected DAC interrupts */
224
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
225
+  }
226
+}
227
+#endif
228
+
229
+/**
230
+  * @brief  Enables or disables the specified DAC channel DMA request.
231
+  * @param  DAC_Channel: the selected DAC channel. 
232
+  *   This parameter can be one of the following values:
233
+  *     @arg DAC_Channel_1: DAC Channel1 selected
234
+  *     @arg DAC_Channel_2: DAC Channel2 selected
235
+  * @param  NewState: new state of the selected DAC channel DMA request.
236
+  *   This parameter can be: ENABLE or DISABLE.
237
+  * @retval None
238
+  */
239
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
240
+{
241
+  /* Check the parameters */
242
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
243
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
244
+  if (NewState != DISABLE)
245
+  {
246
+    /* Enable the selected DAC channel DMA request */
247
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
248
+  }
249
+  else
250
+  {
251
+    /* Disable the selected DAC channel DMA request */
252
+    DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
253
+  }
254
+}
255
+
256
+/**
257
+  * @brief  Enables or disables the selected DAC channel software trigger.
258
+  * @param  DAC_Channel: the selected DAC channel. 
259
+  *   This parameter can be one of the following values:
260
+  *     @arg DAC_Channel_1: DAC Channel1 selected
261
+  *     @arg DAC_Channel_2: DAC Channel2 selected
262
+  * @param  NewState: new state of the selected DAC channel software trigger.
263
+  *   This parameter can be: ENABLE or DISABLE.
264
+  * @retval None
265
+  */
266
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
267
+{
268
+  /* Check the parameters */
269
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
270
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
271
+  if (NewState != DISABLE)
272
+  {
273
+    /* Enable software trigger for the selected DAC channel */
274
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
275
+  }
276
+  else
277
+  {
278
+    /* Disable software trigger for the selected DAC channel */
279
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
280
+  }
281
+}
282
+
283
+/**
284
+  * @brief  Enables or disables simultaneously the two DAC channels software
285
+  *   triggers.
286
+  * @param  NewState: new state of the DAC channels software triggers.
287
+  *   This parameter can be: ENABLE or DISABLE.
288
+  * @retval None
289
+  */
290
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
291
+{
292
+  /* Check the parameters */
293
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
294
+  if (NewState != DISABLE)
295
+  {
296
+    /* Enable software trigger for both DAC channels */
297
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
298
+  }
299
+  else
300
+  {
301
+    /* Disable software trigger for both DAC channels */
302
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
303
+  }
304
+}
305
+
306
+/**
307
+  * @brief  Enables or disables the selected DAC channel wave generation.
308
+  * @param  DAC_Channel: the selected DAC channel. 
309
+  *   This parameter can be one of the following values:
310
+  *     @arg DAC_Channel_1: DAC Channel1 selected
311
+  *     @arg DAC_Channel_2: DAC Channel2 selected
312
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
313
+  *   This parameter can be one of the following values:
314
+  *     @arg DAC_Wave_Noise: noise wave generation
315
+  *     @arg DAC_Wave_Triangle: triangle wave generation
316
+  * @param  NewState: new state of the selected DAC channel wave generation.
317
+  *   This parameter can be: ENABLE or DISABLE.
318
+  * @retval None
319
+  */
320
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
321
+{
322
+  /* Check the parameters */
323
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
324
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
325
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
326
+  if (NewState != DISABLE)
327
+  {
328
+    /* Enable the selected wave generation for the selected DAC channel */
329
+    DAC->CR |= DAC_Wave << DAC_Channel;
330
+  }
331
+  else
332
+  {
333
+    /* Disable the selected wave generation for the selected DAC channel */
334
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
335
+  }
336
+}
337
+
338
+/**
339
+  * @brief  Set the specified data holding register value for DAC channel1.
340
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
341
+  *   This parameter can be one of the following values:
342
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
343
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
344
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
345
+  * @param  Data : Data to be loaded in the selected data holding register.
346
+  * @retval None
347
+  */
348
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
349
+{  
350
+  __IO uint32_t tmp = 0;
351
+  
352
+  /* Check the parameters */
353
+  assert_param(IS_DAC_ALIGN(DAC_Align));
354
+  assert_param(IS_DAC_DATA(Data));
355
+  
356
+  tmp = (uint32_t)DAC_BASE; 
357
+  tmp += DHR12R1_OFFSET + DAC_Align;
358
+
359
+  /* Set the DAC channel1 selected data holding register */
360
+  *(__IO uint32_t *) tmp = Data;
361
+}
362
+
363
+/**
364
+  * @brief  Set the specified data holding register value for DAC channel2.
365
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
366
+  *   This parameter can be one of the following values:
367
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
368
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
369
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
370
+  * @param  Data : Data to be loaded in the selected data holding register.
371
+  * @retval None
372
+  */
373
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
374
+{
375
+  __IO uint32_t tmp = 0;
376
+
377
+  /* Check the parameters */
378
+  assert_param(IS_DAC_ALIGN(DAC_Align));
379
+  assert_param(IS_DAC_DATA(Data));
380
+  
381
+  tmp = (uint32_t)DAC_BASE;
382
+  tmp += DHR12R2_OFFSET + DAC_Align;
383
+
384
+  /* Set the DAC channel2 selected data holding register */
385
+  *(__IO uint32_t *)tmp = Data;
386
+}
387
+
388
+/**
389
+  * @brief  Set the specified data holding register value for dual channel
390
+  *   DAC.
391
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
392
+  *   This parameter can be one of the following values:
393
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
394
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
395
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
396
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
397
+  *   holding register.
398
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
399
+  *   holding register.
400
+  * @retval None
401
+  */
402
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
403
+{
404
+  uint32_t data = 0, tmp = 0;
405
+  
406
+  /* Check the parameters */
407
+  assert_param(IS_DAC_ALIGN(DAC_Align));
408
+  assert_param(IS_DAC_DATA(Data1));
409
+  assert_param(IS_DAC_DATA(Data2));
410
+  
411
+  /* Calculate and set dual DAC data holding register value */
412
+  if (DAC_Align == DAC_Align_8b_R)
413
+  {
414
+    data = ((uint32_t)Data2 << 8) | Data1; 
415
+  }
416
+  else
417
+  {
418
+    data = ((uint32_t)Data2 << 16) | Data1;
419
+  }
420
+  
421
+  tmp = (uint32_t)DAC_BASE;
422
+  tmp += DHR12RD_OFFSET + DAC_Align;
423
+
424
+  /* Set the dual DAC selected data holding register */
425
+  *(__IO uint32_t *)tmp = data;
426
+}
427
+
428
+/**
429
+  * @brief  Returns the last data output value of the selected DAC channel.
430
+  * @param  DAC_Channel: the selected DAC channel. 
431
+  *   This parameter can be one of the following values:
432
+  *     @arg DAC_Channel_1: DAC Channel1 selected
433
+  *     @arg DAC_Channel_2: DAC Channel2 selected
434
+  * @retval The selected DAC channel data output value.
435
+  */
436
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
437
+{
438
+  __IO uint32_t tmp = 0;
439
+  
440
+  /* Check the parameters */
441
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
442
+  
443
+  tmp = (uint32_t) DAC_BASE ;
444
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
445
+  
446
+  /* Returns the DAC channel data output register value */
447
+  return (uint16_t) (*(__IO uint32_t*) tmp);
448
+}
449
+
450
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
451
+/**
452
+  * @brief  Checks whether the specified DAC flag is set or not.
453
+  * @param  DAC_Channel: thee selected DAC channel. 
454
+  *   This parameter can be one of the following values:
455
+  *     @arg DAC_Channel_1: DAC Channel1 selected
456
+  *     @arg DAC_Channel_2: DAC Channel2 selected
457
+  * @param  DAC_FLAG: specifies the flag to check. 
458
+  *   This parameter can be only of the following value:
459
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                                                 
460
+  * @retval The new state of DAC_FLAG (SET or RESET).
461
+  */
462
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
463
+{
464
+  FlagStatus bitstatus = RESET;
465
+  /* Check the parameters */
466
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
467
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
468
+
469
+  /* Check the status of the specified DAC flag */
470
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
471
+  {
472
+    /* DAC_FLAG is set */
473
+    bitstatus = SET;
474
+  }
475
+  else
476
+  {
477
+    /* DAC_FLAG is reset */
478
+    bitstatus = RESET;
479
+  }
480
+  /* Return the DAC_FLAG status */
481
+  return  bitstatus;
482
+}
483
+
484
+/**
485
+  * @brief  Clears the DAC channelx's pending flags.
486
+  * @param  DAC_Channel: the selected DAC channel. 
487
+  *   This parameter can be one of the following values:
488
+  *     @arg DAC_Channel_1: DAC Channel1 selected
489
+  *     @arg DAC_Channel_2: DAC Channel2 selected
490
+  * @param  DAC_FLAG: specifies the flag to clear. 
491
+  *   This parameter can be of the following value:
492
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                           
493
+  * @retval None
494
+  */
495
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
496
+{
497
+  /* Check the parameters */
498
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
499
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
500
+
501
+  /* Clear the selected DAC flags */
502
+  DAC->SR = (DAC_FLAG << DAC_Channel);
503
+}
504
+
505
+/**
506
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
507
+  * @param  DAC_Channel: the selected DAC channel. 
508
+  *   This parameter can be one of the following values:
509
+  *     @arg DAC_Channel_1: DAC Channel1 selected
510
+  *     @arg DAC_Channel_2: DAC Channel2 selected
511
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
512
+  *   This parameter can be the following values:
513
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                       
514
+  * @retval The new state of DAC_IT (SET or RESET).
515
+  */
516
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
517
+{
518
+  ITStatus bitstatus = RESET;
519
+  uint32_t enablestatus = 0;
520
+  
521
+  /* Check the parameters */
522
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
523
+  assert_param(IS_DAC_IT(DAC_IT));
524
+
525
+  /* Get the DAC_IT enable bit status */
526
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
527
+  
528
+  /* Check the status of the specified DAC interrupt */
529
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
530
+  {
531
+    /* DAC_IT is set */
532
+    bitstatus = SET;
533
+  }
534
+  else
535
+  {
536
+    /* DAC_IT is reset */
537
+    bitstatus = RESET;
538
+  }
539
+  /* Return the DAC_IT status */
540
+  return  bitstatus;
541
+}
542
+
543
+/**
544
+  * @brief  Clears the DAC channelx's interrupt pending bits.
545
+  * @param  DAC_Channel: the selected DAC channel. 
546
+  *   This parameter can be one of the following values:
547
+  *     @arg DAC_Channel_1: DAC Channel1 selected
548
+  *     @arg DAC_Channel_2: DAC Channel2 selected
549
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
550
+  *   This parameter can be the following values:
551
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
552
+  * @retval None
553
+  */
554
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
555
+{
556
+  /* Check the parameters */
557
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
558
+  assert_param(IS_DAC_IT(DAC_IT)); 
559
+
560
+  /* Clear the selected DAC interrupt pending bits */
561
+  DAC->SR = (DAC_IT << DAC_Channel);
562
+}
563
+#endif
564
+
565
+/**
566
+  * @}
567
+  */
568
+
569
+/**
570
+  * @}
571
+  */
572
+
573
+/**
574
+  * @}
575
+  */
576
+
577
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 168
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c View File

@@ -0,0 +1,168 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dbgmcu.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the DBGMCU firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_dbgmcu.h"
30
+
31
+/** @addtogroup STM32F10x_StdPeriph_Driver
32
+  * @{
33
+  */
34
+
35
+/** @defgroup DBGMCU 
36
+  * @brief DBGMCU driver modules
37
+  * @{
38
+  */ 
39
+
40
+/** @defgroup DBGMCU_Private_TypesDefinitions
41
+  * @{
42
+  */
43
+
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup DBGMCU_Private_Defines
49
+  * @{
50
+  */
51
+
52
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
53
+/**
54
+  * @}
55
+  */
56
+
57
+/** @defgroup DBGMCU_Private_Macros
58
+  * @{
59
+  */
60
+
61
+/**
62
+  * @}
63
+  */
64
+
65
+/** @defgroup DBGMCU_Private_Variables
66
+  * @{
67
+  */
68
+
69
+/**
70
+  * @}
71
+  */
72
+
73
+/** @defgroup DBGMCU_Private_FunctionPrototypes
74
+  * @{
75
+  */
76
+
77
+/**
78
+  * @}
79
+  */
80
+
81
+/** @defgroup DBGMCU_Private_Functions
82
+  * @{
83
+  */
84
+
85
+/**
86
+  * @brief  Returns the device revision identifier.
87
+  * @param  None
88
+  * @retval Device revision identifier
89
+  */
90
+uint32_t DBGMCU_GetREVID(void)
91
+{
92
+   return(DBGMCU->IDCODE >> 16);
93
+}
94
+
95
+/**
96
+  * @brief  Returns the device identifier.
97
+  * @param  None
98
+  * @retval Device identifier
99
+  */
100
+uint32_t DBGMCU_GetDEVID(void)
101
+{
102
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
103
+}
104
+
105
+/**
106
+  * @brief  Configures the specified peripheral and low power mode behavior
107
+  *   when the MCU under Debug mode.
108
+  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
109
+  *   This parameter can be any combination of the following values:
110
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
111
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
112
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
113
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
114
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
115
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
116
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
117
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
118
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
119
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
120
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
121
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
122
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
123
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
124
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
125
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
126
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
127
+  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
128
+  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
129
+  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
130
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
131
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
132
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
133
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
134
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
135
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
136
+  * @param  NewState: new state of the specified peripheral in Debug mode.
137
+  *   This parameter can be: ENABLE or DISABLE.
138
+  * @retval None
139
+  */
140
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
141
+{
142
+  /* Check the parameters */
143
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
144
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
145
+
146
+  if (NewState != DISABLE)
147
+  {
148
+    DBGMCU->CR |= DBGMCU_Periph;
149
+  }
150
+  else
151
+  {
152
+    DBGMCU->CR &= ~DBGMCU_Periph;
153
+  }
154
+}
155
+
156
+/**
157
+  * @}
158
+  */
159
+
160
+/**
161
+  * @}
162
+  */
163
+
164
+/**
165
+  * @}
166
+  */
167
+
168
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 720
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c View File

@@ -0,0 +1,720 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_dma.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the DMA firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_dma.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup DMA 
37
+  * @brief DMA driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup DMA_Private_TypesDefinitions
42
+  * @{
43
+  */ 
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup DMA_Private_Defines
49
+  * @{
50
+  */
51
+
52
+
53
+/* DMA1 Channelx interrupt pending bit masks */
54
+#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
55
+#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
56
+#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
57
+#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
58
+#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
59
+#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
60
+#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
61
+
62
+/* DMA2 Channelx interrupt pending bit masks */
63
+#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
64
+#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
65
+#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
66
+#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
67
+#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
68
+
69
+/* DMA2 FLAG mask */
70
+#define FLAG_Mask                ((uint32_t)0x10000000)
71
+
72
+/* DMA registers Masks */
73
+#define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
74
+
75
+/**
76
+  * @}
77
+  */
78
+
79
+/** @defgroup DMA_Private_Macros
80
+  * @{
81
+  */
82
+
83
+/**
84
+  * @}
85
+  */
86
+
87
+/** @defgroup DMA_Private_Variables
88
+  * @{
89
+  */
90
+
91
+/**
92
+  * @}
93
+  */
94
+
95
+/** @defgroup DMA_Private_FunctionPrototypes
96
+  * @{
97
+  */
98
+
99
+/**
100
+  * @}
101
+  */
102
+
103
+/** @defgroup DMA_Private_Functions
104
+  * @{
105
+  */
106
+
107
+/**
108
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
109
+  *         values.
110
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
111
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
112
+  * @retval None
113
+  */
114
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
115
+{
116
+  /* Check the parameters */
117
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
118
+  
119
+  /* Disable the selected DMAy Channelx */
120
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
121
+  
122
+  /* Reset DMAy Channelx control register */
123
+  DMAy_Channelx->CCR  = 0;
124
+  
125
+  /* Reset DMAy Channelx remaining bytes register */
126
+  DMAy_Channelx->CNDTR = 0;
127
+  
128
+  /* Reset DMAy Channelx peripheral address register */
129
+  DMAy_Channelx->CPAR  = 0;
130
+  
131
+  /* Reset DMAy Channelx memory address register */
132
+  DMAy_Channelx->CMAR = 0;
133
+  
134
+  if (DMAy_Channelx == DMA1_Channel1)
135
+  {
136
+    /* Reset interrupt pending bits for DMA1 Channel1 */
137
+    DMA1->IFCR |= DMA1_Channel1_IT_Mask;
138
+  }
139
+  else if (DMAy_Channelx == DMA1_Channel2)
140
+  {
141
+    /* Reset interrupt pending bits for DMA1 Channel2 */
142
+    DMA1->IFCR |= DMA1_Channel2_IT_Mask;
143
+  }
144
+  else if (DMAy_Channelx == DMA1_Channel3)
145
+  {
146
+    /* Reset interrupt pending bits for DMA1 Channel3 */
147
+    DMA1->IFCR |= DMA1_Channel3_IT_Mask;
148
+  }
149
+  else if (DMAy_Channelx == DMA1_Channel4)
150
+  {
151
+    /* Reset interrupt pending bits for DMA1 Channel4 */
152
+    DMA1->IFCR |= DMA1_Channel4_IT_Mask;
153
+  }
154
+  else if (DMAy_Channelx == DMA1_Channel5)
155
+  {
156
+    /* Reset interrupt pending bits for DMA1 Channel5 */
157
+    DMA1->IFCR |= DMA1_Channel5_IT_Mask;
158
+  }
159
+  else if (DMAy_Channelx == DMA1_Channel6)
160
+  {
161
+    /* Reset interrupt pending bits for DMA1 Channel6 */
162
+    DMA1->IFCR |= DMA1_Channel6_IT_Mask;
163
+  }
164
+  else if (DMAy_Channelx == DMA1_Channel7)
165
+  {
166
+    /* Reset interrupt pending bits for DMA1 Channel7 */
167
+    DMA1->IFCR |= DMA1_Channel7_IT_Mask;
168
+  }
169
+  else if (DMAy_Channelx == DMA2_Channel1)
170
+  {
171
+    /* Reset interrupt pending bits for DMA2 Channel1 */
172
+    DMA2->IFCR |= DMA2_Channel1_IT_Mask;
173
+  }
174
+  else if (DMAy_Channelx == DMA2_Channel2)
175
+  {
176
+    /* Reset interrupt pending bits for DMA2 Channel2 */
177
+    DMA2->IFCR |= DMA2_Channel2_IT_Mask;
178
+  }
179
+  else if (DMAy_Channelx == DMA2_Channel3)
180
+  {
181
+    /* Reset interrupt pending bits for DMA2 Channel3 */
182
+    DMA2->IFCR |= DMA2_Channel3_IT_Mask;
183
+  }
184
+  else if (DMAy_Channelx == DMA2_Channel4)
185
+  {
186
+    /* Reset interrupt pending bits for DMA2 Channel4 */
187
+    DMA2->IFCR |= DMA2_Channel4_IT_Mask;
188
+  }
189
+  else
190
+  { 
191
+    if (DMAy_Channelx == DMA2_Channel5)
192
+    {
193
+      /* Reset interrupt pending bits for DMA2 Channel5 */
194
+      DMA2->IFCR |= DMA2_Channel5_IT_Mask;
195
+    }
196
+  }
197
+}
198
+
199
+/**
200
+  * @brief  Initializes the DMAy Channelx according to the specified
201
+  *         parameters in the DMA_InitStruct.
202
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
203
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
204
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
205
+  *         contains the configuration information for the specified DMA Channel.
206
+  * @retval None
207
+  */
208
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
209
+{
210
+  uint32_t tmpreg = 0;
211
+
212
+  /* Check the parameters */
213
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
214
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
215
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
216
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
217
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
218
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
219
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
220
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
221
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
222
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
223
+
224
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
225
+  /* Get the DMAy_Channelx CCR value */
226
+  tmpreg = DMAy_Channelx->CCR;
227
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
228
+  tmpreg &= CCR_CLEAR_Mask;
229
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
230
+  /* Set DIR bit according to DMA_DIR value */
231
+  /* Set CIRC bit according to DMA_Mode value */
232
+  /* Set PINC bit according to DMA_PeripheralInc value */
233
+  /* Set MINC bit according to DMA_MemoryInc value */
234
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
235
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
236
+  /* Set PL bits according to DMA_Priority value */
237
+  /* Set the MEM2MEM bit according to DMA_M2M value */
238
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
239
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
240
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
241
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
242
+
243
+  /* Write to DMAy Channelx CCR */
244
+  DMAy_Channelx->CCR = tmpreg;
245
+
246
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
247
+  /* Write to DMAy Channelx CNDTR */
248
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
249
+
250
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
251
+  /* Write to DMAy Channelx CPAR */
252
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
253
+
254
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
255
+  /* Write to DMAy Channelx CMAR */
256
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
257
+}
258
+
259
+/**
260
+  * @brief  Fills each DMA_InitStruct member with its default value.
261
+  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
262
+  *         be initialized.
263
+  * @retval None
264
+  */
265
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
266
+{
267
+/*-------------- Reset DMA init structure parameters values ------------------*/
268
+  /* Initialize the DMA_PeripheralBaseAddr member */
269
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
270
+  /* Initialize the DMA_MemoryBaseAddr member */
271
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
272
+  /* Initialize the DMA_DIR member */
273
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
274
+  /* Initialize the DMA_BufferSize member */
275
+  DMA_InitStruct->DMA_BufferSize = 0;
276
+  /* Initialize the DMA_PeripheralInc member */
277
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
278
+  /* Initialize the DMA_MemoryInc member */
279
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
280
+  /* Initialize the DMA_PeripheralDataSize member */
281
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
282
+  /* Initialize the DMA_MemoryDataSize member */
283
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
284
+  /* Initialize the DMA_Mode member */
285
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
286
+  /* Initialize the DMA_Priority member */
287
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
288
+  /* Initialize the DMA_M2M member */
289
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
290
+}
291
+
292
+/**
293
+  * @brief  Enables or disables the specified DMAy Channelx.
294
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
295
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
296
+  * @param  NewState: new state of the DMAy Channelx. 
297
+  *   This parameter can be: ENABLE or DISABLE.
298
+  * @retval None
299
+  */
300
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
301
+{
302
+  /* Check the parameters */
303
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
304
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
305
+
306
+  if (NewState != DISABLE)
307
+  {
308
+    /* Enable the selected DMAy Channelx */
309
+    DMAy_Channelx->CCR |= DMA_CCR1_EN;
310
+  }
311
+  else
312
+  {
313
+    /* Disable the selected DMAy Channelx */
314
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
315
+  }
316
+}
317
+
318
+/**
319
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
320
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
321
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
322
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
323
+  *   or disabled. 
324
+  *   This parameter can be any combination of the following values:
325
+  *     @arg DMA_IT_TC:  Transfer complete interrupt mask
326
+  *     @arg DMA_IT_HT:  Half transfer interrupt mask
327
+  *     @arg DMA_IT_TE:  Transfer error interrupt mask
328
+  * @param  NewState: new state of the specified DMA interrupts.
329
+  *   This parameter can be: ENABLE or DISABLE.
330
+  * @retval None
331
+  */
332
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
333
+{
334
+  /* Check the parameters */
335
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
336
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
337
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
338
+  if (NewState != DISABLE)
339
+  {
340
+    /* Enable the selected DMA interrupts */
341
+    DMAy_Channelx->CCR |= DMA_IT;
342
+  }
343
+  else
344
+  {
345
+    /* Disable the selected DMA interrupts */
346
+    DMAy_Channelx->CCR &= ~DMA_IT;
347
+  }
348
+}
349
+
350
+/**
351
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
352
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
353
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
354
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
355
+  *         transfer.   
356
+  * @note   This function can only be used when the DMAy_Channelx is disabled.                 
357
+  * @retval None.
358
+  */
359
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
360
+{
361
+  /* Check the parameters */
362
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
363
+  
364
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
365
+  /* Write to DMAy Channelx CNDTR */
366
+  DMAy_Channelx->CNDTR = DataNumber;  
367
+}
368
+
369
+/**
370
+  * @brief  Returns the number of remaining data units in the current
371
+  *         DMAy Channelx transfer.
372
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
373
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
374
+  * @retval The number of remaining data units in the current DMAy Channelx
375
+  *         transfer.
376
+  */
377
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
378
+{
379
+  /* Check the parameters */
380
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
381
+  /* Return the number of remaining data units for DMAy Channelx */
382
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
383
+}
384
+
385
+/**
386
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
387
+  * @param  DMAy_FLAG: specifies the flag to check.
388
+  *   This parameter can be one of the following values:
389
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
390
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
391
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
392
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
393
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
394
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
395
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
396
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
397
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
398
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
399
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
400
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
401
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
402
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
403
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
404
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
405
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
406
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
407
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
408
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
409
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
410
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
411
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
412
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
413
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
414
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
415
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
416
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
417
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
418
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
419
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
420
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
421
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
422
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
423
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
424
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
425
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
426
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
427
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
428
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
429
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
430
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
431
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
432
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
433
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
434
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
435
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
436
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
437
+  * @retval The new state of DMAy_FLAG (SET or RESET).
438
+  */
439
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
440
+{
441
+  FlagStatus bitstatus = RESET;
442
+  uint32_t tmpreg = 0;
443
+  
444
+  /* Check the parameters */
445
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
446
+
447
+  /* Calculate the used DMAy */
448
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
449
+  {
450
+    /* Get DMA2 ISR register value */
451
+    tmpreg = DMA2->ISR ;
452
+  }
453
+  else
454
+  {
455
+    /* Get DMA1 ISR register value */
456
+    tmpreg = DMA1->ISR ;
457
+  }
458
+
459
+  /* Check the status of the specified DMAy flag */
460
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
461
+  {
462
+    /* DMAy_FLAG is set */
463
+    bitstatus = SET;
464
+  }
465
+  else
466
+  {
467
+    /* DMAy_FLAG is reset */
468
+    bitstatus = RESET;
469
+  }
470
+  
471
+  /* Return the DMAy_FLAG status */
472
+  return  bitstatus;
473
+}
474
+
475
+/**
476
+  * @brief  Clears the DMAy Channelx's pending flags.
477
+  * @param  DMAy_FLAG: specifies the flag to clear.
478
+  *   This parameter can be any combination (for the same DMA) of the following values:
479
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
480
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
481
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
482
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
483
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
484
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
485
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
486
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
487
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
488
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
489
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
490
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
491
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
492
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
493
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
494
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
495
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
496
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
497
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
498
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
499
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
500
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
501
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
502
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
503
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
504
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
505
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
506
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
507
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
508
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
509
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
510
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
511
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
512
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
513
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
514
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
515
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
516
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
517
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
518
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
519
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
520
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
521
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
522
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
523
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
524
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
525
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
526
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
527
+  * @retval None
528
+  */
529
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
530
+{
531
+  /* Check the parameters */
532
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
533
+
534
+  /* Calculate the used DMAy */
535
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
536
+  {
537
+    /* Clear the selected DMAy flags */
538
+    DMA2->IFCR = DMAy_FLAG;
539
+  }
540
+  else
541
+  {
542
+    /* Clear the selected DMAy flags */
543
+    DMA1->IFCR = DMAy_FLAG;
544
+  }
545
+}
546
+
547
+/**
548
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
549
+  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
550
+  *   This parameter can be one of the following values:
551
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
552
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
553
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
554
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
555
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
556
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
557
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
558
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
559
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
560
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
561
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
562
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
563
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
564
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
565
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
566
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
567
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
568
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
569
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
570
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
571
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
572
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
573
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
574
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
575
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
576
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
577
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
578
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
579
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
580
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
581
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
582
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
583
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
584
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
585
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
586
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
587
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
588
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
589
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
590
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
591
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
592
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
593
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
594
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
595
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
596
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
597
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
598
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
599
+  * @retval The new state of DMAy_IT (SET or RESET).
600
+  */
601
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
602
+{
603
+  ITStatus bitstatus = RESET;
604
+  uint32_t tmpreg = 0;
605
+
606
+  /* Check the parameters */
607
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
608
+
609
+  /* Calculate the used DMA */
610
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
611
+  {
612
+    /* Get DMA2 ISR register value */
613
+    tmpreg = DMA2->ISR;
614
+  }
615
+  else
616
+  {
617
+    /* Get DMA1 ISR register value */
618
+    tmpreg = DMA1->ISR;
619
+  }
620
+
621
+  /* Check the status of the specified DMAy interrupt */
622
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
623
+  {
624
+    /* DMAy_IT is set */
625
+    bitstatus = SET;
626
+  }
627
+  else
628
+  {
629
+    /* DMAy_IT is reset */
630
+    bitstatus = RESET;
631
+  }
632
+  /* Return the DMA_IT status */
633
+  return  bitstatus;
634
+}
635
+
636
+/**
637
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
638
+  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
639
+  *   This parameter can be any combination (for the same DMA) of the following values:
640
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
641
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
642
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
643
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
644
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
645
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
646
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
647
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
648
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
649
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
650
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
651
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
652
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
653
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
654
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
655
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
656
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
657
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
658
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
659
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
660
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
661
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
662
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
663
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
664
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
665
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
666
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
667
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
668
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
669
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
670
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
671
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
672
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
673
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
674
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
675
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
676
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
677
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
678
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
679
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
680
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
681
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
682
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
683
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
684
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
685
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
686
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
687
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
688
+  * @retval None
689
+  */
690
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
691
+{
692
+  /* Check the parameters */
693
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
694
+
695
+  /* Calculate the used DMAy */
696
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
697
+  {
698
+    /* Clear the selected DMAy interrupt pending bits */
699
+    DMA2->IFCR = DMAy_IT;
700
+  }
701
+  else
702
+  {
703
+    /* Clear the selected DMAy interrupt pending bits */
704
+    DMA1->IFCR = DMAy_IT;
705
+  }
706
+}
707
+
708
+/**
709
+  * @}
710
+  */
711
+
712
+/**
713
+  * @}
714
+  */
715
+
716
+/**
717
+  * @}
718
+  */
719
+
720
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 275
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c View File

@@ -0,0 +1,275 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_exti.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the EXTI firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_exti.h"
30
+
31
+/** @addtogroup STM32F10x_StdPeriph_Driver
32
+  * @{
33
+  */
34
+
35
+/** @defgroup EXTI 
36
+  * @brief EXTI driver modules
37
+  * @{
38
+  */
39
+
40
+/** @defgroup EXTI_Private_TypesDefinitions
41
+  * @{
42
+  */
43
+
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup EXTI_Private_Defines
49
+  * @{
50
+  */
51
+
52
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
53
+
54
+/**
55
+  * @}
56
+  */
57
+
58
+/** @defgroup EXTI_Private_Macros
59
+  * @{
60
+  */
61
+
62
+/**
63
+  * @}
64
+  */
65
+
66
+/** @defgroup EXTI_Private_Variables
67
+  * @{
68
+  */
69
+
70
+/**
71
+  * @}
72
+  */
73
+
74
+/** @defgroup EXTI_Private_FunctionPrototypes
75
+  * @{
76
+  */
77
+
78
+/**
79
+  * @}
80
+  */
81
+
82
+/** @defgroup EXTI_Private_Functions
83
+  * @{
84
+  */
85
+
86
+/**
87
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
88
+  * @param  None
89
+  * @retval None
90
+  */
91
+void EXTI_DeInit(void)
92
+{
93
+  EXTI->IMR = 0x00000000;
94
+  EXTI->EMR = 0x00000000;
95
+  EXTI->RTSR = 0x00000000; 
96
+  EXTI->FTSR = 0x00000000; 
97
+  EXTI->PR = 0x000FFFFF;
98
+}
99
+
100
+/**
101
+  * @brief  Initializes the EXTI peripheral according to the specified
102
+  *         parameters in the EXTI_InitStruct.
103
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
104
+  *         that contains the configuration information for the EXTI peripheral.
105
+  * @retval None
106
+  */
107
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
108
+{
109
+  uint32_t tmp = 0;
110
+
111
+  /* Check the parameters */
112
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
113
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
114
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
115
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
116
+
117
+  tmp = (uint32_t)EXTI_BASE;
118
+     
119
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
120
+  {
121
+    /* Clear EXTI line configuration */
122
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
123
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
124
+    
125
+    tmp += EXTI_InitStruct->EXTI_Mode;
126
+
127
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
128
+
129
+    /* Clear Rising Falling edge configuration */
130
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
131
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
132
+    
133
+    /* Select the trigger for the selected external interrupts */
134
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
135
+    {
136
+      /* Rising Falling edge */
137
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
138
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
139
+    }
140
+    else
141
+    {
142
+      tmp = (uint32_t)EXTI_BASE;
143
+      tmp += EXTI_InitStruct->EXTI_Trigger;
144
+
145
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
146
+    }
147
+  }
148
+  else
149
+  {
150
+    tmp += EXTI_InitStruct->EXTI_Mode;
151
+
152
+    /* Disable the selected external lines */
153
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
154
+  }
155
+}
156
+
157
+/**
158
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
159
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
160
+  *         be initialized.
161
+  * @retval None
162
+  */
163
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
164
+{
165
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
166
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
167
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
168
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
169
+}
170
+
171
+/**
172
+  * @brief  Generates a Software interrupt.
173
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
174
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
175
+  * @retval None
176
+  */
177
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
178
+{
179
+  /* Check the parameters */
180
+  assert_param(IS_EXTI_LINE(EXTI_Line));
181
+  
182
+  EXTI->SWIER |= EXTI_Line;
183
+}
184
+
185
+/**
186
+  * @brief  Checks whether the specified EXTI line flag is set or not.
187
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
188
+  *   This parameter can be:
189
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
190
+  * @retval The new state of EXTI_Line (SET or RESET).
191
+  */
192
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
193
+{
194
+  FlagStatus bitstatus = RESET;
195
+  /* Check the parameters */
196
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
197
+  
198
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
199
+  {
200
+    bitstatus = SET;
201
+  }
202
+  else
203
+  {
204
+    bitstatus = RESET;
205
+  }
206
+  return bitstatus;
207
+}
208
+
209
+/**
210
+  * @brief  Clears the EXTI's line pending flags.
211
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
212
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
213
+  * @retval None
214
+  */
215
+void EXTI_ClearFlag(uint32_t EXTI_Line)
216
+{
217
+  /* Check the parameters */
218
+  assert_param(IS_EXTI_LINE(EXTI_Line));
219
+  
220
+  EXTI->PR = EXTI_Line;
221
+}
222
+
223
+/**
224
+  * @brief  Checks whether the specified EXTI line is asserted or not.
225
+  * @param  EXTI_Line: specifies the EXTI line to check.
226
+  *   This parameter can be:
227
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
228
+  * @retval The new state of EXTI_Line (SET or RESET).
229
+  */
230
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
231
+{
232
+  ITStatus bitstatus = RESET;
233
+  uint32_t enablestatus = 0;
234
+  /* Check the parameters */
235
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
236
+  
237
+  enablestatus =  EXTI->IMR & EXTI_Line;
238
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
239
+  {
240
+    bitstatus = SET;
241
+  }
242
+  else
243
+  {
244
+    bitstatus = RESET;
245
+  }
246
+  return bitstatus;
247
+}
248
+
249
+/**
250
+  * @brief  Clears the EXTI's line pending bits.
251
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
252
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
253
+  * @retval None
254
+  */
255
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
256
+{
257
+  /* Check the parameters */
258
+  assert_param(IS_EXTI_LINE(EXTI_Line));
259
+  
260
+  EXTI->PR = EXTI_Line;
261
+}
262
+
263
+/**
264
+  * @}
265
+  */
266
+
267
+/**
268
+  * @}
269
+  */
270
+
271
+/**
272
+  * @}
273
+  */
274
+
275
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1685
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
File diff suppressed because it is too large
View File


+ 872
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c View File

@@ -0,0 +1,872 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_fsmc.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the FSMC firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_fsmc.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup FSMC 
37
+  * @brief FSMC driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup FSMC_Private_TypesDefinitions
42
+  * @{
43
+  */ 
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup FSMC_Private_Defines
49
+  * @{
50
+  */
51
+
52
+/* --------------------- FSMC registers bit mask ---------------------------- */
53
+
54
+/* FSMC BCRx Mask */
55
+#define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
56
+#define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
57
+#define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
58
+
59
+/* FSMC PCRx Mask */
60
+#define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
61
+#define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
62
+#define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
63
+#define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
64
+#define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
65
+/**
66
+  * @}
67
+  */
68
+
69
+/** @defgroup FSMC_Private_Macros
70
+  * @{
71
+  */
72
+
73
+/**
74
+  * @}
75
+  */
76
+
77
+/** @defgroup FSMC_Private_Variables
78
+  * @{
79
+  */
80
+
81
+/**
82
+  * @}
83
+  */
84
+
85
+/** @defgroup FSMC_Private_FunctionPrototypes
86
+  * @{
87
+  */
88
+
89
+/**
90
+  * @}
91
+  */
92
+
93
+/** @defgroup FSMC_Private_Functions
94
+  * @{
95
+  */
96
+
97
+/**
98
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
99
+  *         reset values.
100
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
101
+  *   This parameter can be one of the following values:
102
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
103
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
104
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
105
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
106
+  * @retval None
107
+  */
108
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
109
+{
110
+  /* Check the parameter */
111
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
112
+  
113
+  /* FSMC_Bank1_NORSRAM1 */
114
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
115
+  {
116
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
117
+  }
118
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
119
+  else
120
+  {   
121
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
122
+  }
123
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
124
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
125
+}
126
+
127
+/**
128
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
129
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
130
+  *   This parameter can be one of the following values:
131
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
132
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
133
+  * @retval None
134
+  */
135
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
136
+{
137
+  /* Check the parameter */
138
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
139
+  
140
+  if(FSMC_Bank == FSMC_Bank2_NAND)
141
+  {
142
+    /* Set the FSMC_Bank2 registers to their reset values */
143
+    FSMC_Bank2->PCR2 = 0x00000018;
144
+    FSMC_Bank2->SR2 = 0x00000040;
145
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
146
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
147
+  }
148
+  /* FSMC_Bank3_NAND */  
149
+  else
150
+  {
151
+    /* Set the FSMC_Bank3 registers to their reset values */
152
+    FSMC_Bank3->PCR3 = 0x00000018;
153
+    FSMC_Bank3->SR3 = 0x00000040;
154
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
155
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
156
+  }  
157
+}
158
+
159
+/**
160
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
161
+  * @param  None                       
162
+  * @retval None
163
+  */
164
+void FSMC_PCCARDDeInit(void)
165
+{
166
+  /* Set the FSMC_Bank4 registers to their reset values */
167
+  FSMC_Bank4->PCR4 = 0x00000018; 
168
+  FSMC_Bank4->SR4 = 0x00000000;	
169
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
170
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
171
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
172
+}
173
+
174
+/**
175
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
176
+  *         parameters in the FSMC_NORSRAMInitStruct.
177
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
178
+  *         structure that contains the configuration information for 
179
+  *        the FSMC NOR/SRAM specified Banks.                       
180
+  * @retval None
181
+  */
182
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
183
+{ 
184
+  /* Check the parameters */
185
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
186
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
187
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
188
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
189
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
190
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
191
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
192
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
193
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
194
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
195
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
196
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
197
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
198
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
199
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
200
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
201
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
202
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
203
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
204
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
205
+  
206
+  /* Bank1 NOR/SRAM control register configuration */ 
207
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
208
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
209
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
210
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
211
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
212
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
213
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
214
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
215
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
216
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
217
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
218
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
219
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
220
+
221
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
222
+  {
223
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
224
+  }
225
+  
226
+  /* Bank1 NOR/SRAM timing register configuration */
227
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
228
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
229
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
230
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
231
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
232
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
233
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
234
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
235
+            
236
+    
237
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
238
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
239
+  {
240
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
241
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
242
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
243
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
244
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
245
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
246
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
247
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
248
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
249
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
250
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
251
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
252
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
253
+  }
254
+  else
255
+  {
256
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
257
+  }
258
+}
259
+
260
+/**
261
+  * @brief  Initializes the FSMC NAND Banks according to the specified 
262
+  *         parameters in the FSMC_NANDInitStruct.
263
+  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef 
264
+  *         structure that contains the configuration information for the FSMC 
265
+  *         NAND specified Banks.                       
266
+  * @retval None
267
+  */
268
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
269
+{
270
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
271
+    
272
+  /* Check the parameters */
273
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
274
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
275
+  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
276
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
277
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
278
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
279
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
280
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
281
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
282
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
283
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
284
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
285
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
286
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
287
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
288
+  
289
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
290
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
291
+            PCR_MemoryType_NAND |
292
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
293
+            FSMC_NANDInitStruct->FSMC_ECC |
294
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
295
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
296
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
297
+            
298
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
299
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
300
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
301
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
302
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
303
+            
304
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
305
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
306
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
307
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
308
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
309
+  
310
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
311
+  {
312
+    /* FSMC_Bank2_NAND registers configuration */
313
+    FSMC_Bank2->PCR2 = tmppcr;
314
+    FSMC_Bank2->PMEM2 = tmppmem;
315
+    FSMC_Bank2->PATT2 = tmppatt;
316
+  }
317
+  else
318
+  {
319
+    /* FSMC_Bank3_NAND registers configuration */
320
+    FSMC_Bank3->PCR3 = tmppcr;
321
+    FSMC_Bank3->PMEM3 = tmppmem;
322
+    FSMC_Bank3->PATT3 = tmppatt;
323
+  }
324
+}
325
+
326
+/**
327
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified 
328
+  *         parameters in the FSMC_PCCARDInitStruct.
329
+  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
330
+  *         structure that contains the configuration information for the FSMC 
331
+  *         PCCARD Bank.                       
332
+  * @retval None
333
+  */
334
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
335
+{
336
+  /* Check the parameters */
337
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
338
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
339
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
340
+ 
341
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
342
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
343
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
344
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
345
+  
346
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
347
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
348
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
349
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
350
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
351
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
352
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
353
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
354
+  
355
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
356
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
357
+                     FSMC_MemoryDataWidth_16b |  
358
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
359
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
360
+            
361
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
362
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
363
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
364
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
365
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
366
+            
367
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
368
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
369
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
370
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
371
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
372
+            
373
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
374
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
375
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
376
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
377
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
378
+}
379
+
380
+/**
381
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
382
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
383
+  *         structure which will be initialized.
384
+  * @retval None
385
+  */
386
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
387
+{  
388
+  /* Reset NOR/SRAM Init structure parameters values */
389
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
390
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
391
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
392
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
393
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
394
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
395
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
396
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
397
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
398
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
399
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
400
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
401
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
402
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
403
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
404
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
405
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
406
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
407
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
408
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
409
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
410
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
411
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
412
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
413
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
414
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
415
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
416
+}
417
+
418
+/**
419
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
420
+  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef 
421
+  *         structure which will be initialized.
422
+  * @retval None
423
+  */
424
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
425
+{ 
426
+  /* Reset NAND Init structure parameters values */
427
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
428
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
429
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
430
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
431
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
432
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
433
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
434
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
435
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
436
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
437
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
438
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
439
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
440
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
441
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
442
+}
443
+
444
+/**
445
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
446
+  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef 
447
+  *         structure which will be initialized.
448
+  * @retval None
449
+  */
450
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
451
+{
452
+  /* Reset PCCARD Init structure parameters values */
453
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
454
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
455
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
456
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
457
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
458
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
459
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
460
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
461
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
462
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
463
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
464
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
465
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
466
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
467
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
468
+}
469
+
470
+/**
471
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
472
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
473
+  *   This parameter can be one of the following values:
474
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
475
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
476
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
477
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
478
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
479
+  * @retval None
480
+  */
481
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
482
+{
483
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
484
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
485
+  
486
+  if (NewState != DISABLE)
487
+  {
488
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
489
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
490
+  }
491
+  else
492
+  {
493
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
494
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
495
+  }
496
+}
497
+
498
+/**
499
+  * @brief  Enables or disables the specified NAND Memory Bank.
500
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
501
+  *   This parameter can be one of the following values:
502
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
503
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
504
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
505
+  * @retval None
506
+  */
507
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
508
+{
509
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
510
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
511
+  
512
+  if (NewState != DISABLE)
513
+  {
514
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
515
+    if(FSMC_Bank == FSMC_Bank2_NAND)
516
+    {
517
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
518
+    }
519
+    else
520
+    {
521
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
522
+    }
523
+  }
524
+  else
525
+  {
526
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
527
+    if(FSMC_Bank == FSMC_Bank2_NAND)
528
+    {
529
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
530
+    }
531
+    else
532
+    {
533
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
534
+    }
535
+  }
536
+}
537
+
538
+/**
539
+  * @brief  Enables or disables the PCCARD Memory Bank.
540
+  * @param  NewState: new state of the PCCARD Memory Bank.  
541
+  *   This parameter can be: ENABLE or DISABLE.
542
+  * @retval None
543
+  */
544
+void FSMC_PCCARDCmd(FunctionalState NewState)
545
+{
546
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
547
+  
548
+  if (NewState != DISABLE)
549
+  {
550
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
551
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
552
+  }
553
+  else
554
+  {
555
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
556
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
557
+  }
558
+}
559
+
560
+/**
561
+  * @brief  Enables or disables the FSMC NAND ECC feature.
562
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
563
+  *   This parameter can be one of the following values:
564
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
565
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
566
+  * @param  NewState: new state of the FSMC NAND ECC feature.  
567
+  *   This parameter can be: ENABLE or DISABLE.
568
+  * @retval None
569
+  */
570
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
571
+{
572
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
573
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
574
+  
575
+  if (NewState != DISABLE)
576
+  {
577
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
578
+    if(FSMC_Bank == FSMC_Bank2_NAND)
579
+    {
580
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
581
+    }
582
+    else
583
+    {
584
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
585
+    }
586
+  }
587
+  else
588
+  {
589
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
590
+    if(FSMC_Bank == FSMC_Bank2_NAND)
591
+    {
592
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
593
+    }
594
+    else
595
+    {
596
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
597
+    }
598
+  }
599
+}
600
+
601
+/**
602
+  * @brief  Returns the error correction code register value.
603
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
604
+  *   This parameter can be one of the following values:
605
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
606
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
607
+  * @retval The Error Correction Code (ECC) value.
608
+  */
609
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
610
+{
611
+  uint32_t eccval = 0x00000000;
612
+  
613
+  if(FSMC_Bank == FSMC_Bank2_NAND)
614
+  {
615
+    /* Get the ECCR2 register value */
616
+    eccval = FSMC_Bank2->ECCR2;
617
+  }
618
+  else
619
+  {
620
+    /* Get the ECCR3 register value */
621
+    eccval = FSMC_Bank3->ECCR3;
622
+  }
623
+  /* Return the error correction code value */
624
+  return(eccval);
625
+}
626
+
627
+/**
628
+  * @brief  Enables or disables the specified FSMC interrupts.
629
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
630
+  *   This parameter can be one of the following values:
631
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
632
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
633
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
634
+  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
635
+  *   This parameter can be any combination of the following values:
636
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
637
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
638
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
639
+  * @param  NewState: new state of the specified FSMC interrupts.
640
+  *   This parameter can be: ENABLE or DISABLE.
641
+  * @retval None
642
+  */
643
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
644
+{
645
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
646
+  assert_param(IS_FSMC_IT(FSMC_IT));	
647
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
648
+  
649
+  if (NewState != DISABLE)
650
+  {
651
+    /* Enable the selected FSMC_Bank2 interrupts */
652
+    if(FSMC_Bank == FSMC_Bank2_NAND)
653
+    {
654
+      FSMC_Bank2->SR2 |= FSMC_IT;
655
+    }
656
+    /* Enable the selected FSMC_Bank3 interrupts */
657
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
658
+    {
659
+      FSMC_Bank3->SR3 |= FSMC_IT;
660
+    }
661
+    /* Enable the selected FSMC_Bank4 interrupts */
662
+    else
663
+    {
664
+      FSMC_Bank4->SR4 |= FSMC_IT;    
665
+    }
666
+  }
667
+  else
668
+  {
669
+    /* Disable the selected FSMC_Bank2 interrupts */
670
+    if(FSMC_Bank == FSMC_Bank2_NAND)
671
+    {
672
+      
673
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
674
+    }
675
+    /* Disable the selected FSMC_Bank3 interrupts */
676
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
677
+    {
678
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
679
+    }
680
+    /* Disable the selected FSMC_Bank4 interrupts */
681
+    else
682
+    {
683
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
684
+    }
685
+  }
686
+}
687
+
688
+/**
689
+  * @brief  Checks whether the specified FSMC flag is set or not.
690
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
691
+  *   This parameter can be one of the following values:
692
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
693
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
694
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
695
+  * @param  FSMC_FLAG: specifies the flag to check.
696
+  *   This parameter can be one of the following values:
697
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
698
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
699
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
700
+  *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
701
+  * @retval The new state of FSMC_FLAG (SET or RESET).
702
+  */
703
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
704
+{
705
+  FlagStatus bitstatus = RESET;
706
+  uint32_t tmpsr = 0x00000000;
707
+  
708
+  /* Check the parameters */
709
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
710
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
711
+  
712
+  if(FSMC_Bank == FSMC_Bank2_NAND)
713
+  {
714
+    tmpsr = FSMC_Bank2->SR2;
715
+  }  
716
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
717
+  {
718
+    tmpsr = FSMC_Bank3->SR3;
719
+  }
720
+  /* FSMC_Bank4_PCCARD*/
721
+  else
722
+  {
723
+    tmpsr = FSMC_Bank4->SR4;
724
+  } 
725
+  
726
+  /* Get the flag status */
727
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
728
+  {
729
+    bitstatus = SET;
730
+  }
731
+  else
732
+  {
733
+    bitstatus = RESET;
734
+  }
735
+  /* Return the flag status */
736
+  return bitstatus;
737
+}
738
+
739
+/**
740
+  * @brief  Clears the FSMC's pending flags.
741
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
742
+  *   This parameter can be one of the following values:
743
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
744
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
745
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
746
+  * @param  FSMC_FLAG: specifies the flag to clear.
747
+  *   This parameter can be any combination of the following values:
748
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
749
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
750
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
751
+  * @retval None
752
+  */
753
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
754
+{
755
+ /* Check the parameters */
756
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
757
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
758
+    
759
+  if(FSMC_Bank == FSMC_Bank2_NAND)
760
+  {
761
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
762
+  }  
763
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
764
+  {
765
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
766
+  }
767
+  /* FSMC_Bank4_PCCARD*/
768
+  else
769
+  {
770
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
771
+  }
772
+}
773
+
774
+/**
775
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
776
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
777
+  *   This parameter can be one of the following values:
778
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
779
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
780
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
781
+  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
782
+  *   This parameter can be one of the following values:
783
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
784
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
785
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
786
+  * @retval The new state of FSMC_IT (SET or RESET).
787
+  */
788
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
789
+{
790
+  ITStatus bitstatus = RESET;
791
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
792
+  
793
+  /* Check the parameters */
794
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
795
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
796
+  
797
+  if(FSMC_Bank == FSMC_Bank2_NAND)
798
+  {
799
+    tmpsr = FSMC_Bank2->SR2;
800
+  }  
801
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
802
+  {
803
+    tmpsr = FSMC_Bank3->SR3;
804
+  }
805
+  /* FSMC_Bank4_PCCARD*/
806
+  else
807
+  {
808
+    tmpsr = FSMC_Bank4->SR4;
809
+  } 
810
+  
811
+  itstatus = tmpsr & FSMC_IT;
812
+  
813
+  itenable = tmpsr & (FSMC_IT >> 3);
814
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
815
+  {
816
+    bitstatus = SET;
817
+  }
818
+  else
819
+  {
820
+    bitstatus = RESET;
821
+  }
822
+  return bitstatus; 
823
+}
824
+
825
+/**
826
+  * @brief  Clears the FSMC's interrupt pending bits.
827
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
828
+  *   This parameter can be one of the following values:
829
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
830
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
831
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
832
+  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
833
+  *   This parameter can be any combination of the following values:
834
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
835
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
836
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
837
+  * @retval None
838
+  */
839
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
840
+{
841
+  /* Check the parameters */
842
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
843
+  assert_param(IS_FSMC_IT(FSMC_IT));
844
+    
845
+  if(FSMC_Bank == FSMC_Bank2_NAND)
846
+  {
847
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
848
+  }  
849
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
850
+  {
851
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
852
+  }
853
+  /* FSMC_Bank4_PCCARD*/
854
+  else
855
+  {
856
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
857
+  }
858
+}
859
+
860
+/**
861
+  * @}
862
+  */ 
863
+
864
+/**
865
+  * @}
866
+  */
867
+
868
+/**
869
+  * @}
870
+  */
871
+
872
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 656
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c View File

@@ -0,0 +1,656 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_gpio.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the GPIO firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_gpio.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup GPIO 
37
+  * @brief GPIO driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup GPIO_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+/** @defgroup GPIO_Private_Defines
50
+  * @{
51
+  */
52
+
53
+/* ------------ RCC registers bit address in the alias region ----------------*/
54
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
55
+
56
+/* --- EVENTCR Register -----*/
57
+
58
+/* Alias word address of EVOE bit */
59
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
60
+#define EVOE_BitNumber              ((uint8_t)0x07)
61
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
62
+
63
+
64
+/* ---  MAPR Register ---*/ 
65
+/* Alias word address of MII_RMII_SEL bit */ 
66
+#define MAPR_OFFSET                 (AFIO_OFFSET + 0x04) 
67
+#define MII_RMII_SEL_BitNumber      ((u8)0x17) 
68
+#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
69
+
70
+
71
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
72
+#define LSB_MASK                    ((uint16_t)0xFFFF)
73
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
74
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
75
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
76
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
77
+/**
78
+  * @}
79
+  */
80
+
81
+/** @defgroup GPIO_Private_Macros
82
+  * @{
83
+  */
84
+
85
+/**
86
+  * @}
87
+  */
88
+
89
+/** @defgroup GPIO_Private_Variables
90
+  * @{
91
+  */
92
+
93
+/**
94
+  * @}
95
+  */
96
+
97
+/** @defgroup GPIO_Private_FunctionPrototypes
98
+  * @{
99
+  */
100
+
101
+/**
102
+  * @}
103
+  */
104
+
105
+/** @defgroup GPIO_Private_Functions
106
+  * @{
107
+  */
108
+
109
+/**
110
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
111
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
112
+  * @retval None
113
+  */
114
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
115
+{
116
+  /* Check the parameters */
117
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
118
+  
119
+  if (GPIOx == GPIOA)
120
+  {
121
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
122
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
123
+  }
124
+  else if (GPIOx == GPIOB)
125
+  {
126
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
127
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
128
+  }
129
+  else if (GPIOx == GPIOC)
130
+  {
131
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
132
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
133
+  }
134
+  else if (GPIOx == GPIOD)
135
+  {
136
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
137
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
138
+  }    
139
+  else if (GPIOx == GPIOE)
140
+  {
141
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
142
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
143
+  } 
144
+  else if (GPIOx == GPIOF)
145
+  {
146
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
147
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
148
+  }
149
+  else
150
+  {
151
+    if (GPIOx == GPIOG)
152
+    {
153
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
154
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
155
+    }
156
+  }
157
+}
158
+
159
+/**
160
+  * @brief  Deinitializes the Alternate Functions (remap, event control
161
+  *   and EXTI configuration) registers to their default reset values.
162
+  * @param  None
163
+  * @retval None
164
+  */
165
+void GPIO_AFIODeInit(void)
166
+{
167
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
168
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
169
+}
170
+
171
+/**
172
+  * @brief  Initializes the GPIOx peripheral according to the specified
173
+  *         parameters in the GPIO_InitStruct.
174
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
175
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
176
+  *         contains the configuration information for the specified GPIO peripheral.
177
+  * @retval None
178
+  */
179
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
180
+{
181
+  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
182
+  uint32_t tmpreg = 0x00, pinmask = 0x00;
183
+  /* Check the parameters */
184
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
185
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
186
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
187
+  
188
+/*---------------------------- GPIO Mode Configuration -----------------------*/
189
+  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
190
+  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
191
+  { 
192
+    /* Check the parameters */
193
+    assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
194
+    /* Output mode */
195
+    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
196
+  }
197
+/*---------------------------- GPIO CRL Configuration ------------------------*/
198
+  /* Configure the eight low port pins */
199
+  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
200
+  {
201
+    tmpreg = GPIOx->CRL;
202
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
203
+    {
204
+      pos = ((uint32_t)0x01) << pinpos;
205
+      /* Get the port pins position */
206
+      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
207
+      if (currentpin == pos)
208
+      {
209
+        pos = pinpos << 2;
210
+        /* Clear the corresponding low control register bits */
211
+        pinmask = ((uint32_t)0x0F) << pos;
212
+        tmpreg &= ~pinmask;
213
+        /* Write the mode configuration in the corresponding bits */
214
+        tmpreg |= (currentmode << pos);
215
+        /* Reset the corresponding ODR bit */
216
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
217
+        {
218
+          GPIOx->BRR = (((uint32_t)0x01) << pinpos);
219
+        }
220
+        else
221
+        {
222
+          /* Set the corresponding ODR bit */
223
+          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
224
+          {
225
+            GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
226
+          }
227
+        }
228
+      }
229
+    }
230
+    GPIOx->CRL = tmpreg;
231
+  }
232
+/*---------------------------- GPIO CRH Configuration ------------------------*/
233
+  /* Configure the eight high port pins */
234
+  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
235
+  {
236
+    tmpreg = GPIOx->CRH;
237
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
238
+    {
239
+      pos = (((uint32_t)0x01) << (pinpos + 0x08));
240
+      /* Get the port pins position */
241
+      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
242
+      if (currentpin == pos)
243
+      {
244
+        pos = pinpos << 2;
245
+        /* Clear the corresponding high control register bits */
246
+        pinmask = ((uint32_t)0x0F) << pos;
247
+        tmpreg &= ~pinmask;
248
+        /* Write the mode configuration in the corresponding bits */
249
+        tmpreg |= (currentmode << pos);
250
+        /* Reset the corresponding ODR bit */
251
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
252
+        {
253
+          GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
254
+        }
255
+        /* Set the corresponding ODR bit */
256
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
257
+        {
258
+          GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
259
+        }
260
+      }
261
+    }
262
+    GPIOx->CRH = tmpreg;
263
+  }
264
+}
265
+
266
+/**
267
+  * @brief  Fills each GPIO_InitStruct member with its default value.
268
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
269
+  *         be initialized.
270
+  * @retval None
271
+  */
272
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
273
+{
274
+  /* Reset GPIO init structure parameters values */
275
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
276
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
277
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
278
+}
279
+
280
+/**
281
+  * @brief  Reads the specified input port pin.
282
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
283
+  * @param  GPIO_Pin:  specifies the port bit to read.
284
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
285
+  * @retval The input port pin value.
286
+  */
287
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
288
+{
289
+  uint8_t bitstatus = 0x00;
290
+  
291
+  /* Check the parameters */
292
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
293
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
294
+  
295
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
296
+  {
297
+    bitstatus = (uint8_t)Bit_SET;
298
+  }
299
+  else
300
+  {
301
+    bitstatus = (uint8_t)Bit_RESET;
302
+  }
303
+  return bitstatus;
304
+}
305
+
306
+/**
307
+  * @brief  Reads the specified GPIO input data port.
308
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
309
+  * @retval GPIO input data port value.
310
+  */
311
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
312
+{
313
+  /* Check the parameters */
314
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
315
+  
316
+  return ((uint16_t)GPIOx->IDR);
317
+}
318
+
319
+/**
320
+  * @brief  Reads the specified output data port bit.
321
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
322
+  * @param  GPIO_Pin:  specifies the port bit to read.
323
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
324
+  * @retval The output port pin value.
325
+  */
326
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
327
+{
328
+  uint8_t bitstatus = 0x00;
329
+  /* Check the parameters */
330
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
331
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
332
+  
333
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
334
+  {
335
+    bitstatus = (uint8_t)Bit_SET;
336
+  }
337
+  else
338
+  {
339
+    bitstatus = (uint8_t)Bit_RESET;
340
+  }
341
+  return bitstatus;
342
+}
343
+
344
+/**
345
+  * @brief  Reads the specified GPIO output data port.
346
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
347
+  * @retval GPIO output data port value.
348
+  */
349
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
350
+{
351
+  /* Check the parameters */
352
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
353
+    
354
+  return ((uint16_t)GPIOx->ODR);
355
+}
356
+
357
+/**
358
+  * @brief  Sets the selected data port bits.
359
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
360
+  * @param  GPIO_Pin: specifies the port bits to be written.
361
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
362
+  * @retval None
363
+  */
364
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
365
+{
366
+  /* Check the parameters */
367
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
368
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
369
+  
370
+  GPIOx->BSRR = GPIO_Pin;
371
+}
372
+
373
+/**
374
+  * @brief  Clears the selected data port bits.
375
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
376
+  * @param  GPIO_Pin: specifies the port bits to be written.
377
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
378
+  * @retval None
379
+  */
380
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
381
+{
382
+  /* Check the parameters */
383
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
384
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
385
+  
386
+  GPIOx->BRR = GPIO_Pin;
387
+}
388
+
389
+/**
390
+  * @brief  Sets or clears the selected data port bit.
391
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
392
+  * @param  GPIO_Pin: specifies the port bit to be written.
393
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
394
+  * @param  BitVal: specifies the value to be written to the selected bit.
395
+  *   This parameter can be one of the BitAction enum values:
396
+  *     @arg Bit_RESET: to clear the port pin
397
+  *     @arg Bit_SET: to set the port pin
398
+  * @retval None
399
+  */
400
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
401
+{
402
+  /* Check the parameters */
403
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
404
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
405
+  assert_param(IS_GPIO_BIT_ACTION(BitVal)); 
406
+  
407
+  if (BitVal != Bit_RESET)
408
+  {
409
+    GPIOx->BSRR = GPIO_Pin;
410
+  }
411
+  else
412
+  {
413
+    GPIOx->BRR = GPIO_Pin;
414
+  }
415
+}
416
+
417
+/**
418
+  * @brief  Writes data to the specified GPIO data port.
419
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
420
+  * @param  PortVal: specifies the value to be written to the port output data register.
421
+  * @retval None
422
+  */
423
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
424
+{
425
+  /* Check the parameters */
426
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
427
+  
428
+  GPIOx->ODR = PortVal;
429
+}
430
+
431
+/**
432
+  * @brief  Locks GPIO Pins configuration registers.
433
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
434
+  * @param  GPIO_Pin: specifies the port bit to be written.
435
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
436
+  * @retval None
437
+  */
438
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
439
+{
440
+  uint32_t tmp = 0x00010000;
441
+  
442
+  /* Check the parameters */
443
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
444
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
445
+  
446
+  tmp |= GPIO_Pin;
447
+  /* Set LCKK bit */
448
+  GPIOx->LCKR = tmp;
449
+  /* Reset LCKK bit */
450
+  GPIOx->LCKR =  GPIO_Pin;
451
+  /* Set LCKK bit */
452
+  GPIOx->LCKR = tmp;
453
+  /* Read LCKK bit*/
454
+  tmp = GPIOx->LCKR;
455
+  /* Read LCKK bit*/
456
+  tmp = GPIOx->LCKR;
457
+}
458
+
459
+/**
460
+  * @brief  Selects the GPIO pin used as Event output.
461
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source
462
+  *   for Event output.
463
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
464
+  * @param  GPIO_PinSource: specifies the pin for the Event output.
465
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
466
+  * @retval None
467
+  */
468
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
469
+{
470
+  uint32_t tmpreg = 0x00;
471
+  /* Check the parameters */
472
+  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
473
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
474
+    
475
+  tmpreg = AFIO->EVCR;
476
+  /* Clear the PORT[6:4] and PIN[3:0] bits */
477
+  tmpreg &= EVCR_PORTPINCONFIG_MASK;
478
+  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
479
+  tmpreg |= GPIO_PinSource;
480
+  AFIO->EVCR = tmpreg;
481
+}
482
+
483
+/**
484
+  * @brief  Enables or disables the Event Output.
485
+  * @param  NewState: new state of the Event output.
486
+  *   This parameter can be: ENABLE or DISABLE.
487
+  * @retval None
488
+  */
489
+void GPIO_EventOutputCmd(FunctionalState NewState)
490
+{
491
+  /* Check the parameters */
492
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
493
+  
494
+  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
495
+}
496
+
497
+/**
498
+  * @brief  Changes the mapping of the specified pin.
499
+  * @param  GPIO_Remap: selects the pin to remap.
500
+  *   This parameter can be one of the following values:
501
+  *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
502
+  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
503
+  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
504
+  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
505
+  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
506
+  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
507
+  *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
508
+  *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
509
+  *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
510
+  *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
511
+  *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
512
+  *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
513
+  *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
514
+  *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
515
+  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
516
+  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
517
+  *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
518
+  *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
519
+  *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
520
+  *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
521
+  *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
522
+  *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
523
+  *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
524
+  *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
525
+  *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
526
+  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
527
+  *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
528
+  *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
529
+  *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
530
+  *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.   
531
+  *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
532
+  *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
533
+  *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to 
534
+  *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.    
535
+  *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
536
+  *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
537
+  *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
538
+  *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
539
+  *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
540
+  *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
541
+  *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
542
+  *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
543
+  *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
544
+  *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
545
+  *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
546
+  *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
547
+  *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
548
+  *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
549
+  *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
550
+  *                                        only for High density Value line devices)     
551
+  * @param  NewState: new state of the port pin remapping.
552
+  *   This parameter can be: ENABLE or DISABLE.
553
+  * @retval None
554
+  */
555
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
556
+{
557
+  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
558
+
559
+  /* Check the parameters */
560
+  assert_param(IS_GPIO_REMAP(GPIO_Remap));
561
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
562
+  
563
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
564
+  {
565
+    tmpreg = AFIO->MAPR2;
566
+  }
567
+  else
568
+  {
569
+    tmpreg = AFIO->MAPR;
570
+  }
571
+
572
+  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
573
+  tmp = GPIO_Remap & LSB_MASK;
574
+
575
+  if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
576
+  {
577
+    tmpreg &= DBGAFR_SWJCFG_MASK;
578
+    AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
579
+  }
580
+  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
581
+  {
582
+    tmp1 = ((uint32_t)0x03) << tmpmask;
583
+    tmpreg &= ~tmp1;
584
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
585
+  }
586
+  else
587
+  {
588
+    tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
589
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
590
+  }
591
+
592
+  if (NewState != DISABLE)
593
+  {
594
+    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
595
+  }
596
+
597
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
598
+  {
599
+    AFIO->MAPR2 = tmpreg;
600
+  }
601
+  else
602
+  {
603
+    AFIO->MAPR = tmpreg;
604
+  }  
605
+}
606
+
607
+/**
608
+  * @brief  Selects the GPIO pin used as EXTI Line.
609
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
610
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
611
+  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
612
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
613
+  * @retval None
614
+  */
615
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
616
+{
617
+  uint32_t tmp = 0x00;
618
+  /* Check the parameters */
619
+  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
620
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
621
+  
622
+  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
623
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
624
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
625
+}
626
+
627
+/**
628
+  * @brief  Selects the Ethernet media interface.
629
+  * @note   This function applies only to STM32 Connectivity line devices.  
630
+  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
631
+  *   This parameter can be one of the following values:
632
+  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
633
+  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
634
+  * @retval None
635
+  */
636
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
637
+{ 
638
+  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
639
+
640
+  /* Configure MII_RMII selection bit */ 
641
+  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
642
+}
643
+  
644
+/**
645
+  * @}
646
+  */
647
+
648
+/**
649
+  * @}
650
+  */
651
+
652
+/**
653
+  * @}
654
+  */
655
+
656
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1337
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
File diff suppressed because it is too large
View File


+ 196
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c View File

@@ -0,0 +1,196 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_iwdg.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the IWDG firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_iwdg.h"
30
+
31
+/** @addtogroup STM32F10x_StdPeriph_Driver
32
+  * @{
33
+  */
34
+
35
+/** @defgroup IWDG 
36
+  * @brief IWDG driver modules
37
+  * @{
38
+  */ 
39
+
40
+/** @defgroup IWDG_Private_TypesDefinitions
41
+  * @{
42
+  */
43
+
44
+/**
45
+  * @}
46
+  */
47
+
48
+/** @defgroup IWDG_Private_Defines
49
+  * @{
50
+  */ 
51
+
52
+/* ---------------------- IWDG registers bit mask ----------------------------*/
53
+
54
+/* KR register bit mask */
55
+#define KR_KEY_Reload    ((uint16_t)0xAAAA)
56
+#define KR_KEY_Enable    ((uint16_t)0xCCCC)
57
+
58
+/**
59
+  * @}
60
+  */ 
61
+
62
+/** @defgroup IWDG_Private_Macros
63
+  * @{
64
+  */
65
+
66
+/**
67
+  * @}
68
+  */
69
+
70
+/** @defgroup IWDG_Private_Variables
71
+  * @{
72
+  */
73
+
74
+/**
75
+  * @}
76
+  */
77
+
78
+/** @defgroup IWDG_Private_FunctionPrototypes
79
+  * @{
80
+  */
81
+
82
+/**
83
+  * @}
84
+  */
85
+
86
+/** @defgroup IWDG_Private_Functions
87
+  * @{
88
+  */
89
+
90
+/**
91
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
92
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
93
+  *   This parameter can be one of the following values:
94
+  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
95
+  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
96
+  * @retval None
97
+  */
98
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
99
+{
100
+  /* Check the parameters */
101
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
102
+  IWDG->KR = IWDG_WriteAccess;
103
+}
104
+
105
+/**
106
+  * @brief  Sets IWDG Prescaler value.
107
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
108
+  *   This parameter can be one of the following values:
109
+  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
110
+  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
111
+  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
112
+  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
113
+  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
114
+  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
115
+  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
116
+  * @retval None
117
+  */
118
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
119
+{
120
+  /* Check the parameters */
121
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
122
+  IWDG->PR = IWDG_Prescaler;
123
+}
124
+
125
+/**
126
+  * @brief  Sets IWDG Reload value.
127
+  * @param  Reload: specifies the IWDG Reload value.
128
+  *   This parameter must be a number between 0 and 0x0FFF.
129
+  * @retval None
130
+  */
131
+void IWDG_SetReload(uint16_t Reload)
132
+{
133
+  /* Check the parameters */
134
+  assert_param(IS_IWDG_RELOAD(Reload));
135
+  IWDG->RLR = Reload;
136
+}
137
+
138
+/**
139
+  * @brief  Reloads IWDG counter with value defined in the reload register
140
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
141
+  * @param  None
142
+  * @retval None
143
+  */
144
+void IWDG_ReloadCounter(void)
145
+{
146
+  IWDG->KR = KR_KEY_Reload;
147
+}
148
+
149
+/**
150
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
151
+  * @param  None
152
+  * @retval None
153
+  */
154
+void IWDG_Enable(void)
155
+{
156
+  IWDG->KR = KR_KEY_Enable;
157
+}
158
+
159
+/**
160
+  * @brief  Checks whether the specified IWDG flag is set or not.
161
+  * @param  IWDG_FLAG: specifies the flag to check.
162
+  *   This parameter can be one of the following values:
163
+  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
164
+  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
165
+  * @retval The new state of IWDG_FLAG (SET or RESET).
166
+  */
167
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
168
+{
169
+  FlagStatus bitstatus = RESET;
170
+  /* Check the parameters */
171
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
172
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
173
+  {
174
+    bitstatus = SET;
175
+  }
176
+  else
177
+  {
178
+    bitstatus = RESET;
179
+  }
180
+  /* Return the flag status */
181
+  return bitstatus;
182
+}
183
+
184
+/**
185
+  * @}
186
+  */
187
+
188
+/**
189
+  * @}
190
+  */
191
+
192
+/**
193
+  * @}
194
+  */
195
+
196
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 313
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c View File

@@ -0,0 +1,313 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_pwr.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the PWR firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_pwr.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup PWR 
37
+  * @brief PWR driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup PWR_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+/** @defgroup PWR_Private_Defines
50
+  * @{
51
+  */
52
+
53
+/* --------- PWR registers bit address in the alias region ---------- */
54
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
55
+
56
+/* --- CR Register ---*/
57
+
58
+/* Alias word address of DBP bit */
59
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
60
+#define DBP_BitNumber            0x08
61
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
62
+
63
+/* Alias word address of PVDE bit */
64
+#define PVDE_BitNumber           0x04
65
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
66
+
67
+/* --- CSR Register ---*/
68
+
69
+/* Alias word address of EWUP bit */
70
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
71
+#define EWUP_BitNumber           0x08
72
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
73
+
74
+/* ------------------ PWR registers bit mask ------------------------ */
75
+
76
+/* CR register bit mask */
77
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
78
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
79
+
80
+
81
+/**
82
+  * @}
83
+  */
84
+
85
+/** @defgroup PWR_Private_Macros
86
+  * @{
87
+  */
88
+
89
+/**
90
+  * @}
91
+  */
92
+
93
+/** @defgroup PWR_Private_Variables
94
+  * @{
95
+  */
96
+
97
+/**
98
+  * @}
99
+  */
100
+
101
+/** @defgroup PWR_Private_FunctionPrototypes
102
+  * @{
103
+  */
104
+
105
+/**
106
+  * @}
107
+  */
108
+
109
+/** @defgroup PWR_Private_Functions
110
+  * @{
111
+  */
112
+
113
+/**
114
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
115
+  * @param  None
116
+  * @retval None
117
+  */
118
+void PWR_DeInit(void)
119
+{
120
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
121
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
122
+}
123
+
124
+/**
125
+  * @brief  Enables or disables access to the RTC and backup registers.
126
+  * @param  NewState: new state of the access to the RTC and backup registers.
127
+  *   This parameter can be: ENABLE or DISABLE.
128
+  * @retval None
129
+  */
130
+void PWR_BackupAccessCmd(FunctionalState NewState)
131
+{
132
+  /* Check the parameters */
133
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
134
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
135
+}
136
+
137
+/**
138
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
139
+  * @param  NewState: new state of the PVD.
140
+  *   This parameter can be: ENABLE or DISABLE.
141
+  * @retval None
142
+  */
143
+void PWR_PVDCmd(FunctionalState NewState)
144
+{
145
+  /* Check the parameters */
146
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
147
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
148
+}
149
+
150
+/**
151
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
152
+  * @param  PWR_PVDLevel: specifies the PVD detection level
153
+  *   This parameter can be one of the following values:
154
+  *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
155
+  *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
156
+  *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
157
+  *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
158
+  *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
159
+  *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
160
+  *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
161
+  *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
162
+  * @retval None
163
+  */
164
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
165
+{
166
+  uint32_t tmpreg = 0;
167
+  /* Check the parameters */
168
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
169
+  tmpreg = PWR->CR;
170
+  /* Clear PLS[7:5] bits */
171
+  tmpreg &= CR_PLS_MASK;
172
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
173
+  tmpreg |= PWR_PVDLevel;
174
+  /* Store the new value */
175
+  PWR->CR = tmpreg;
176
+}
177
+
178
+/**
179
+  * @brief  Enables or disables the WakeUp Pin functionality.
180
+  * @param  NewState: new state of the WakeUp Pin functionality.
181
+  *   This parameter can be: ENABLE or DISABLE.
182
+  * @retval None
183
+  */
184
+void PWR_WakeUpPinCmd(FunctionalState NewState)
185
+{
186
+  /* Check the parameters */
187
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
188
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
189
+}
190
+
191
+/**
192
+  * @brief  Enters STOP mode.
193
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
194
+  *   This parameter can be one of the following values:
195
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
196
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
197
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
198
+  *   This parameter can be one of the following values:
199
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
200
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
201
+  * @retval None
202
+  */
203
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
204
+{
205
+  uint32_t tmpreg = 0;
206
+  /* Check the parameters */
207
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
208
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
209
+  
210
+  /* Select the regulator state in STOP mode ---------------------------------*/
211
+  tmpreg = PWR->CR;
212
+  /* Clear PDDS and LPDS bits */
213
+  tmpreg &= CR_DS_MASK;
214
+  /* Set LPDS bit according to PWR_Regulator value */
215
+  tmpreg |= PWR_Regulator;
216
+  /* Store the new value */
217
+  PWR->CR = tmpreg;
218
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
219
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
220
+  
221
+  /* Select STOP mode entry --------------------------------------------------*/
222
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
223
+  {   
224
+    /* Request Wait For Interrupt */
225
+    __WFI();
226
+  }
227
+  else
228
+  {
229
+    /* Request Wait For Event */
230
+    __WFE();
231
+  }
232
+  
233
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
234
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
235
+}
236
+
237
+/**
238
+  * @brief  Enters STANDBY mode.
239
+  * @param  None
240
+  * @retval None
241
+  */
242
+void PWR_EnterSTANDBYMode(void)
243
+{
244
+  /* Clear Wake-up flag */
245
+  PWR->CR |= PWR_CR_CWUF;
246
+  /* Select STANDBY mode */
247
+  PWR->CR |= PWR_CR_PDDS;
248
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
249
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
250
+/* This option is used to ensure that store operations are completed */
251
+#if defined ( __CC_ARM   )
252
+  __force_stores();
253
+#endif
254
+  /* Request Wait For Interrupt */
255
+  __WFI();
256
+}
257
+
258
+/**
259
+  * @brief  Checks whether the specified PWR flag is set or not.
260
+  * @param  PWR_FLAG: specifies the flag to check.
261
+  *   This parameter can be one of the following values:
262
+  *     @arg PWR_FLAG_WU: Wake Up flag
263
+  *     @arg PWR_FLAG_SB: StandBy flag
264
+  *     @arg PWR_FLAG_PVDO: PVD Output
265
+  * @retval The new state of PWR_FLAG (SET or RESET).
266
+  */
267
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
268
+{
269
+  FlagStatus bitstatus = RESET;
270
+  /* Check the parameters */
271
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
272
+  
273
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
274
+  {
275
+    bitstatus = SET;
276
+  }
277
+  else
278
+  {
279
+    bitstatus = RESET;
280
+  }
281
+  /* Return the flag status */
282
+  return bitstatus;
283
+}
284
+
285
+/**
286
+  * @brief  Clears the PWR's pending flags.
287
+  * @param  PWR_FLAG: specifies the flag to clear.
288
+  *   This parameter can be one of the following values:
289
+  *     @arg PWR_FLAG_WU: Wake Up flag
290
+  *     @arg PWR_FLAG_SB: StandBy flag
291
+  * @retval None
292
+  */
293
+void PWR_ClearFlag(uint32_t PWR_FLAG)
294
+{
295
+  /* Check the parameters */
296
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
297
+         
298
+  PWR->CR |=  PWR_FLAG << 2;
299
+}
300
+
301
+/**
302
+  * @}
303
+  */
304
+
305
+/**
306
+  * @}
307
+  */
308
+
309
+/**
310
+  * @}
311
+  */
312
+
313
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1476
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
File diff suppressed because it is too large
View File


+ 358
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c View File

@@ -0,0 +1,358 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_rtc.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the RTC firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_rtc.h"
30
+
31
+/** @addtogroup STM32F10x_StdPeriph_Driver
32
+  * @{
33
+  */
34
+
35
+/** @defgroup RTC 
36
+  * @brief RTC driver modules
37
+  * @{
38
+  */
39
+
40
+/** @defgroup RTC_Private_TypesDefinitions
41
+  * @{
42
+  */ 
43
+/**
44
+  * @}
45
+  */
46
+
47
+/** @defgroup RTC_Private_Defines
48
+  * @{
49
+  */
50
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
51
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
52
+
53
+/**
54
+  * @}
55
+  */
56
+
57
+/** @defgroup RTC_Private_Macros
58
+  * @{
59
+  */
60
+
61
+/**
62
+  * @}
63
+  */
64
+
65
+/** @defgroup RTC_Private_Variables
66
+  * @{
67
+  */
68
+
69
+/**
70
+  * @}
71
+  */
72
+
73
+/** @defgroup RTC_Private_FunctionPrototypes
74
+  * @{
75
+  */
76
+
77
+/**
78
+  * @}
79
+  */
80
+
81
+/** @defgroup RTC_Private_Functions
82
+  * @{
83
+  */
84
+
85
+/**
86
+  * @brief  Enables or disables the specified RTC interrupts.
87
+  * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
88
+  *   This parameter can be any combination of the following values:
89
+  *     @arg RTC_IT_OW: Overflow interrupt
90
+  *     @arg RTC_IT_ALR: Alarm interrupt
91
+  *     @arg RTC_IT_SEC: Second interrupt
92
+  * @param  NewState: new state of the specified RTC interrupts.
93
+  *   This parameter can be: ENABLE or DISABLE.
94
+  * @retval None
95
+  */
96
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
97
+{
98
+  /* Check the parameters */
99
+  assert_param(IS_RTC_IT(RTC_IT));  
100
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
101
+  
102
+  if (NewState != DISABLE)
103
+  {
104
+    RTC->CRH |= RTC_IT;
105
+  }
106
+  else
107
+  {
108
+    RTC->CRH &= (uint16_t)~RTC_IT;
109
+  }
110
+}
111
+
112
+/**
113
+  * @brief  Enters the RTC configuration mode.
114
+  * @param  None
115
+  * @retval None
116
+  */
117
+void RTC_EnterConfigMode(void)
118
+{
119
+  /* Set the CNF flag to enter in the Configuration Mode */
120
+  RTC->CRL |= RTC_CRL_CNF;
121
+}
122
+
123
+/**
124
+  * @brief  Exits from the RTC configuration mode.
125
+  * @param  None
126
+  * @retval None
127
+  */
128
+void RTC_ExitConfigMode(void)
129
+{
130
+  /* Reset the CNF flag to exit from the Configuration Mode */
131
+  RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 
132
+}
133
+
134
+/**
135
+  * @brief  Gets the RTC counter value.
136
+  * @param  None
137
+  * @retval RTC counter value.
138
+  */
139
+uint32_t RTC_GetCounter(void)
140
+{
141
+  uint16_t high1 = 0, high2 = 0, low = 0;
142
+
143
+  high1 = RTC->CNTH;
144
+  low   = RTC->CNTL;
145
+  high2 = RTC->CNTH;
146
+
147
+  if (high1 != high2)
148
+  { /* In this case the counter roll over during reading of CNTL and CNTH registers, 
149
+       read again CNTL register then return the counter value */
150
+    return (((uint32_t) high2 << 16 ) | RTC->CNTL);
151
+  }
152
+  else
153
+  { /* No counter roll over during reading of CNTL and CNTH registers, counter 
154
+       value is equal to first value of CNTL and CNTH */
155
+    return (((uint32_t) high1 << 16 ) | low);
156
+  }
157
+}
158
+
159
+/**
160
+  * @brief  Sets the RTC counter value.
161
+  * @param  CounterValue: RTC counter new value.
162
+  * @retval None
163
+  */
164
+void RTC_SetCounter(uint32_t CounterValue)
165
+{ 
166
+  RTC_EnterConfigMode();
167
+  /* Set RTC COUNTER MSB word */
168
+  RTC->CNTH = CounterValue >> 16;
169
+  /* Set RTC COUNTER LSB word */
170
+  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
171
+  RTC_ExitConfigMode();
172
+}
173
+
174
+/**
175
+  * @brief  Sets the RTC prescaler value.
176
+  * @param  PrescalerValue: RTC prescaler new value.
177
+  * @retval None
178
+  */
179
+void RTC_SetPrescaler(uint32_t PrescalerValue)
180
+{
181
+  /* Check the parameters */
182
+  assert_param(IS_RTC_PRESCALER(PrescalerValue));
183
+  
184
+  RTC_EnterConfigMode();
185
+  /* Set RTC PRESCALER MSB word */
186
+  RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
187
+  /* Set RTC PRESCALER LSB word */
188
+  RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
189
+  RTC_ExitConfigMode();
190
+}
191
+
192
+/**
193
+  * @brief  Sets the RTC alarm value.
194
+  * @param  AlarmValue: RTC alarm new value.
195
+  * @retval None
196
+  */
197
+void RTC_SetAlarm(uint32_t AlarmValue)
198
+{  
199
+  RTC_EnterConfigMode();
200
+  /* Set the ALARM MSB word */
201
+  RTC->ALRH = AlarmValue >> 16;
202
+  /* Set the ALARM LSB word */
203
+  RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
204
+  RTC_ExitConfigMode();
205
+}
206
+
207
+/**
208
+  * @brief  Gets the RTC divider value.
209
+  * @param  None
210
+  * @retval RTC Divider value.
211
+  */
212
+uint32_t RTC_GetDivider(void)
213
+{
214
+  uint32_t tmp = 0x00;
215
+  tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
216
+  tmp |= RTC->DIVL;
217
+  return tmp;
218
+}
219
+
220
+/**
221
+  * @brief  Waits until last write operation on RTC registers has finished.
222
+  * @note   This function must be called before any write to RTC registers.
223
+  * @param  None
224
+  * @retval None
225
+  */
226
+void RTC_WaitForLastTask(void)
227
+{
228
+  /* Loop until RTOFF flag is set */
229
+  while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
230
+  {
231
+  }
232
+}
233
+
234
+/**
235
+  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
236
+  *   are synchronized with RTC APB clock.
237
+  * @note   This function must be called before any read operation after an APB reset
238
+  *   or an APB clock stop.
239
+  * @param  None
240
+  * @retval None
241
+  */
242
+void RTC_WaitForSynchro(void)
243
+{
244
+  /* Clear RSF flag */
245
+  RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
246
+  /* Loop until RSF flag is set */
247
+  while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
248
+  {
249
+  }
250
+}
251
+
252
+/**
253
+  * @brief  Checks whether the specified RTC flag is set or not.
254
+  * @param  RTC_FLAG: specifies the flag to check.
255
+  *   This parameter can be one the following values:
256
+  *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
257
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
258
+  *     @arg RTC_FLAG_OW: Overflow flag
259
+  *     @arg RTC_FLAG_ALR: Alarm flag
260
+  *     @arg RTC_FLAG_SEC: Second flag
261
+  * @retval The new state of RTC_FLAG (SET or RESET).
262
+  */
263
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
264
+{
265
+  FlagStatus bitstatus = RESET;
266
+  
267
+  /* Check the parameters */
268
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 
269
+  
270
+  if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
271
+  {
272
+    bitstatus = SET;
273
+  }
274
+  else
275
+  {
276
+    bitstatus = RESET;
277
+  }
278
+  return bitstatus;
279
+}
280
+
281
+/**
282
+  * @brief  Clears the RTC's pending flags.
283
+  * @param  RTC_FLAG: specifies the flag to clear.
284
+  *   This parameter can be any combination of the following values:
285
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
286
+  *                        an APB reset or an APB Clock stop.
287
+  *     @arg RTC_FLAG_OW: Overflow flag
288
+  *     @arg RTC_FLAG_ALR: Alarm flag
289
+  *     @arg RTC_FLAG_SEC: Second flag
290
+  * @retval None
291
+  */
292
+void RTC_ClearFlag(uint16_t RTC_FLAG)
293
+{
294
+  /* Check the parameters */
295
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
296
+    
297
+  /* Clear the corresponding RTC flag */
298
+  RTC->CRL &= (uint16_t)~RTC_FLAG;
299
+}
300
+
301
+/**
302
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
303
+  * @param  RTC_IT: specifies the RTC interrupts sources to check.
304
+  *   This parameter can be one of the following values:
305
+  *     @arg RTC_IT_OW: Overflow interrupt
306
+  *     @arg RTC_IT_ALR: Alarm interrupt
307
+  *     @arg RTC_IT_SEC: Second interrupt
308
+  * @retval The new state of the RTC_IT (SET or RESET).
309
+  */
310
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
311
+{
312
+  ITStatus bitstatus = RESET;
313
+  /* Check the parameters */
314
+  assert_param(IS_RTC_GET_IT(RTC_IT)); 
315
+  
316
+  bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
317
+  if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
318
+  {
319
+    bitstatus = SET;
320
+  }
321
+  else
322
+  {
323
+    bitstatus = RESET;
324
+  }
325
+  return bitstatus;
326
+}
327
+
328
+/**
329
+  * @brief  Clears the RTC's interrupt pending bits.
330
+  * @param  RTC_IT: specifies the interrupt pending bit to clear.
331
+  *   This parameter can be any combination of the following values:
332
+  *     @arg RTC_IT_OW: Overflow interrupt
333
+  *     @arg RTC_IT_ALR: Alarm interrupt
334
+  *     @arg RTC_IT_SEC: Second interrupt
335
+  * @retval None
336
+  */
337
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
338
+{
339
+  /* Check the parameters */
340
+  assert_param(IS_RTC_IT(RTC_IT));  
341
+  
342
+  /* Clear the corresponding RTC pending bit */
343
+  RTC->CRL &= (uint16_t)~RTC_IT;
344
+}
345
+
346
+/**
347
+  * @}
348
+  */
349
+
350
+/**
351
+  * @}
352
+  */
353
+
354
+/**
355
+  * @}
356
+  */
357
+
358
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 804
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c View File

@@ -0,0 +1,804 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_sdio.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the SDIO firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_sdio.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup SDIO 
37
+  * @brief SDIO driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup SDIO_Private_TypesDefinitions
42
+  * @{
43
+  */ 
44
+
45
+/* ------------ SDIO registers bit address in the alias region ----------- */
46
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
47
+
48
+/* --- CLKCR Register ---*/
49
+
50
+/* Alias word address of CLKEN bit */
51
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
52
+#define CLKEN_BitNumber           0x08
53
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
54
+
55
+/* --- CMD Register ---*/
56
+
57
+/* Alias word address of SDIOSUSPEND bit */
58
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
59
+#define SDIOSUSPEND_BitNumber     0x0B
60
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
61
+
62
+/* Alias word address of ENCMDCOMPL bit */
63
+#define ENCMDCOMPL_BitNumber      0x0C
64
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
65
+
66
+/* Alias word address of NIEN bit */
67
+#define NIEN_BitNumber            0x0D
68
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
69
+
70
+/* Alias word address of ATACMD bit */
71
+#define ATACMD_BitNumber          0x0E
72
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
73
+
74
+/* --- DCTRL Register ---*/
75
+
76
+/* Alias word address of DMAEN bit */
77
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
78
+#define DMAEN_BitNumber           0x03
79
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
80
+
81
+/* Alias word address of RWSTART bit */
82
+#define RWSTART_BitNumber         0x08
83
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
84
+
85
+/* Alias word address of RWSTOP bit */
86
+#define RWSTOP_BitNumber          0x09
87
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
88
+
89
+/* Alias word address of RWMOD bit */
90
+#define RWMOD_BitNumber           0x0A
91
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
92
+
93
+/* Alias word address of SDIOEN bit */
94
+#define SDIOEN_BitNumber          0x0B
95
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
96
+
97
+/* ---------------------- SDIO registers bit mask ------------------------ */
98
+
99
+/* --- CLKCR Register ---*/
100
+
101
+/* CLKCR register clear mask */
102
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
103
+
104
+/* --- PWRCTRL Register ---*/
105
+
106
+/* SDIO PWRCTRL Mask */
107
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
108
+
109
+/* --- DCTRL Register ---*/
110
+
111
+/* SDIO DCTRL Clear Mask */
112
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
113
+
114
+/* --- CMD Register ---*/
115
+
116
+/* CMD Register clear mask */
117
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
118
+
119
+/* SDIO RESP Registers Address */
120
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
121
+
122
+/**
123
+  * @}
124
+  */
125
+
126
+/** @defgroup SDIO_Private_Defines
127
+  * @{
128
+  */
129
+
130
+/**
131
+  * @}
132
+  */
133
+
134
+/** @defgroup SDIO_Private_Macros
135
+  * @{
136
+  */
137
+
138
+/**
139
+  * @}
140
+  */
141
+
142
+/** @defgroup SDIO_Private_Variables
143
+  * @{
144
+  */
145
+
146
+/**
147
+  * @}
148
+  */
149
+
150
+/** @defgroup SDIO_Private_FunctionPrototypes
151
+  * @{
152
+  */
153
+
154
+/**
155
+  * @}
156
+  */
157
+
158
+/** @defgroup SDIO_Private_Functions
159
+  * @{
160
+  */
161
+
162
+/**
163
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
164
+  * @param  None
165
+  * @retval None
166
+  */
167
+void SDIO_DeInit(void)
168
+{
169
+  SDIO->POWER = 0x00000000;
170
+  SDIO->CLKCR = 0x00000000;
171
+  SDIO->ARG = 0x00000000;
172
+  SDIO->CMD = 0x00000000;
173
+  SDIO->DTIMER = 0x00000000;
174
+  SDIO->DLEN = 0x00000000;
175
+  SDIO->DCTRL = 0x00000000;
176
+  SDIO->ICR = 0x00C007FF;
177
+  SDIO->MASK = 0x00000000;
178
+}
179
+
180
+/**
181
+  * @brief  Initializes the SDIO peripheral according to the specified 
182
+  *         parameters in the SDIO_InitStruct.
183
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
184
+  *         that contains the configuration information for the SDIO peripheral.
185
+  * @retval None
186
+  */
187
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
188
+{
189
+  uint32_t tmpreg = 0;
190
+    
191
+  /* Check the parameters */
192
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
193
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
194
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
195
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
196
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
197
+   
198
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
199
+  /* Get the SDIO CLKCR value */
200
+  tmpreg = SDIO->CLKCR;
201
+  
202
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
203
+  tmpreg &= CLKCR_CLEAR_MASK;
204
+  
205
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
206
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
207
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
208
+  /* Set WIDBUS bits according to SDIO_BusWide value */
209
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
210
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
211
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
212
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
213
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
214
+  
215
+  /* Write to SDIO CLKCR */
216
+  SDIO->CLKCR = tmpreg;
217
+}
218
+
219
+/**
220
+  * @brief  Fills each SDIO_InitStruct member with its default value.
221
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
222
+  *   will be initialized.
223
+  * @retval None
224
+  */
225
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
226
+{
227
+  /* SDIO_InitStruct members default value */
228
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
229
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
230
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
231
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
232
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
233
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
234
+}
235
+
236
+/**
237
+  * @brief  Enables or disables the SDIO Clock.
238
+  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
239
+  * @retval None
240
+  */
241
+void SDIO_ClockCmd(FunctionalState NewState)
242
+{
243
+  /* Check the parameters */
244
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
245
+  
246
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
247
+}
248
+
249
+/**
250
+  * @brief  Sets the power status of the controller.
251
+  * @param  SDIO_PowerState: new state of the Power state. 
252
+  *   This parameter can be one of the following values:
253
+  *     @arg SDIO_PowerState_OFF
254
+  *     @arg SDIO_PowerState_ON
255
+  * @retval None
256
+  */
257
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
258
+{
259
+  /* Check the parameters */
260
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
261
+  
262
+  SDIO->POWER = SDIO_PowerState;
263
+}
264
+
265
+/**
266
+  * @brief  Gets the power status of the controller.
267
+  * @param  None
268
+  * @retval Power status of the controller. The returned value can
269
+  *   be one of the following:
270
+  * - 0x00: Power OFF
271
+  * - 0x02: Power UP
272
+  * - 0x03: Power ON 
273
+  */
274
+uint32_t SDIO_GetPowerState(void)
275
+{
276
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
277
+}
278
+
279
+/**
280
+  * @brief  Enables or disables the SDIO interrupts.
281
+  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
282
+  *   This parameter can be one or a combination of the following values:
283
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
284
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
285
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
286
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
287
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
288
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
289
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
290
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
291
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
292
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
293
+  *                            bus mode interrupt
294
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
295
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
296
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
297
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
298
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
299
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
300
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
301
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
302
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
303
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
304
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
305
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
306
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
307
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
308
+  * @param  NewState: new state of the specified SDIO interrupts.
309
+  *   This parameter can be: ENABLE or DISABLE.
310
+  * @retval None 
311
+  */
312
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
313
+{
314
+  /* Check the parameters */
315
+  assert_param(IS_SDIO_IT(SDIO_IT));
316
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
317
+  
318
+  if (NewState != DISABLE)
319
+  {
320
+    /* Enable the SDIO interrupts */
321
+    SDIO->MASK |= SDIO_IT;
322
+  }
323
+  else
324
+  {
325
+    /* Disable the SDIO interrupts */
326
+    SDIO->MASK &= ~SDIO_IT;
327
+  } 
328
+}
329
+
330
+/**
331
+  * @brief  Enables or disables the SDIO DMA request.
332
+  * @param  NewState: new state of the selected SDIO DMA request.
333
+  *   This parameter can be: ENABLE or DISABLE.
334
+  * @retval None
335
+  */
336
+void SDIO_DMACmd(FunctionalState NewState)
337
+{
338
+  /* Check the parameters */
339
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
340
+  
341
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
342
+}
343
+
344
+/**
345
+  * @brief  Initializes the SDIO Command according to the specified 
346
+  *         parameters in the SDIO_CmdInitStruct and send the command.
347
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
348
+  *         structure that contains the configuration information for the SDIO command.
349
+  * @retval None
350
+  */
351
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
352
+{
353
+  uint32_t tmpreg = 0;
354
+  
355
+  /* Check the parameters */
356
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
357
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
358
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
359
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
360
+  
361
+/*---------------------------- SDIO ARG Configuration ------------------------*/
362
+  /* Set the SDIO Argument value */
363
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
364
+  
365
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
366
+  /* Get the SDIO CMD value */
367
+  tmpreg = SDIO->CMD;
368
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
369
+  tmpreg &= CMD_CLEAR_MASK;
370
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
371
+  /* Set WAITRESP bits according to SDIO_Response value */
372
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
373
+  /* Set CPSMEN bits according to SDIO_CPSM value */
374
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
375
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
376
+  
377
+  /* Write to SDIO CMD */
378
+  SDIO->CMD = tmpreg;
379
+}
380
+
381
+/**
382
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
383
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
384
+  *         structure which will be initialized.
385
+  * @retval None
386
+  */
387
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
388
+{
389
+  /* SDIO_CmdInitStruct members default value */
390
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
391
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
392
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
393
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
394
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
395
+}
396
+
397
+/**
398
+  * @brief  Returns command index of last command for which response received.
399
+  * @param  None
400
+  * @retval Returns the command index of the last command response received.
401
+  */
402
+uint8_t SDIO_GetCommandResponse(void)
403
+{
404
+  return (uint8_t)(SDIO->RESPCMD);
405
+}
406
+
407
+/**
408
+  * @brief  Returns response received from the card for the last command.
409
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
410
+  *   This parameter can be one of the following values:
411
+  *     @arg SDIO_RESP1: Response Register 1
412
+  *     @arg SDIO_RESP2: Response Register 2
413
+  *     @arg SDIO_RESP3: Response Register 3
414
+  *     @arg SDIO_RESP4: Response Register 4
415
+  * @retval The Corresponding response register value.
416
+  */
417
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
418
+{
419
+  __IO uint32_t tmp = 0;
420
+
421
+  /* Check the parameters */
422
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
423
+
424
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
425
+  
426
+  return (*(__IO uint32_t *) tmp); 
427
+}
428
+
429
+/**
430
+  * @brief  Initializes the SDIO data path according to the specified 
431
+  *   parameters in the SDIO_DataInitStruct.
432
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
433
+  *   contains the configuration information for the SDIO command.
434
+  * @retval None
435
+  */
436
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
437
+{
438
+  uint32_t tmpreg = 0;
439
+  
440
+  /* Check the parameters */
441
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
442
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
443
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
444
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
445
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
446
+
447
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
448
+  /* Set the SDIO Data TimeOut value */
449
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
450
+
451
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
452
+  /* Set the SDIO DataLength value */
453
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
454
+
455
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
456
+  /* Get the SDIO DCTRL value */
457
+  tmpreg = SDIO->DCTRL;
458
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
459
+  tmpreg &= DCTRL_CLEAR_MASK;
460
+  /* Set DEN bit according to SDIO_DPSM value */
461
+  /* Set DTMODE bit according to SDIO_TransferMode value */
462
+  /* Set DTDIR bit according to SDIO_TransferDir value */
463
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
464
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
465
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
466
+
467
+  /* Write to SDIO DCTRL */
468
+  SDIO->DCTRL = tmpreg;
469
+}
470
+
471
+/**
472
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
473
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
474
+  *         will be initialized.
475
+  * @retval None
476
+  */
477
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
478
+{
479
+  /* SDIO_DataInitStruct members default value */
480
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
481
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
482
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
483
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
484
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
485
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
486
+}
487
+
488
+/**
489
+  * @brief  Returns number of remaining data bytes to be transferred.
490
+  * @param  None
491
+  * @retval Number of remaining data bytes to be transferred
492
+  */
493
+uint32_t SDIO_GetDataCounter(void)
494
+{ 
495
+  return SDIO->DCOUNT;
496
+}
497
+
498
+/**
499
+  * @brief  Read one data word from Rx FIFO.
500
+  * @param  None
501
+  * @retval Data received
502
+  */
503
+uint32_t SDIO_ReadData(void)
504
+{ 
505
+  return SDIO->FIFO;
506
+}
507
+
508
+/**
509
+  * @brief  Write one data word to Tx FIFO.
510
+  * @param  Data: 32-bit data word to write.
511
+  * @retval None
512
+  */
513
+void SDIO_WriteData(uint32_t Data)
514
+{ 
515
+  SDIO->FIFO = Data;
516
+}
517
+
518
+/**
519
+  * @brief  Returns the number of words left to be written to or read from FIFO.	
520
+  * @param  None
521
+  * @retval Remaining number of words.
522
+  */
523
+uint32_t SDIO_GetFIFOCount(void)
524
+{ 
525
+  return SDIO->FIFOCNT;
526
+}
527
+
528
+/**
529
+  * @brief  Starts the SD I/O Read Wait operation.	
530
+  * @param  NewState: new state of the Start SDIO Read Wait operation. 
531
+  *   This parameter can be: ENABLE or DISABLE.
532
+  * @retval None
533
+  */
534
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
535
+{ 
536
+  /* Check the parameters */
537
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
538
+  
539
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
540
+}
541
+
542
+/**
543
+  * @brief  Stops the SD I/O Read Wait operation.	
544
+  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
545
+  *   This parameter can be: ENABLE or DISABLE.
546
+  * @retval None
547
+  */
548
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
549
+{ 
550
+  /* Check the parameters */
551
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
552
+  
553
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
554
+}
555
+
556
+/**
557
+  * @brief  Sets one of the two options of inserting read wait interval.
558
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
559
+  *   This parameter can be:
560
+  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
561
+  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
562
+  * @retval None
563
+  */
564
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
565
+{
566
+  /* Check the parameters */
567
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
568
+  
569
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
570
+}
571
+
572
+/**
573
+  * @brief  Enables or disables the SD I/O Mode Operation.
574
+  * @param  NewState: new state of SDIO specific operation. 
575
+  *   This parameter can be: ENABLE or DISABLE.
576
+  * @retval None
577
+  */
578
+void SDIO_SetSDIOOperation(FunctionalState NewState)
579
+{ 
580
+  /* Check the parameters */
581
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
582
+  
583
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
584
+}
585
+
586
+/**
587
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
588
+  * @param  NewState: new state of the SD I/O Mode suspend command.
589
+  *   This parameter can be: ENABLE or DISABLE.
590
+  * @retval None
591
+  */
592
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
593
+{ 
594
+  /* Check the parameters */
595
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
596
+  
597
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
598
+}
599
+
600
+/**
601
+  * @brief  Enables or disables the command completion signal.
602
+  * @param  NewState: new state of command completion signal. 
603
+  *   This parameter can be: ENABLE or DISABLE.
604
+  * @retval None
605
+  */
606
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
607
+{ 
608
+  /* Check the parameters */
609
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
610
+  
611
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
612
+}
613
+
614
+/**
615
+  * @brief  Enables or disables the CE-ATA interrupt.
616
+  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
617
+  * @retval None
618
+  */
619
+void SDIO_CEATAITCmd(FunctionalState NewState)
620
+{ 
621
+  /* Check the parameters */
622
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
623
+  
624
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
625
+}
626
+
627
+/**
628
+  * @brief  Sends CE-ATA command (CMD61).
629
+  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
630
+  * @retval None
631
+  */
632
+void SDIO_SendCEATACmd(FunctionalState NewState)
633
+{ 
634
+  /* Check the parameters */
635
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
636
+  
637
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
638
+}
639
+
640
+/**
641
+  * @brief  Checks whether the specified SDIO flag is set or not.
642
+  * @param  SDIO_FLAG: specifies the flag to check. 
643
+  *   This parameter can be one of the following values:
644
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
645
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
646
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
647
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
648
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
649
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
650
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
651
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
652
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
653
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
654
+  *                              bus mode.
655
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
656
+  *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
657
+  *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
658
+  *     @arg SDIO_FLAG_RXACT:    Data receive in progress
659
+  *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
660
+  *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
661
+  *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
662
+  *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
663
+  *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
664
+  *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
665
+  *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
666
+  *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
667
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
668
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
669
+  * @retval The new state of SDIO_FLAG (SET or RESET).
670
+  */
671
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
672
+{ 
673
+  FlagStatus bitstatus = RESET;
674
+  
675
+  /* Check the parameters */
676
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
677
+  
678
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
679
+  {
680
+    bitstatus = SET;
681
+  }
682
+  else
683
+  {
684
+    bitstatus = RESET;
685
+  }
686
+  return bitstatus;
687
+}
688
+
689
+/**
690
+  * @brief  Clears the SDIO's pending flags.
691
+  * @param  SDIO_FLAG: specifies the flag to clear.  
692
+  *   This parameter can be one or a combination of the following values:
693
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
694
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
695
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
696
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
697
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
698
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
699
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
700
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
701
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
702
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
703
+  *                              bus mode
704
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
705
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
706
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
707
+  * @retval None
708
+  */
709
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
710
+{ 
711
+  /* Check the parameters */
712
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
713
+   
714
+  SDIO->ICR = SDIO_FLAG;
715
+}
716
+
717
+/**
718
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
719
+  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
720
+  *   This parameter can be one of the following values:
721
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
722
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
723
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
724
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
725
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
726
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
727
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
728
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
729
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
730
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
731
+  *                            bus mode interrupt
732
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
733
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
734
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
735
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
736
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
737
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
738
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
739
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
740
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
741
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
742
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
743
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
744
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
745
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
746
+  * @retval The new state of SDIO_IT (SET or RESET).
747
+  */
748
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
749
+{ 
750
+  ITStatus bitstatus = RESET;
751
+  
752
+  /* Check the parameters */
753
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
754
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
755
+  {
756
+    bitstatus = SET;
757
+  }
758
+  else
759
+  {
760
+    bitstatus = RESET;
761
+  }
762
+  return bitstatus;
763
+}
764
+
765
+/**
766
+  * @brief  Clears the SDIO's interrupt pending bits.
767
+  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
768
+  *   This parameter can be one or a combination of the following values:
769
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
770
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
771
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
772
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
773
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
774
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
775
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
776
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
777
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
778
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
779
+  *                            bus mode interrupt
780
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
781
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
782
+  * @retval None
783
+  */
784
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
785
+{ 
786
+  /* Check the parameters */
787
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
788
+   
789
+  SDIO->ICR = SDIO_IT;
790
+}
791
+
792
+/**
793
+  * @}
794
+  */
795
+
796
+/**
797
+  * @}
798
+  */
799
+
800
+/**
801
+  * @}
802
+  */
803
+
804
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 914
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c View File

@@ -0,0 +1,914 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_spi.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the SPI firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_spi.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup SPI 
37
+  * @brief SPI driver modules
38
+  * @{
39
+  */ 
40
+
41
+/** @defgroup SPI_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */ 
48
+
49
+
50
+/** @defgroup SPI_Private_Defines
51
+  * @{
52
+  */
53
+
54
+/* SPI SPE mask */
55
+#define CR1_SPE_Set          ((uint16_t)0x0040)
56
+#define CR1_SPE_Reset        ((uint16_t)0xFFBF)
57
+
58
+/* I2S I2SE mask */
59
+#define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
60
+#define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
61
+
62
+/* SPI CRCNext mask */
63
+#define CR1_CRCNext_Set      ((uint16_t)0x1000)
64
+
65
+/* SPI CRCEN mask */
66
+#define CR1_CRCEN_Set        ((uint16_t)0x2000)
67
+#define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
68
+
69
+/* SPI SSOE mask */
70
+#define CR2_SSOE_Set         ((uint16_t)0x0004)
71
+#define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
72
+
73
+/* SPI registers Masks */
74
+#define CR1_CLEAR_Mask       ((uint16_t)0x3040)
75
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
76
+
77
+/* SPI or I2S mode selection masks */
78
+#define SPI_Mode_Select      ((uint16_t)0xF7FF)
79
+#define I2S_Mode_Select      ((uint16_t)0x0800) 
80
+
81
+/* I2S clock source selection masks */
82
+#define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
83
+#define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
84
+#define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
85
+#define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
86
+
87
+/**
88
+  * @}
89
+  */
90
+
91
+/** @defgroup SPI_Private_Macros
92
+  * @{
93
+  */
94
+
95
+/**
96
+  * @}
97
+  */
98
+
99
+/** @defgroup SPI_Private_Variables
100
+  * @{
101
+  */
102
+
103
+/**
104
+  * @}
105
+  */
106
+
107
+/** @defgroup SPI_Private_FunctionPrototypes
108
+  * @{
109
+  */
110
+
111
+/**
112
+  * @}
113
+  */
114
+
115
+/** @defgroup SPI_Private_Functions
116
+  * @{
117
+  */
118
+
119
+/**
120
+  * @brief  Deinitializes the SPIx peripheral registers to their default
121
+  *         reset values (Affects also the I2Ss).
122
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
123
+  * @retval None
124
+  */
125
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
126
+{
127
+  /* Check the parameters */
128
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
129
+
130
+  if (SPIx == SPI1)
131
+  {
132
+    /* Enable SPI1 reset state */
133
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
134
+    /* Release SPI1 from reset state */
135
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
136
+  }
137
+  else if (SPIx == SPI2)
138
+  {
139
+    /* Enable SPI2 reset state */
140
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
141
+    /* Release SPI2 from reset state */
142
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
143
+  }
144
+  else
145
+  {
146
+    if (SPIx == SPI3)
147
+    {
148
+      /* Enable SPI3 reset state */
149
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
150
+      /* Release SPI3 from reset state */
151
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
152
+    }
153
+  }
154
+}
155
+
156
+/**
157
+  * @brief  Initializes the SPIx peripheral according to the specified 
158
+  *         parameters in the SPI_InitStruct.
159
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
160
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
161
+  *         contains the configuration information for the specified SPI peripheral.
162
+  * @retval None
163
+  */
164
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
165
+{
166
+  uint16_t tmpreg = 0;
167
+  
168
+  /* check the parameters */
169
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
170
+  
171
+  /* Check the SPI parameters */
172
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
173
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
174
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
175
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
176
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
177
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
178
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
179
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
180
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
181
+
182
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
183
+  /* Get the SPIx CR1 value */
184
+  tmpreg = SPIx->CR1;
185
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
186
+  tmpreg &= CR1_CLEAR_Mask;
187
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
188
+     master/salve mode, CPOL and CPHA */
189
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
190
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
191
+  /* Set LSBFirst bit according to SPI_FirstBit value */
192
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
193
+  /* Set CPOL bit according to SPI_CPOL value */
194
+  /* Set CPHA bit according to SPI_CPHA value */
195
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
196
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
197
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
198
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
199
+  /* Write to SPIx CR1 */
200
+  SPIx->CR1 = tmpreg;
201
+  
202
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
203
+  SPIx->I2SCFGR &= SPI_Mode_Select;		
204
+
205
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
206
+  /* Write to SPIx CRCPOLY */
207
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
208
+}
209
+
210
+/**
211
+  * @brief  Initializes the SPIx peripheral according to the specified 
212
+  *         parameters in the I2S_InitStruct.
213
+  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
214
+  *         (configured in I2S mode).
215
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
216
+  *         contains the configuration information for the specified SPI peripheral
217
+  *         configured in I2S mode.
218
+  * @note
219
+  *  The function calculates the optimal prescaler needed to obtain the most 
220
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
221
+  *  and the product configuration). But in case the prescaler value is greater 
222
+  *  than 511, the default value (0x02) will be configured instead.  *   
223
+  * @retval None
224
+  */
225
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
226
+{
227
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
228
+  uint32_t tmp = 0;
229
+  RCC_ClocksTypeDef RCC_Clocks;
230
+  uint32_t sourceclock = 0;
231
+  
232
+  /* Check the I2S parameters */
233
+  assert_param(IS_SPI_23_PERIPH(SPIx));
234
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
235
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
236
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
237
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
238
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
239
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
240
+
241
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
242
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
243
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
244
+  SPIx->I2SPR = 0x0002;
245
+  
246
+  /* Get the I2SCFGR register value */
247
+  tmpreg = SPIx->I2SCFGR;
248
+  
249
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
250
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
251
+  {
252
+    i2sodd = (uint16_t)0;
253
+    i2sdiv = (uint16_t)2;   
254
+  }
255
+  /* If the requested audio frequency is not the default, compute the prescaler */
256
+  else
257
+  {
258
+    /* Check the frame length (For the Prescaler computing) */
259
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
260
+    {
261
+      /* Packet length is 16 bits */
262
+      packetlength = 1;
263
+    }
264
+    else
265
+    {
266
+      /* Packet length is 32 bits */
267
+      packetlength = 2;
268
+    }
269
+
270
+    /* Get the I2S clock source mask depending on the peripheral number */
271
+    if(((uint32_t)SPIx) == SPI2_BASE)
272
+    {
273
+      /* The mask is relative to I2S2 */
274
+      tmp = I2S2_CLOCK_SRC;
275
+    }
276
+    else 
277
+    {
278
+      /* The mask is relative to I2S3 */      
279
+      tmp = I2S3_CLOCK_SRC;
280
+    }
281
+
282
+    /* Check the I2S clock source configuration depending on the Device:
283
+       Only Connectivity line devices have the PLL3 VCO clock */
284
+#ifdef STM32F10X_CL
285
+    if((RCC->CFGR2 & tmp) != 0)
286
+    {
287
+      /* Get the configuration bits of RCC PLL3 multiplier */
288
+      tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
289
+
290
+      /* Get the value of the PLL3 multiplier */      
291
+      if((tmp > 5) && (tmp < 15))
292
+      {
293
+        /* Multiplier is between 8 and 14 (value 15 is forbidden) */
294
+        tmp += 2;
295
+      }
296
+      else
297
+      {
298
+        if (tmp == 15)
299
+        {
300
+          /* Multiplier is 20 */
301
+          tmp = 20;
302
+        }
303
+      }      
304
+      /* Get the PREDIV2 value */
305
+      sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
306
+      
307
+      /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
308
+      sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); 
309
+    }
310
+    else
311
+    {
312
+      /* I2S Clock source is System clock: Get System Clock frequency */
313
+      RCC_GetClocksFreq(&RCC_Clocks);      
314
+      
315
+      /* Get the source clock value: based on System Clock value */
316
+      sourceclock = RCC_Clocks.SYSCLK_Frequency;
317
+    }        
318
+#else /* STM32F10X_HD */
319
+    /* I2S Clock source is System clock: Get System Clock frequency */
320
+    RCC_GetClocksFreq(&RCC_Clocks);      
321
+      
322
+    /* Get the source clock value: based on System Clock value */
323
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
324
+#endif /* STM32F10X_CL */    
325
+
326
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
327
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
328
+    {
329
+      /* MCLK output is enabled */
330
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
331
+    }
332
+    else
333
+    {
334
+      /* MCLK output is disabled */
335
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
336
+    }
337
+    
338
+    /* Remove the floating point */
339
+    tmp = tmp / 10;  
340
+      
341
+    /* Check the parity of the divider */
342
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
343
+   
344
+    /* Compute the i2sdiv prescaler */
345
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
346
+   
347
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
348
+    i2sodd = (uint16_t) (i2sodd << 8);
349
+  }
350
+  
351
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
352
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
353
+  {
354
+    /* Set the default values */
355
+    i2sdiv = 2;
356
+    i2sodd = 0;
357
+  }
358
+
359
+  /* Write to SPIx I2SPR register the computed value */
360
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
361
+ 
362
+  /* Configure the I2S with the SPI_InitStruct values */
363
+  tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
364
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
365
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
366
+ 
367
+  /* Write to SPIx I2SCFGR */  
368
+  SPIx->I2SCFGR = tmpreg;   
369
+}
370
+
371
+/**
372
+  * @brief  Fills each SPI_InitStruct member with its default value.
373
+  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
374
+  * @retval None
375
+  */
376
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
377
+{
378
+/*--------------- Reset SPI init structure parameters values -----------------*/
379
+  /* Initialize the SPI_Direction member */
380
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
381
+  /* initialize the SPI_Mode member */
382
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
383
+  /* initialize the SPI_DataSize member */
384
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
385
+  /* Initialize the SPI_CPOL member */
386
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
387
+  /* Initialize the SPI_CPHA member */
388
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
389
+  /* Initialize the SPI_NSS member */
390
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
391
+  /* Initialize the SPI_BaudRatePrescaler member */
392
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
393
+  /* Initialize the SPI_FirstBit member */
394
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
395
+  /* Initialize the SPI_CRCPolynomial member */
396
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
397
+}
398
+
399
+/**
400
+  * @brief  Fills each I2S_InitStruct member with its default value.
401
+  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
402
+  * @retval None
403
+  */
404
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
405
+{
406
+/*--------------- Reset I2S init structure parameters values -----------------*/
407
+  /* Initialize the I2S_Mode member */
408
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
409
+  
410
+  /* Initialize the I2S_Standard member */
411
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
412
+  
413
+  /* Initialize the I2S_DataFormat member */
414
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
415
+  
416
+  /* Initialize the I2S_MCLKOutput member */
417
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
418
+  
419
+  /* Initialize the I2S_AudioFreq member */
420
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
421
+  
422
+  /* Initialize the I2S_CPOL member */
423
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
424
+}
425
+
426
+/**
427
+  * @brief  Enables or disables the specified SPI peripheral.
428
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
429
+  * @param  NewState: new state of the SPIx peripheral. 
430
+  *   This parameter can be: ENABLE or DISABLE.
431
+  * @retval None
432
+  */
433
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
434
+{
435
+  /* Check the parameters */
436
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
437
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
438
+  if (NewState != DISABLE)
439
+  {
440
+    /* Enable the selected SPI peripheral */
441
+    SPIx->CR1 |= CR1_SPE_Set;
442
+  }
443
+  else
444
+  {
445
+    /* Disable the selected SPI peripheral */
446
+    SPIx->CR1 &= CR1_SPE_Reset;
447
+  }
448
+}
449
+
450
+/**
451
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
452
+  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
453
+  * @param  NewState: new state of the SPIx peripheral. 
454
+  *   This parameter can be: ENABLE or DISABLE.
455
+  * @retval None
456
+  */
457
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
458
+{
459
+  /* Check the parameters */
460
+  assert_param(IS_SPI_23_PERIPH(SPIx));
461
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
462
+  if (NewState != DISABLE)
463
+  {
464
+    /* Enable the selected SPI peripheral (in I2S mode) */
465
+    SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
466
+  }
467
+  else
468
+  {
469
+    /* Disable the selected SPI peripheral (in I2S mode) */
470
+    SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
471
+  }
472
+}
473
+
474
+/**
475
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
476
+  * @param  SPIx: where x can be
477
+  *   - 1, 2 or 3 in SPI mode 
478
+  *   - 2 or 3 in I2S mode
479
+  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. 
480
+  *   This parameter can be one of the following values:
481
+  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
482
+  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
483
+  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
484
+  * @param  NewState: new state of the specified SPI/I2S interrupt.
485
+  *   This parameter can be: ENABLE or DISABLE.
486
+  * @retval None
487
+  */
488
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
489
+{
490
+  uint16_t itpos = 0, itmask = 0 ;
491
+  /* Check the parameters */
492
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
493
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
494
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
495
+
496
+  /* Get the SPI/I2S IT index */
497
+  itpos = SPI_I2S_IT >> 4;
498
+
499
+  /* Set the IT mask */
500
+  itmask = (uint16_t)1 << (uint16_t)itpos;
501
+
502
+  if (NewState != DISABLE)
503
+  {
504
+    /* Enable the selected SPI/I2S interrupt */
505
+    SPIx->CR2 |= itmask;
506
+  }
507
+  else
508
+  {
509
+    /* Disable the selected SPI/I2S interrupt */
510
+    SPIx->CR2 &= (uint16_t)~itmask;
511
+  }
512
+}
513
+
514
+/**
515
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
516
+  * @param  SPIx: where x can be
517
+  *   - 1, 2 or 3 in SPI mode 
518
+  *   - 2 or 3 in I2S mode
519
+  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. 
520
+  *   This parameter can be any combination of the following values:
521
+  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
522
+  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
523
+  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
524
+  *   This parameter can be: ENABLE or DISABLE.
525
+  * @retval None
526
+  */
527
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
528
+{
529
+  /* Check the parameters */
530
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
531
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
532
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
533
+  if (NewState != DISABLE)
534
+  {
535
+    /* Enable the selected SPI/I2S DMA requests */
536
+    SPIx->CR2 |= SPI_I2S_DMAReq;
537
+  }
538
+  else
539
+  {
540
+    /* Disable the selected SPI/I2S DMA requests */
541
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
542
+  }
543
+}
544
+
545
+/**
546
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
547
+  * @param  SPIx: where x can be
548
+  *   - 1, 2 or 3 in SPI mode 
549
+  *   - 2 or 3 in I2S mode
550
+  * @param  Data : Data to be transmitted.
551
+  * @retval None
552
+  */
553
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
554
+{
555
+  /* Check the parameters */
556
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
557
+  
558
+  /* Write in the DR register the data to be sent */
559
+  SPIx->DR = Data;
560
+}
561
+
562
+/**
563
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
564
+  * @param  SPIx: where x can be
565
+  *   - 1, 2 or 3 in SPI mode 
566
+  *   - 2 or 3 in I2S mode
567
+  * @retval The value of the received data.
568
+  */
569
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
570
+{
571
+  /* Check the parameters */
572
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
573
+  
574
+  /* Return the data in the DR register */
575
+  return SPIx->DR;
576
+}
577
+
578
+/**
579
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
580
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
581
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
582
+  *   This parameter can be one of the following values:
583
+  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
584
+  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
585
+  * @retval None
586
+  */
587
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
588
+{
589
+  /* Check the parameters */
590
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
591
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
592
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
593
+  {
594
+    /* Set NSS pin internally by software */
595
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
596
+  }
597
+  else
598
+  {
599
+    /* Reset NSS pin internally by software */
600
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
601
+  }
602
+}
603
+
604
+/**
605
+  * @brief  Enables or disables the SS output for the selected SPI.
606
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
607
+  * @param  NewState: new state of the SPIx SS output. 
608
+  *   This parameter can be: ENABLE or DISABLE.
609
+  * @retval None
610
+  */
611
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
612
+{
613
+  /* Check the parameters */
614
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
615
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
616
+  if (NewState != DISABLE)
617
+  {
618
+    /* Enable the selected SPI SS output */
619
+    SPIx->CR2 |= CR2_SSOE_Set;
620
+  }
621
+  else
622
+  {
623
+    /* Disable the selected SPI SS output */
624
+    SPIx->CR2 &= CR2_SSOE_Reset;
625
+  }
626
+}
627
+
628
+/**
629
+  * @brief  Configures the data size for the selected SPI.
630
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
631
+  * @param  SPI_DataSize: specifies the SPI data size.
632
+  *   This parameter can be one of the following values:
633
+  *     @arg SPI_DataSize_16b: Set data frame format to 16bit
634
+  *     @arg SPI_DataSize_8b: Set data frame format to 8bit
635
+  * @retval None
636
+  */
637
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
638
+{
639
+  /* Check the parameters */
640
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
641
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
642
+  /* Clear DFF bit */
643
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
644
+  /* Set new DFF bit value */
645
+  SPIx->CR1 |= SPI_DataSize;
646
+}
647
+
648
+/**
649
+  * @brief  Transmit the SPIx CRC value.
650
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
651
+  * @retval None
652
+  */
653
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
654
+{
655
+  /* Check the parameters */
656
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
657
+  
658
+  /* Enable the selected SPI CRC transmission */
659
+  SPIx->CR1 |= CR1_CRCNext_Set;
660
+}
661
+
662
+/**
663
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
664
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
665
+  * @param  NewState: new state of the SPIx CRC value calculation.
666
+  *   This parameter can be: ENABLE or DISABLE.
667
+  * @retval None
668
+  */
669
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
670
+{
671
+  /* Check the parameters */
672
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
673
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
674
+  if (NewState != DISABLE)
675
+  {
676
+    /* Enable the selected SPI CRC calculation */
677
+    SPIx->CR1 |= CR1_CRCEN_Set;
678
+  }
679
+  else
680
+  {
681
+    /* Disable the selected SPI CRC calculation */
682
+    SPIx->CR1 &= CR1_CRCEN_Reset;
683
+  }
684
+}
685
+
686
+/**
687
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
688
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
689
+  * @param  SPI_CRC: specifies the CRC register to be read.
690
+  *   This parameter can be one of the following values:
691
+  *     @arg SPI_CRC_Tx: Selects Tx CRC register
692
+  *     @arg SPI_CRC_Rx: Selects Rx CRC register
693
+  * @retval The selected CRC register value..
694
+  */
695
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
696
+{
697
+  uint16_t crcreg = 0;
698
+  /* Check the parameters */
699
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
700
+  assert_param(IS_SPI_CRC(SPI_CRC));
701
+  if (SPI_CRC != SPI_CRC_Rx)
702
+  {
703
+    /* Get the Tx CRC register */
704
+    crcreg = SPIx->TXCRCR;
705
+  }
706
+  else
707
+  {
708
+    /* Get the Rx CRC register */
709
+    crcreg = SPIx->RXCRCR;
710
+  }
711
+  /* Return the selected CRC register */
712
+  return crcreg;
713
+}
714
+
715
+/**
716
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
717
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
718
+  * @retval The CRC Polynomial register value.
719
+  */
720
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
721
+{
722
+  /* Check the parameters */
723
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
724
+  
725
+  /* Return the CRC polynomial register */
726
+  return SPIx->CRCPR;
727
+}
728
+
729
+/**
730
+  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
731
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
732
+  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. 
733
+  *   This parameter can be one of the following values:
734
+  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
735
+  *     @arg SPI_Direction_Rx: Selects Rx receive direction
736
+  * @retval None
737
+  */
738
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
739
+{
740
+  /* Check the parameters */
741
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
742
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
743
+  if (SPI_Direction == SPI_Direction_Tx)
744
+  {
745
+    /* Set the Tx only mode */
746
+    SPIx->CR1 |= SPI_Direction_Tx;
747
+  }
748
+  else
749
+  {
750
+    /* Set the Rx only mode */
751
+    SPIx->CR1 &= SPI_Direction_Rx;
752
+  }
753
+}
754
+
755
+/**
756
+  * @brief  Checks whether the specified SPI/I2S flag is set or not.
757
+  * @param  SPIx: where x can be
758
+  *   - 1, 2 or 3 in SPI mode 
759
+  *   - 2 or 3 in I2S mode
760
+  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
761
+  *   This parameter can be one of the following values:
762
+  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
763
+  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
764
+  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
765
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
766
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.
767
+  *     @arg SPI_FLAG_CRCERR: CRC Error flag.
768
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
769
+  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
770
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
771
+  */
772
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
773
+{
774
+  FlagStatus bitstatus = RESET;
775
+  /* Check the parameters */
776
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
777
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
778
+  /* Check the status of the specified SPI/I2S flag */
779
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
780
+  {
781
+    /* SPI_I2S_FLAG is set */
782
+    bitstatus = SET;
783
+  }
784
+  else
785
+  {
786
+    /* SPI_I2S_FLAG is reset */
787
+    bitstatus = RESET;
788
+  }
789
+  /* Return the SPI_I2S_FLAG status */
790
+  return  bitstatus;
791
+}
792
+
793
+/**
794
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
795
+  * @param  SPIx: where x can be
796
+  *   - 1, 2 or 3 in SPI mode 
797
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
798
+  *   This function clears only CRCERR flag.
799
+  * @note
800
+  *   - OVR (OverRun error) flag is cleared by software sequence: a read 
801
+  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
802
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
803
+  *   - UDR (UnderRun error) flag is cleared by a read operation to 
804
+  *     SPI_SR register (SPI_I2S_GetFlagStatus()).
805
+  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
806
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
807
+  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
808
+  * @retval None
809
+  */
810
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
811
+{
812
+  /* Check the parameters */
813
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
814
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
815
+    
816
+    /* Clear the selected SPI CRC Error (CRCERR) flag */
817
+    SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
818
+}
819
+
820
+/**
821
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
822
+  * @param  SPIx: where x can be
823
+  *   - 1, 2 or 3 in SPI mode 
824
+  *   - 2 or 3 in I2S mode
825
+  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
826
+  *   This parameter can be one of the following values:
827
+  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
828
+  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
829
+  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
830
+  *     @arg SPI_IT_MODF: Mode Fault interrupt.
831
+  *     @arg SPI_IT_CRCERR: CRC Error interrupt.
832
+  *     @arg I2S_IT_UDR: Underrun Error interrupt.
833
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
834
+  */
835
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
836
+{
837
+  ITStatus bitstatus = RESET;
838
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
839
+
840
+  /* Check the parameters */
841
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
842
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
843
+
844
+  /* Get the SPI/I2S IT index */
845
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
846
+
847
+  /* Get the SPI/I2S IT mask */
848
+  itmask = SPI_I2S_IT >> 4;
849
+
850
+  /* Set the IT mask */
851
+  itmask = 0x01 << itmask;
852
+
853
+  /* Get the SPI_I2S_IT enable bit status */
854
+  enablestatus = (SPIx->CR2 & itmask) ;
855
+
856
+  /* Check the status of the specified SPI/I2S interrupt */
857
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
858
+  {
859
+    /* SPI_I2S_IT is set */
860
+    bitstatus = SET;
861
+  }
862
+  else
863
+  {
864
+    /* SPI_I2S_IT is reset */
865
+    bitstatus = RESET;
866
+  }
867
+  /* Return the SPI_I2S_IT status */
868
+  return bitstatus;
869
+}
870
+
871
+/**
872
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
873
+  * @param  SPIx: where x can be
874
+  *   - 1, 2 or 3 in SPI mode 
875
+  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
876
+  *   This function clears only CRCERR interrupt pending bit.   
877
+  * @note
878
+  *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
879
+  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
880
+  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
881
+  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
882
+  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
883
+  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
884
+  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
885
+  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
886
+  *     the SPI).
887
+  * @retval None
888
+  */
889
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
890
+{
891
+  uint16_t itpos = 0;
892
+  /* Check the parameters */
893
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
894
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
895
+
896
+  /* Get the SPI IT index */
897
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
898
+
899
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
900
+  SPIx->SR = (uint16_t)~itpos;
901
+}
902
+/**
903
+  * @}
904
+  */ 
905
+
906
+/**
907
+  * @}
908
+  */ 
909
+
910
+/**
911
+  * @}
912
+  */ 
913
+
914
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 2896
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
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+ 1065
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
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+ 230
- 0
software/robot/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c View File

@@ -0,0 +1,230 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f10x_wwdg.c
4
+  * @author  MCD Application Team
5
+  * @version V3.6.1
6
+  * @date    05-March-2012
7
+  * @brief   This file provides all the WWDG firmware functions.
8
+  ******************************************************************************
9
+  * @attention
10
+  *
11
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
12
+  *
13
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14
+  * You may not use this file except in compliance with the License.
15
+  * You may obtain a copy of the License at:
16
+  *
17
+  *        http://www.st.com/software_license_agreement_liberty_v2
18
+  *
19
+  * Unless required by applicable law or agreed to in writing, software 
20
+  * distributed under the License is distributed on an "AS IS" BASIS, 
21
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+  * See the License for the specific language governing permissions and
23
+  * limitations under the License.
24
+  *
25
+  ******************************************************************************
26
+  */
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f10x_wwdg.h"
30
+#include "stm32f10x_rcc.h"
31
+
32
+/** @addtogroup STM32F10x_StdPeriph_Driver
33
+  * @{
34
+  */
35
+
36
+/** @defgroup WWDG 
37
+  * @brief WWDG driver modules
38
+  * @{
39
+  */
40
+
41
+/** @defgroup WWDG_Private_TypesDefinitions
42
+  * @{
43
+  */
44
+
45
+/**
46
+  * @}
47
+  */
48
+
49
+/** @defgroup WWDG_Private_Defines
50
+  * @{
51
+  */
52
+
53
+/* ----------- WWDG registers bit address in the alias region ----------- */
54
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
55
+
56
+/* Alias word address of EWI bit */
57
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
58
+#define EWI_BitNumber     0x09
59
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
60
+
61
+/* --------------------- WWDG registers bit mask ------------------------ */
62
+
63
+/* CR register bit mask */
64
+#define CR_WDGA_Set       ((uint32_t)0x00000080)
65
+
66
+/* CFR register bit mask */
67
+#define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
68
+#define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
69
+#define BIT_Mask          ((uint8_t)0x7F)
70
+
71
+/**
72
+  * @}
73
+  */
74
+
75
+/** @defgroup WWDG_Private_Macros
76
+  * @{
77
+  */
78
+
79
+/**
80
+  * @}
81
+  */
82
+
83
+/** @defgroup WWDG_Private_Variables
84
+  * @{
85
+  */
86
+
87
+/**
88
+  * @}
89
+  */
90
+
91
+/** @defgroup WWDG_Private_FunctionPrototypes
92
+  * @{
93
+  */
94
+
95
+/**
96
+  * @}
97
+  */
98
+
99
+/** @defgroup WWDG_Private_Functions
100
+  * @{
101
+  */
102
+
103
+/**
104
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
105
+  * @param  None
106
+  * @retval None
107
+  */
108
+void WWDG_DeInit(void)
109
+{
110
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
111
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
112
+}
113
+
114
+/**
115
+  * @brief  Sets the WWDG Prescaler.
116
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
117
+  *   This parameter can be one of the following values:
118
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
119
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
120
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
121
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
122
+  * @retval None
123
+  */
124
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
125
+{
126
+  uint32_t tmpreg = 0;
127
+  /* Check the parameters */
128
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
129
+  /* Clear WDGTB[1:0] bits */
130
+  tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
131
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
132
+  tmpreg |= WWDG_Prescaler;
133
+  /* Store the new value */
134
+  WWDG->CFR = tmpreg;
135
+}
136
+
137
+/**
138
+  * @brief  Sets the WWDG window value.
139
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
140
+  *   This parameter value must be lower than 0x80.
141
+  * @retval None
142
+  */
143
+void WWDG_SetWindowValue(uint8_t WindowValue)
144
+{
145
+  __IO uint32_t tmpreg = 0;
146
+
147
+  /* Check the parameters */
148
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
149
+  /* Clear W[6:0] bits */
150
+
151
+  tmpreg = WWDG->CFR & CFR_W_Mask;
152
+
153
+  /* Set W[6:0] bits according to WindowValue value */
154
+  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
155
+
156
+  /* Store the new value */
157
+  WWDG->CFR = tmpreg;
158
+}
159
+
160
+/**
161
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
162
+  * @param  None
163
+  * @retval None
164
+  */
165
+void WWDG_EnableIT(void)
166
+{
167
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
168
+}
169
+
170
+/**
171
+  * @brief  Sets the WWDG counter value.
172
+  * @param  Counter: specifies the watchdog counter value.
173
+  *   This parameter must be a number between 0x40 and 0x7F.
174
+  * @retval None
175
+  */
176
+void WWDG_SetCounter(uint8_t Counter)
177
+{
178
+  /* Check the parameters */
179
+  assert_param(IS_WWDG_COUNTER(Counter));
180
+  /* Write to T[6:0] bits to configure the counter value, no need to do
181
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
182
+  WWDG->CR = Counter & BIT_Mask;
183
+}
184
+
185
+/**
186
+  * @brief  Enables WWDG and load the counter value.                  
187
+  * @param  Counter: specifies the watchdog counter value.
188
+  *   This parameter must be a number between 0x40 and 0x7F.
189
+  * @retval None
190
+  */
191
+void WWDG_Enable(uint8_t Counter)
192
+{
193
+  /* Check the parameters */
194
+  assert_param(IS_WWDG_COUNTER(Counter));
195
+  WWDG->CR = CR_WDGA_Set | Counter;
196
+}
197
+
198
+/**
199
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
200
+  * @param  None
201
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
202
+  */
203
+FlagStatus WWDG_GetFlagStatus(void)
204
+{
205
+  return (FlagStatus)(WWDG->SR);
206
+}
207
+
208
+/**
209
+  * @brief  Clears Early Wakeup interrupt flag.
210
+  * @param  None
211
+  * @retval None
212
+  */
213
+void WWDG_ClearFlag(void)
214
+{
215
+  WWDG->SR = (uint32_t)RESET;
216
+}
217
+
218
+/**
219
+  * @}
220
+  */
221
+
222
+/**
223
+  * @}
224
+  */
225
+
226
+/**
227
+  * @}
228
+  */
229
+
230
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 0
- 32
software/robot/MAE.c View File

@@ -1,32 +0,0 @@
1
-#include <stm32f10x.h>
2
-#include "system_dumby.h"
3
-#include "MAE.h"
4
-#include "motor.h"
5
-
6
-
7
-
8
-/**	
9
-	*	@brief 	Cette fonction met à jour la machine à état de dumby.
10
-	*					les états peuvent être : IDLE, RUN, DISABLE, LOW, CHARGE.
11
-	*	@param 	Aucun
12
-	*/
13
-void machineWithStates(void)
14
-{
15
-	switch (Dumber.StateSystem)
16
-	{
17
-		case IDLE : // Le changement d'état se fait uniquement par commande
18
-							break;
19
-		case RUN:		if(Dumber.LowBat == TRUE)
20
-										Dumber.StateSystem=LOW;								
21
-							break;
22
-		case DISABLE: cmdLeftMotor(BRAKE,255);
23
-									cmdRightMotor(BRAKE,255);
24
-									while(1);
25
-									break;
26
-		case LOW		: 	if(Dumber.cpt_watchdog>=3)
27
-											Dumber.StateSystem=DISABLE;
28
-							break;
29
-		case CHARGE : 
30
-							break;
31
-	}
32
-}

+ 0
- 12
software/robot/MAE.h View File

@@ -1,12 +0,0 @@
1
-#ifndef MAE_H
2
-#define MAE_H
3
-
4
-#include "stm32f10x.h"
5
-
6
-void machineWithStates(void);
7
-
8
-void action_IDLE(void);
9
-void action_RUN (void);
10
-void action_LOWBAT(void);
11
-void action_CHARGE(void);
12
-#endif

+ 0
- 11
software/robot/RTE/CMSIS/.svn/all-wcprops View File

@@ -1,11 +0,0 @@
1
-K 25
2
-svn:wc:ra_dav:version-url
3
-V 75
4
-/svn/projets-gei/!svn/ver/118/trunk/Dumber%202015/Logiciel/Dumber/RTE/CMSIS
5
-END
6
-RTX_Conf_CM.c
7
-K 25
8
-svn:wc:ra_dav:version-url
9
-V 89
10
-/svn/projets-gei/!svn/ver/118/trunk/Dumber%202015/Logiciel/Dumber/RTE/CMSIS/RTX_Conf_CM.c
11
-END

+ 0
- 62
software/robot/RTE/CMSIS/.svn/entries View File

@@ -1,62 +0,0 @@
1
-10
2
-
3
-dir
4
-159
5
-https://srv-svn-ens/svn/projets-gei/trunk/Dumber%202015/Logiciel/Dumber/RTE/CMSIS
6
-https://srv-svn-ens/svn/projets-gei
7
-
8
-
9
-
10
-2015-12-18T12:18:50.965451Z
11
-118
12
-dimercur
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-42267aa1-c692-48ff-b16d-51b880ef70ee
28
-
29
-RTX_Conf_CM.c
30
-file
31
-
32
-
33
-
34
-
35
-2016-10-18T11:03:41.383670Z
36
-fbd88d694ef282aedeb1cf7df483e25c
37
-2015-12-18T12:18:50.965451Z
38
-118
39
-dimercur
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
-
54
-
55
-
56
-
57
-
58
-
59
-
60
-
61
-11209
62
-

+ 0
- 313
software/robot/RTE/CMSIS/.svn/text-base/RTX_Conf_CM.c.svn-base View File

@@ -1,313 +0,0 @@
1
-/*----------------------------------------------------------------------------
2
- *      CMSIS-RTOS  -  RTX
3
- *----------------------------------------------------------------------------
4
- *      Name:    RTX_Conf_CM.C
5
- *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
6
- *      Rev.:    V4.70.1
7
- *----------------------------------------------------------------------------
8
- *
9
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
10
- * All rights reserved.
11
- * Redistribution and use in source and binary forms, with or without
12
- * modification, are permitted provided that the following conditions are met:
13
- *  - Redistributions of source code must retain the above copyright
14
- *    notice, this list of conditions and the following disclaimer.
15
- *  - Redistributions in binary form must reproduce the above copyright
16
- *    notice, this list of conditions and the following disclaimer in the
17
- *    documentation and/or other materials provided with the distribution.
18
- *  - Neither the name of ARM  nor the names of its contributors may be used 
19
- *    to endorse or promote products derived from this software without 
20
- *    specific prior written permission.
21
- *
22
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
23
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
24
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
28
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
29
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
30
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
31
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32
- * POSSIBILITY OF SUCH DAMAGE.
33
- *---------------------------------------------------------------------------*/
34
- 
35
-#include "cmsis_os.h"
36
- 
37
-
38
-/*----------------------------------------------------------------------------
39
- *      RTX User configuration part BEGIN
40
- *---------------------------------------------------------------------------*/
41
- 
42
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
43
-//
44
-// <h>Thread Configuration
45
-// =======================
46
-//
47
-//   <o>Number of concurrent running user threads <1-250>
48
-//   <i> Defines max. number of user threads that will run at the same time.
49
-//   <i> Default: 6
50
-#ifndef OS_TASKCNT
51
- #define OS_TASKCNT     6
52
-#endif
53
- 
54
-//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
55
-//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
56
-//   <i> Default: 200
57
-#ifndef OS_STKSIZE
58
- #define OS_STKSIZE     50      // this stack size value is in words
59
-#endif
60
- 
61
-//   <o>Main Thread stack size [bytes] <64-32768:8><#/4>
62
-//   <i> Defines stack size for main thread.
63
-//   <i> Default: 200
64
-#ifndef OS_MAINSTKSIZE
65
- #define OS_MAINSTKSIZE 50      // this stack size value is in words
66
-#endif
67
- 
68
-//   <o>Number of threads with user-provided stack size <0-250>
69
-//   <i> Defines the number of threads with user-provided stack size.
70
-//   <i> Default: 0
71
-#ifndef OS_PRIVCNT
72
- #define OS_PRIVCNT     0
73
-#endif
74
- 
75
-//   <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
76
-//   <i> Defines the combined stack size for threads with user-provided stack size.
77
-//   <i> Default: 0
78
-#ifndef OS_PRIVSTKSIZE
79
- #define OS_PRIVSTKSIZE 0       // this stack size value is in words
80
-#endif
81
- 
82
-//   <q>Stack overflow checking
83
-//   <i> Enable stack overflow checks at thread switch.
84
-//   <i> Enabling this option increases slightly the execution time of a thread switch.
85
-#ifndef OS_STKCHECK
86
- #define OS_STKCHECK    1
87
-#endif
88
- 
89
-//   <q>Stack usage watermark
90
-//   <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
91
-//   <i> Enabling this option increases significantly the execution time of osThreadCreate.
92
-#ifndef OS_STKINIT
93
-#define OS_STKINIT      1
94
-#endif
95
- 
96
-//   <o>Processor mode for thread execution 
97
-//     <0=> Unprivileged mode 
98
-//     <1=> Privileged mode
99
-//   <i> Default: Privileged mode
100
-#ifndef OS_RUNPRIV
101
- #define OS_RUNPRIV     1
102
-#endif
103
- 
104
-// </h>
105
- 
106
-// <h>RTX Kernel Timer Tick Configuration
107
-// ======================================
108
-//   <q> Use Cortex-M SysTick timer as RTX Kernel Timer
109
-//   <i> Cortex-M processors provide in most cases a SysTick timer that can be used as 
110
-//   <i> as time-base for RTX.
111
-#ifndef OS_SYSTICK
112
- #define OS_SYSTICK     1
113
-#endif
114
-//
115
-//   <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
116
-//   <i> Defines the input frequency of the RTOS Kernel Timer.  
117
-//   <i> When the Cortex-M SysTick timer is used, the input clock 
118
-//   <i> is on most systems identical with the core clock.
119
-#ifndef OS_CLOCK
120
- #define OS_CLOCK       12000000
121
-#endif
122
- 
123
-//   <o>RTX Timer tick interval value [us] <1-1000000>
124
-//   <i> The RTX Timer tick interval value is used to calculate timeout values.
125
-//   <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
126
-//   <i> Default: 1000  (1ms)
127
-#ifndef OS_TICK
128
- #define OS_TICK        1000
129
-#endif
130
- 
131
-// </h>
132
- 
133
-// <h>System Configuration
134
-// =======================
135
-//
136
-// <e>Round-Robin Thread switching
137
-// ===============================
138
-//
139
-// <i> Enables Round-Robin Thread switching.
140
-#ifndef OS_ROBIN
141
- #define OS_ROBIN       1
142
-#endif
143
- 
144
-//   <o>Round-Robin Timeout [ticks] <1-1000>
145
-//   <i> Defines how long a thread will execute before a thread switch.
146
-//   <i> Default: 5
147
-#ifndef OS_ROBINTOUT
148
- #define OS_ROBINTOUT   5
149
-#endif
150
- 
151
-// </e>
152
- 
153
-// <e>User Timers
154
-// ==============
155
-//   <i> Enables user Timers
156
-#ifndef OS_TIMERS
157
- #define OS_TIMERS      1
158
-#endif
159
- 
160
-//   <o>Timer Thread Priority
161
-//                        <1=> Low
162
-//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
163
-//                        <5=> High
164
-//                        <6=> Realtime (highest)
165
-//   <i> Defines priority for Timer Thread
166
-//   <i> Default: High
167
-#ifndef OS_TIMERPRIO
168
- #define OS_TIMERPRIO   5
169
-#endif
170
- 
171
-//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
172
-//   <i> Defines stack size for Timer thread.
173
-//   <i> Default: 200
174
-#ifndef OS_TIMERSTKSZ
175
- #define OS_TIMERSTKSZ  50     // this stack size value is in words
176
-#endif
177
- 
178
-//   <o>Timer Callback Queue size <1-32>
179
-//   <i> Number of concurrent active timer callback functions.
180
-//   <i> Default: 4
181
-#ifndef OS_TIMERCBQS
182
- #define OS_TIMERCBQS   4
183
-#endif
184
- 
185
-// </e>
186
- 
187
-//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
188
-//                         <12=> 12 entries  <16=> 16 entries
189
-//                         <24=> 24 entries  <32=> 32 entries
190
-//                         <48=> 48 entries  <64=> 64 entries
191
-//                         <96=> 96 entries
192
-//   <i> ISR functions store requests to this buffer,
193
-//   <i> when they are called from the interrupt handler.
194
-//   <i> Default: 16 entries
195
-#ifndef OS_FIFOSZ
196
- #define OS_FIFOSZ      16
197
-#endif
198
- 
199
-// </h>
200
- 
201
-//------------- <<< end of configuration section >>> -----------------------
202
- 
203
-// Standard library system mutexes
204
-// ===============================
205
-//  Define max. number system mutexes that are used to protect 
206
-//  the arm standard runtime library. For microlib they are not used.
207
-#ifndef OS_MUTEXCNT
208
- #define OS_MUTEXCNT    8
209
-#endif
210
- 
211
-/*----------------------------------------------------------------------------
212
- *      RTX User configuration part END
213
- *---------------------------------------------------------------------------*/
214
- 
215
-#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
216
- 
217
-
218
-/*----------------------------------------------------------------------------
219
- *      Global Functions
220
- *---------------------------------------------------------------------------*/
221
- 
222
-/*--------------------------- os_idle_demon ---------------------------------*/
223
-
224
-/// \brief The idle demon is running when no other thread is ready to run
225
-void os_idle_demon (void) {
226
- 
227
-  for (;;) {
228
-    /* HERE: include optional user code to be executed when no thread runs.*/
229
-  }
230
-}
231
- 
232
-#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
233
- 
234
-/*--------------------------- os_tick_init ----------------------------------*/
235
- 
236
-/// \brief Initializes an alternative hardware timer as RTX kernel timer
237
-/// \return                             IRQ number of the alternative hardware timer
238
-int os_tick_init (void) {
239
-  return (-1);  /* Return IRQ number of timer (0..239) */
240
-}
241
- 
242
-/*--------------------------- os_tick_val -----------------------------------*/
243
- 
244
-/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
245
-/// \return                             Current value of the alternative hardware timer
246
-uint32_t os_tick_val (void) {
247
-  return (0);
248
-}
249
- 
250
-/*--------------------------- os_tick_ovf -----------------------------------*/
251
- 
252
-/// \brief Get alternative hardware timer's  overflow flag
253
-/// \return                             Overflow flag\n
254
-///                                     - 1 : overflow
255
-///                                     - 0 : no overflow
256
-uint32_t os_tick_ovf (void) {
257
-  return (0);
258
-}
259
- 
260
-/*--------------------------- os_tick_irqack --------------------------------*/
261
- 
262
-/// \brief Acknowledge alternative hardware timer interrupt
263
-void os_tick_irqack (void) {
264
-  /* ... */
265
-}
266
- 
267
-#endif   // (OS_SYSTICK == 0)
268
- 
269
-/*--------------------------- os_error --------------------------------------*/
270
- 
271
-/* OS Error Codes */
272
-#define OS_ERROR_STACK_OVF      1
273
-#define OS_ERROR_FIFO_OVF       2
274
-#define OS_ERROR_MBX_OVF        3
275
-#define OS_ERROR_TIMER_OVF      4
276
- 
277
-extern osThreadId svcThreadGetId (void);
278
- 
279
-/// \brief Called when a runtime error is detected
280
-/// \param[in]   error_code   actual error code that has been detected
281
-void os_error (uint32_t error_code) {
282
- 
283
-  /* HERE: include optional code to be executed on runtime error. */
284
-  switch (error_code) {
285
-    case OS_ERROR_STACK_OVF:
286
-      /* Stack overflow detected for the currently running task. */
287
-      /* Thread can be identified by calling svcThreadGetId().   */
288
-      break;
289
-    case OS_ERROR_FIFO_OVF:
290
-      /* ISR FIFO Queue buffer overflow detected. */
291
-      break;
292
-    case OS_ERROR_MBX_OVF:
293
-      /* Mailbox overflow detected. */
294
-      break;
295
-    case OS_ERROR_TIMER_OVF:
296
-      /* User Timer Callback Queue overflow detected. */
297
-      break;
298
-    default:
299
-      break;
300
-  }
301
-  for (;;);
302
-}
303
- 
304
-
305
-/*----------------------------------------------------------------------------
306
- *      RTX Configuration Functions
307
- *---------------------------------------------------------------------------*/
308
- 
309
-#include "RTX_CM_lib.h"
310
- 
311
-/*----------------------------------------------------------------------------
312
- * end of file
313
- *---------------------------------------------------------------------------*/

+ 0
- 313
software/robot/RTE/CMSIS/RTX_Conf_CM.c View File

@@ -1,313 +0,0 @@
1
-/*----------------------------------------------------------------------------
2
- *      CMSIS-RTOS  -  RTX
3
- *----------------------------------------------------------------------------
4
- *      Name:    RTX_Conf_CM.C
5
- *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
6
- *      Rev.:    V4.70.1
7
- *----------------------------------------------------------------------------
8
- *
9
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
10
- * All rights reserved.
11
- * Redistribution and use in source and binary forms, with or without
12
- * modification, are permitted provided that the following conditions are met:
13
- *  - Redistributions of source code must retain the above copyright
14
- *    notice, this list of conditions and the following disclaimer.
15
- *  - Redistributions in binary form must reproduce the above copyright
16
- *    notice, this list of conditions and the following disclaimer in the
17
- *    documentation and/or other materials provided with the distribution.
18
- *  - Neither the name of ARM  nor the names of its contributors may be used 
19
- *    to endorse or promote products derived from this software without 
20
- *    specific prior written permission.
21
- *
22
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
23
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
24
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
28
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
29
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
30
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
31
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32
- * POSSIBILITY OF SUCH DAMAGE.
33
- *---------------------------------------------------------------------------*/
34
- 
35
-#include "cmsis_os.h"
36
- 
37
-
38
-/*----------------------------------------------------------------------------
39
- *      RTX User configuration part BEGIN
40
- *---------------------------------------------------------------------------*/
41
- 
42
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
43
-//
44
-// <h>Thread Configuration
45
-// =======================
46
-//
47
-//   <o>Number of concurrent running user threads <1-250>
48
-//   <i> Defines max. number of user threads that will run at the same time.
49
-//   <i> Default: 6
50
-#ifndef OS_TASKCNT
51
- #define OS_TASKCNT     6
52
-#endif
53
- 
54
-//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
55
-//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
56
-//   <i> Default: 200
57
-#ifndef OS_STKSIZE
58
- #define OS_STKSIZE     50      // this stack size value is in words
59
-#endif
60
- 
61
-//   <o>Main Thread stack size [bytes] <64-32768:8><#/4>
62
-//   <i> Defines stack size for main thread.
63
-//   <i> Default: 200
64
-#ifndef OS_MAINSTKSIZE
65
- #define OS_MAINSTKSIZE 50      // this stack size value is in words
66
-#endif
67
- 
68
-//   <o>Number of threads with user-provided stack size <0-250>
69
-//   <i> Defines the number of threads with user-provided stack size.
70
-//   <i> Default: 0
71
-#ifndef OS_PRIVCNT
72
- #define OS_PRIVCNT     0
73
-#endif
74
- 
75
-//   <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
76
-//   <i> Defines the combined stack size for threads with user-provided stack size.
77
-//   <i> Default: 0
78
-#ifndef OS_PRIVSTKSIZE
79
- #define OS_PRIVSTKSIZE 0       // this stack size value is in words
80
-#endif
81
- 
82
-//   <q>Stack overflow checking
83
-//   <i> Enable stack overflow checks at thread switch.
84
-//   <i> Enabling this option increases slightly the execution time of a thread switch.
85
-#ifndef OS_STKCHECK
86
- #define OS_STKCHECK    1
87
-#endif
88
- 
89
-//   <q>Stack usage watermark
90
-//   <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
91
-//   <i> Enabling this option increases significantly the execution time of osThreadCreate.
92
-#ifndef OS_STKINIT
93
-#define OS_STKINIT      1
94
-#endif
95
- 
96
-//   <o>Processor mode for thread execution 
97
-//     <0=> Unprivileged mode 
98
-//     <1=> Privileged mode
99
-//   <i> Default: Privileged mode
100
-#ifndef OS_RUNPRIV
101
- #define OS_RUNPRIV     1
102
-#endif
103
- 
104
-// </h>
105
- 
106
-// <h>RTX Kernel Timer Tick Configuration
107
-// ======================================
108
-//   <q> Use Cortex-M SysTick timer as RTX Kernel Timer
109
-//   <i> Cortex-M processors provide in most cases a SysTick timer that can be used as 
110
-//   <i> as time-base for RTX.
111
-#ifndef OS_SYSTICK
112
- #define OS_SYSTICK     1
113
-#endif
114
-//
115
-//   <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
116
-//   <i> Defines the input frequency of the RTOS Kernel Timer.  
117
-//   <i> When the Cortex-M SysTick timer is used, the input clock 
118
-//   <i> is on most systems identical with the core clock.
119
-#ifndef OS_CLOCK
120
- #define OS_CLOCK       12000000
121
-#endif
122
- 
123
-//   <o>RTX Timer tick interval value [us] <1-1000000>
124
-//   <i> The RTX Timer tick interval value is used to calculate timeout values.
125
-//   <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
126
-//   <i> Default: 1000  (1ms)
127
-#ifndef OS_TICK
128
- #define OS_TICK        1000
129
-#endif
130
- 
131
-// </h>
132
- 
133
-// <h>System Configuration
134
-// =======================
135
-//
136
-// <e>Round-Robin Thread switching
137
-// ===============================
138
-//
139
-// <i> Enables Round-Robin Thread switching.
140
-#ifndef OS_ROBIN
141
- #define OS_ROBIN       1
142
-#endif
143
- 
144
-//   <o>Round-Robin Timeout [ticks] <1-1000>
145
-//   <i> Defines how long a thread will execute before a thread switch.
146
-//   <i> Default: 5
147
-#ifndef OS_ROBINTOUT
148
- #define OS_ROBINTOUT   5
149
-#endif
150
- 
151
-// </e>
152
- 
153
-// <e>User Timers
154
-// ==============
155
-//   <i> Enables user Timers
156
-#ifndef OS_TIMERS
157
- #define OS_TIMERS      1
158
-#endif
159
- 
160
-//   <o>Timer Thread Priority
161
-//                        <1=> Low
162
-//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
163
-//                        <5=> High
164
-//                        <6=> Realtime (highest)
165
-//   <i> Defines priority for Timer Thread
166
-//   <i> Default: High
167
-#ifndef OS_TIMERPRIO
168
- #define OS_TIMERPRIO   5
169
-#endif
170
- 
171
-//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
172
-//   <i> Defines stack size for Timer thread.
173
-//   <i> Default: 200
174
-#ifndef OS_TIMERSTKSZ
175
- #define OS_TIMERSTKSZ  50     // this stack size value is in words
176
-#endif
177
- 
178
-//   <o>Timer Callback Queue size <1-32>
179
-//   <i> Number of concurrent active timer callback functions.
180
-//   <i> Default: 4
181
-#ifndef OS_TIMERCBQS
182
- #define OS_TIMERCBQS   4
183
-#endif
184
- 
185
-// </e>
186
- 
187
-//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
188
-//                         <12=> 12 entries  <16=> 16 entries
189
-//                         <24=> 24 entries  <32=> 32 entries
190
-//                         <48=> 48 entries  <64=> 64 entries
191
-//                         <96=> 96 entries
192
-//   <i> ISR functions store requests to this buffer,
193
-//   <i> when they are called from the interrupt handler.
194
-//   <i> Default: 16 entries
195
-#ifndef OS_FIFOSZ
196
- #define OS_FIFOSZ      16
197
-#endif
198
- 
199
-// </h>
200
- 
201
-//------------- <<< end of configuration section >>> -----------------------
202
- 
203
-// Standard library system mutexes
204
-// ===============================
205
-//  Define max. number system mutexes that are used to protect 
206
-//  the arm standard runtime library. For microlib they are not used.
207
-#ifndef OS_MUTEXCNT
208
- #define OS_MUTEXCNT    8
209
-#endif
210
- 
211
-/*----------------------------------------------------------------------------
212
- *      RTX User configuration part END
213
- *---------------------------------------------------------------------------*/
214
- 
215
-#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
216
- 
217
-
218
-/*----------------------------------------------------------------------------
219
- *      Global Functions
220
- *---------------------------------------------------------------------------*/
221
- 
222
-/*--------------------------- os_idle_demon ---------------------------------*/
223
-
224
-/// \brief The idle demon is running when no other thread is ready to run
225
-void os_idle_demon (void) {
226
- 
227
-  for (;;) {
228
-    /* HERE: include optional user code to be executed when no thread runs.*/
229
-  }
230
-}
231
- 
232
-#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
233
- 
234
-/*--------------------------- os_tick_init ----------------------------------*/
235
- 
236
-/// \brief Initializes an alternative hardware timer as RTX kernel timer
237
-/// \return                             IRQ number of the alternative hardware timer
238
-int os_tick_init (void) {
239
-  return (-1);  /* Return IRQ number of timer (0..239) */
240
-}
241
- 
242
-/*--------------------------- os_tick_val -----------------------------------*/
243
- 
244
-/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
245
-/// \return                             Current value of the alternative hardware timer
246
-uint32_t os_tick_val (void) {
247
-  return (0);
248
-}
249
- 
250
-/*--------------------------- os_tick_ovf -----------------------------------*/
251
- 
252
-/// \brief Get alternative hardware timer's  overflow flag
253
-/// \return                             Overflow flag\n
254
-///                                     - 1 : overflow
255
-///                                     - 0 : no overflow
256
-uint32_t os_tick_ovf (void) {
257
-  return (0);
258
-}
259
- 
260
-/*--------------------------- os_tick_irqack --------------------------------*/
261
- 
262
-/// \brief Acknowledge alternative hardware timer interrupt
263
-void os_tick_irqack (void) {
264
-  /* ... */
265
-}
266
- 
267
-#endif   // (OS_SYSTICK == 0)
268
- 
269
-/*--------------------------- os_error --------------------------------------*/
270
- 
271
-/* OS Error Codes */
272
-#define OS_ERROR_STACK_OVF      1
273
-#define OS_ERROR_FIFO_OVF       2
274
-#define OS_ERROR_MBX_OVF        3
275
-#define OS_ERROR_TIMER_OVF      4
276
- 
277
-extern osThreadId svcThreadGetId (void);
278
- 
279
-/// \brief Called when a runtime error is detected
280
-/// \param[in]   error_code   actual error code that has been detected
281
-void os_error (uint32_t error_code) {
282
- 
283
-  /* HERE: include optional code to be executed on runtime error. */
284
-  switch (error_code) {
285
-    case OS_ERROR_STACK_OVF:
286
-      /* Stack overflow detected for the currently running task. */
287
-      /* Thread can be identified by calling svcThreadGetId().   */
288
-      break;
289
-    case OS_ERROR_FIFO_OVF:
290
-      /* ISR FIFO Queue buffer overflow detected. */
291
-      break;
292
-    case OS_ERROR_MBX_OVF:
293
-      /* Mailbox overflow detected. */
294
-      break;
295
-    case OS_ERROR_TIMER_OVF:
296
-      /* User Timer Callback Queue overflow detected. */
297
-      break;
298
-    default:
299
-      break;
300
-  }
301
-  for (;;);
302
-}
303
- 
304
-
305
-/*----------------------------------------------------------------------------
306
- *      RTX Configuration Functions
307
- *---------------------------------------------------------------------------*/
308
- 
309
-#include "RTX_CM_lib.h"
310
- 
311
-/*----------------------------------------------------------------------------
312
- * end of file
313
- *---------------------------------------------------------------------------*/

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@@ -1,307 +0,0 @@
1
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
2
-;* File Name          : startup_stm32f10x_md.s
3
-;* Author             : MCD Application Team
4
-;* Version            : V3.5.0
5
-;* Date               : 11-March-2011
6
-;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
7
-;*                      toolchain.  
8
-;*                      This module performs:
9
-;*                      - Set the initial SP
10
-;*                      - Set the initial PC == Reset_Handler
11
-;*                      - Set the vector table entries with the exceptions ISR address
12
-;*                      - Configure the clock system
13
-;*                      - Branches to __main in the C library (which eventually
14
-;*                        calls main()).
15
-;*                      After Reset the CortexM3 processor is in Thread mode,
16
-;*                      priority is Privileged, and the Stack is set to Main.
17
-;* <<< Use Configuration Wizard in Context Menu >>>   
18
-;*******************************************************************************
19
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
20
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
21
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
22
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
23
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
24
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25
-;*******************************************************************************
26
-
27
-; Amount of memory (in bytes) allocated for Stack
28
-; Tailor this value to your application needs
29
-; <h> Stack Configuration
30
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31
-; </h>
32
-
33
-Stack_Size      EQU     0x00000400
34
-
35
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
36
-Stack_Mem       SPACE   Stack_Size
37
-__initial_sp
38
-
39
-
40
-; <h> Heap Configuration
41
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42
-; </h>
43
-
44
-Heap_Size       EQU     0x00000200
45
-
46
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
47
-__heap_base
48
-Heap_Mem        SPACE   Heap_Size
49
-__heap_limit
50
-
51
-                PRESERVE8
52
-                THUMB
53
-
54
-
55
-; Vector Table Mapped to Address 0 at Reset
56
-                AREA    RESET, DATA, READONLY
57
-                EXPORT  __Vectors
58
-                EXPORT  __Vectors_End
59
-                EXPORT  __Vectors_Size
60
-
61
-__Vectors       DCD     __initial_sp               ; Top of Stack
62
-                DCD     Reset_Handler              ; Reset Handler
63
-                DCD     NMI_Handler                ; NMI Handler
64
-                DCD     HardFault_Handler          ; Hard Fault Handler
65
-                DCD     MemManage_Handler          ; MPU Fault Handler
66
-                DCD     BusFault_Handler           ; Bus Fault Handler
67
-                DCD     UsageFault_Handler         ; Usage Fault Handler
68
-                DCD     0                          ; Reserved
69
-                DCD     0                          ; Reserved
70
-                DCD     0                          ; Reserved
71
-                DCD     0                          ; Reserved
72
-                DCD     SVC_Handler                ; SVCall Handler
73
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
74
-                DCD     0                          ; Reserved
75
-                DCD     PendSV_Handler             ; PendSV Handler
76
-                DCD     SysTick_Handler            ; SysTick Handler
77
-
78
-                ; External Interrupts
79
-                DCD     WWDG_IRQHandler            ; Window Watchdog
80
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
81
-                DCD     TAMPER_IRQHandler          ; Tamper
82
-                DCD     RTC_IRQHandler             ; RTC
83
-                DCD     FLASH_IRQHandler           ; Flash
84
-                DCD     RCC_IRQHandler             ; RCC
85
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
86
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
87
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
88
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
89
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
90
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
91
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
92
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
93
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
94
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
95
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
96
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
97
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
98
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
99
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
100
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
101
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
102
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
103
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
104
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
105
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
106
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
107
-                DCD     TIM2_IRQHandler            ; TIM2
108
-                DCD     TIM3_IRQHandler            ; TIM3
109
-                DCD     TIM4_IRQHandler            ; TIM4
110
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
111
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
112
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
113
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
114
-                DCD     SPI1_IRQHandler            ; SPI1
115
-                DCD     SPI2_IRQHandler            ; SPI2
116
-                DCD     USART1_IRQHandler          ; USART1
117
-                DCD     USART2_IRQHandler          ; USART2
118
-                DCD     USART3_IRQHandler          ; USART3
119
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
120
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
121
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
122
-__Vectors_End
123
-
124
-__Vectors_Size  EQU  __Vectors_End - __Vectors
125
-
126
-                AREA    |.text|, CODE, READONLY
127
-
128
-; Reset handler
129
-Reset_Handler    PROC
130
-                 EXPORT  Reset_Handler             [WEAK]
131
-     IMPORT  __main
132
-     IMPORT  SystemInit
133
-                 LDR     R0, =SystemInit
134
-                 BLX     R0
135
-                 LDR     R0, =__main
136
-                 BX      R0
137
-                 ENDP
138
-
139
-; Dummy Exception Handlers (infinite loops which can be modified)
140
-
141
-NMI_Handler     PROC
142
-                EXPORT  NMI_Handler                [WEAK]
143
-                B       .
144
-                ENDP
145
-HardFault_Handler\
146
-                PROC
147
-                EXPORT  HardFault_Handler          [WEAK]
148
-                B       .
149
-                ENDP
150
-MemManage_Handler\
151
-                PROC
152
-                EXPORT  MemManage_Handler          [WEAK]
153
-                B       .
154
-                ENDP
155
-BusFault_Handler\
156
-                PROC
157
-                EXPORT  BusFault_Handler           [WEAK]
158
-                B       .
159
-                ENDP
160
-UsageFault_Handler\
161
-                PROC
162
-                EXPORT  UsageFault_Handler         [WEAK]
163
-                B       .
164
-                ENDP
165
-SVC_Handler     PROC
166
-                EXPORT  SVC_Handler                [WEAK]
167
-                B       .
168
-                ENDP
169
-DebugMon_Handler\
170
-                PROC
171
-                EXPORT  DebugMon_Handler           [WEAK]
172
-                B       .
173
-                ENDP
174
-PendSV_Handler  PROC
175
-                EXPORT  PendSV_Handler             [WEAK]
176
-                B       .
177
-                ENDP
178
-SysTick_Handler PROC
179
-                EXPORT  SysTick_Handler            [WEAK]
180
-                B       .
181
-                ENDP
182
-
183
-Default_Handler PROC
184
-
185
-                EXPORT  WWDG_IRQHandler            [WEAK]
186
-                EXPORT  PVD_IRQHandler             [WEAK]
187
-                EXPORT  TAMPER_IRQHandler          [WEAK]
188
-                EXPORT  RTC_IRQHandler             [WEAK]
189
-                EXPORT  FLASH_IRQHandler           [WEAK]
190
-                EXPORT  RCC_IRQHandler             [WEAK]
191
-                EXPORT  EXTI0_IRQHandler           [WEAK]
192
-                EXPORT  EXTI1_IRQHandler           [WEAK]
193
-                EXPORT  EXTI2_IRQHandler           [WEAK]
194
-                EXPORT  EXTI3_IRQHandler           [WEAK]
195
-                EXPORT  EXTI4_IRQHandler           [WEAK]
196
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
197
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
198
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
199
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
200
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
201
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
202
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
203
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
204
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
205
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
206
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
207
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
208
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
209
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
210
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
211
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
212
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
213
-                EXPORT  TIM2_IRQHandler            [WEAK]
214
-                EXPORT  TIM3_IRQHandler            [WEAK]
215
-                EXPORT  TIM4_IRQHandler            [WEAK]
216
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
217
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
218
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
219
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
220
-                EXPORT  SPI1_IRQHandler            [WEAK]
221
-                EXPORT  SPI2_IRQHandler            [WEAK]
222
-                EXPORT  USART1_IRQHandler          [WEAK]
223
-                EXPORT  USART2_IRQHandler          [WEAK]
224
-                EXPORT  USART3_IRQHandler          [WEAK]
225
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
226
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
227
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
228
-
229
-WWDG_IRQHandler
230
-PVD_IRQHandler
231
-TAMPER_IRQHandler
232
-RTC_IRQHandler
233
-FLASH_IRQHandler
234
-RCC_IRQHandler
235
-EXTI0_IRQHandler
236
-EXTI1_IRQHandler
237
-EXTI2_IRQHandler
238
-EXTI3_IRQHandler
239
-EXTI4_IRQHandler
240
-DMA1_Channel1_IRQHandler
241
-DMA1_Channel2_IRQHandler
242
-DMA1_Channel3_IRQHandler
243
-DMA1_Channel4_IRQHandler
244
-DMA1_Channel5_IRQHandler
245
-DMA1_Channel6_IRQHandler
246
-DMA1_Channel7_IRQHandler
247
-ADC1_2_IRQHandler
248
-USB_HP_CAN1_TX_IRQHandler
249
-USB_LP_CAN1_RX0_IRQHandler
250
-CAN1_RX1_IRQHandler
251
-CAN1_SCE_IRQHandler
252
-EXTI9_5_IRQHandler
253
-TIM1_BRK_IRQHandler
254
-TIM1_UP_IRQHandler
255
-TIM1_TRG_COM_IRQHandler
256
-TIM1_CC_IRQHandler
257
-TIM2_IRQHandler
258
-TIM3_IRQHandler
259
-TIM4_IRQHandler
260
-I2C1_EV_IRQHandler
261
-I2C1_ER_IRQHandler
262
-I2C2_EV_IRQHandler
263
-I2C2_ER_IRQHandler
264
-SPI1_IRQHandler
265
-SPI2_IRQHandler
266
-USART1_IRQHandler
267
-USART2_IRQHandler
268
-USART3_IRQHandler
269
-EXTI15_10_IRQHandler
270
-RTCAlarm_IRQHandler
271
-USBWakeUp_IRQHandler
272
-
273
-                B       .
274
-
275
-                ENDP
276
-
277
-                ALIGN
278
-
279
-;*******************************************************************************
280
-; User Stack and Heap initialization
281
-;*******************************************************************************
282
-                 IF      :DEF:__MICROLIB           
283
-                
284
-                 EXPORT  __initial_sp
285
-                 EXPORT  __heap_base
286
-                 EXPORT  __heap_limit
287
-                
288
-                 ELSE
289
-                
290
-                 IMPORT  __use_two_region_memory
291
-                 EXPORT  __user_initial_stackheap
292
-                 
293
-__user_initial_stackheap
294
-
295
-                 LDR     R0, =  Heap_Mem
296
-                 LDR     R1, =(Stack_Mem + Stack_Size)
297
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
298
-                 LDR     R3, = Stack_Mem
299
-                 BX      LR
300
-
301
-                 ALIGN
302
-
303
-                 ENDIF
304
-
305
-                 END
306
-
307
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

+ 0
- 124
software/robot/RTE/Device/STM32F103RB/.svn/text-base/stm32f10x_conf.h.svn-base View File

@@ -1,124 +0,0 @@
1
-/**
2
-  ******************************************************************************
3
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 
4
-  * @author  MCD Application Team
5
-  * @version V3.5.0
6
-  * @date    08-April-2011
7
-  * @brief   Library configuration file.
8
-  ******************************************************************************
9
-  * @attention
10
-  *
11
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17
-  *
18
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19
-  ******************************************************************************
20
-  */
21
-
22
-/* Define to prevent recursive inclusion -------------------------------------*/
23
-#ifndef __STM32F10x_CONF_H
24
-#define __STM32F10x_CONF_H
25
-
26
-/* Run Time Environment will set specific #define for each selected module below */
27
-#include "RTE_Components.h"
28
-
29
-#ifdef RTE_DEVICE_STDPERIPH_ADC
30
-#include "stm32f10x_adc.h"
31
-#endif
32
-#ifdef RTE_DEVICE_STDPERIPH_BKP
33
-#include "stm32f10x_bkp.h"
34
-#endif
35
-#ifdef RTE_DEVICE_STDPERIPH_CAN
36
-#include "stm32f10x_can.h"
37
-#endif
38
-#ifdef RTE_DEVICE_STDPERIPH_CEC
39
-#include "stm32f10x_cec.h"
40
-#endif
41
-#ifdef RTE_DEVICE_STDPERIPH_CRC
42
-#include "stm32f10x_crc.h"
43
-#endif
44
-#ifdef RTE_DEVICE_STDPERIPH_DAC
45
-#include "stm32f10x_dac.h"
46
-#endif
47
-#ifdef RTE_DEVICE_STDPERIPH_DBGMCU
48
-#include "stm32f10x_dbgmcu.h"
49
-#endif
50
-#ifdef RTE_DEVICE_STDPERIPH_DMA
51
-#include "stm32f10x_dma.h"
52
-#endif
53
-#ifdef RTE_DEVICE_STDPERIPH_EXTI
54
-#include "stm32f10x_exti.h"
55
-#endif
56
-#ifdef RTE_DEVICE_STDPERIPH_FLASH
57
-#include "stm32f10x_flash.h"
58
-#endif
59
-#ifdef RTE_DEVICE_STDPERIPH_FSMC
60
-#include "stm32f10x_fsmc.h"
61
-#endif
62
-#ifdef RTE_DEVICE_STDPERIPH_GPIO
63
-#include "stm32f10x_gpio.h"
64
-#endif
65
-#ifdef RTE_DEVICE_STDPERIPH_I2C
66
-#include "stm32f10x_i2c.h"
67
-#endif
68
-#ifdef RTE_DEVICE_STDPERIPH_IWDG
69
-#include "stm32f10x_iwdg.h"
70
-#endif
71
-#ifdef RTE_DEVICE_STDPERIPH_PWR
72
-#include "stm32f10x_pwr.h"
73
-#endif
74
-#ifdef RTE_DEVICE_STDPERIPH_RCC
75
-#include "stm32f10x_rcc.h"
76
-#endif
77
-#ifdef RTE_DEVICE_STDPERIPH_RTC
78
-#include "stm32f10x_rtc.h"
79
-#endif
80
-#ifdef RTE_DEVICE_STDPERIPH_SDIO
81
-#include "stm32f10x_sdio.h"
82
-#endif
83
-#ifdef RTE_DEVICE_STDPERIPH_SPI
84
-#include "stm32f10x_spi.h"
85
-#endif
86
-#ifdef RTE_DEVICE_STDPERIPH_TIM
87
-#include "stm32f10x_tim.h"
88
-#endif
89
-#ifdef RTE_DEVICE_STDPERIPH_USART
90
-#include "stm32f10x_usart.h"
91
-#endif
92
-#ifdef RTE_DEVICE_STDPERIPH_WWDG
93
-#include "stm32f10x_wwdg.h"
94
-#endif
95
-#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
96
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
97
-#endif
98
-
99
-/* Exported types ------------------------------------------------------------*/
100
-/* Exported constants --------------------------------------------------------*/
101
-/* Uncomment the line below to expanse the "assert_param" macro in the 
102
-   Standard Peripheral Library drivers code */
103
-/* #define USE_FULL_ASSERT    1 */
104
-
105
-/* Exported macro ------------------------------------------------------------*/
106
-#ifdef  USE_FULL_ASSERT
107
-
108
-/**
109
-  * @brief  The assert_param macro is used for function's parameters check.
110
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
111
-  *         the name of the source file and the source line number of the call 
112
-  *         that failed. If expr is true, it returns no value.
113
-  * @retval None
114
-  */
115
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
116
-/* Exported functions ------------------------------------------------------- */
117
-  void assert_failed(uint8_t* file, uint32_t line);
118
-#else
119
-  #define assert_param(expr) ((void)0)
120
-#endif /* USE_FULL_ASSERT */
121
-
122
-#endif /* __STM32F10x_CONF_H */
123
-
124
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 0
- 1094
software/robot/RTE/Device/STM32F103RB/.svn/text-base/system_stm32f10x.c.svn-base
File diff suppressed because it is too large
View File


+ 0
- 1690
software/robot/RTE/Device/STM32F103RB/RTE_Device.h
File diff suppressed because it is too large
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+ 0
- 307
software/robot/RTE/Device/STM32F103RB/startup_stm32f10x_md.s View File

@@ -1,307 +0,0 @@
1
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
2
-;* File Name          : startup_stm32f10x_md.s
3
-;* Author             : MCD Application Team
4
-;* Version            : V3.5.0
5
-;* Date               : 11-March-2011
6
-;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
7
-;*                      toolchain.  
8
-;*                      This module performs:
9
-;*                      - Set the initial SP
10
-;*                      - Set the initial PC == Reset_Handler
11
-;*                      - Set the vector table entries with the exceptions ISR address
12
-;*                      - Configure the clock system
13
-;*                      - Branches to __main in the C library (which eventually
14
-;*                        calls main()).
15
-;*                      After Reset the CortexM3 processor is in Thread mode,
16
-;*                      priority is Privileged, and the Stack is set to Main.
17
-;* <<< Use Configuration Wizard in Context Menu >>>   
18
-;*******************************************************************************
19
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
20
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
21
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
22
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
23
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
24
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25
-;*******************************************************************************
26
-
27
-; Amount of memory (in bytes) allocated for Stack
28
-; Tailor this value to your application needs
29
-; <h> Stack Configuration
30
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31
-; </h>
32
-
33
-Stack_Size      EQU     0x00000400
34
-
35
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
36
-Stack_Mem       SPACE   Stack_Size
37
-__initial_sp
38
-
39
-
40
-; <h> Heap Configuration
41
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42
-; </h>
43
-
44
-Heap_Size       EQU     0x00000200
45
-
46
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
47
-__heap_base
48
-Heap_Mem        SPACE   Heap_Size
49
-__heap_limit
50
-
51
-                PRESERVE8
52
-                THUMB
53
-
54
-
55
-; Vector Table Mapped to Address 0 at Reset
56
-                AREA    RESET, DATA, READONLY
57
-                EXPORT  __Vectors
58
-                EXPORT  __Vectors_End
59
-                EXPORT  __Vectors_Size
60
-
61
-__Vectors       DCD     __initial_sp               ; Top of Stack
62
-                DCD     Reset_Handler              ; Reset Handler
63
-                DCD     NMI_Handler                ; NMI Handler
64
-                DCD     HardFault_Handler          ; Hard Fault Handler
65
-                DCD     MemManage_Handler          ; MPU Fault Handler
66
-                DCD     BusFault_Handler           ; Bus Fault Handler
67
-                DCD     UsageFault_Handler         ; Usage Fault Handler
68
-                DCD     0                          ; Reserved
69
-                DCD     0                          ; Reserved
70
-                DCD     0                          ; Reserved
71
-                DCD     0                          ; Reserved
72
-                DCD     SVC_Handler                ; SVCall Handler
73
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
74
-                DCD     0                          ; Reserved
75
-                DCD     PendSV_Handler             ; PendSV Handler
76
-                DCD     SysTick_Handler            ; SysTick Handler
77
-
78
-                ; External Interrupts
79
-                DCD     WWDG_IRQHandler            ; Window Watchdog
80
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
81
-                DCD     TAMPER_IRQHandler          ; Tamper
82
-                DCD     RTC_IRQHandler             ; RTC
83
-                DCD     FLASH_IRQHandler           ; Flash
84
-                DCD     RCC_IRQHandler             ; RCC
85
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
86
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
87
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
88
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
89
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
90
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
91
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
92
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
93
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
94
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
95
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
96
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
97
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
98
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
99
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
100
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
101
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
102
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
103
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
104
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
105
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
106
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
107
-                DCD     TIM2_IRQHandler            ; TIM2
108
-                DCD     TIM3_IRQHandler            ; TIM3
109
-                DCD     TIM4_IRQHandler            ; TIM4
110
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
111
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
112
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
113
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
114
-                DCD     SPI1_IRQHandler            ; SPI1
115
-                DCD     SPI2_IRQHandler            ; SPI2
116
-                DCD     USART1_IRQHandler          ; USART1
117
-                DCD     USART2_IRQHandler          ; USART2
118
-                DCD     USART3_IRQHandler          ; USART3
119
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
120
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
121
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
122
-__Vectors_End
123
-
124
-__Vectors_Size  EQU  __Vectors_End - __Vectors
125
-
126
-                AREA    |.text|, CODE, READONLY
127
-
128
-; Reset handler
129
-Reset_Handler    PROC
130
-                 EXPORT  Reset_Handler             [WEAK]
131
-     IMPORT  __main
132
-     IMPORT  SystemInit
133
-                 LDR     R0, =SystemInit
134
-                 BLX     R0
135
-                 LDR     R0, =__main
136
-                 BX      R0
137
-                 ENDP
138
-
139
-; Dummy Exception Handlers (infinite loops which can be modified)
140
-
141
-NMI_Handler     PROC
142
-                EXPORT  NMI_Handler                [WEAK]
143
-                B       .
144
-                ENDP
145
-HardFault_Handler\
146
-                PROC
147
-                EXPORT  HardFault_Handler          [WEAK]
148
-                B       .
149
-                ENDP
150
-MemManage_Handler\
151
-                PROC
152
-                EXPORT  MemManage_Handler          [WEAK]
153
-                B       .
154
-                ENDP
155
-BusFault_Handler\
156
-                PROC
157
-                EXPORT  BusFault_Handler           [WEAK]
158
-                B       .
159
-                ENDP
160
-UsageFault_Handler\
161
-                PROC
162
-                EXPORT  UsageFault_Handler         [WEAK]
163
-                B       .
164
-                ENDP
165
-SVC_Handler     PROC
166
-                EXPORT  SVC_Handler                [WEAK]
167
-                B       .
168
-                ENDP
169
-DebugMon_Handler\
170
-                PROC
171
-                EXPORT  DebugMon_Handler           [WEAK]
172
-                B       .
173
-                ENDP
174
-PendSV_Handler  PROC
175
-                EXPORT  PendSV_Handler             [WEAK]
176
-                B       .
177
-                ENDP
178
-SysTick_Handler PROC
179
-                EXPORT  SysTick_Handler            [WEAK]
180
-                B       .
181
-                ENDP
182
-
183
-Default_Handler PROC
184
-
185
-                EXPORT  WWDG_IRQHandler            [WEAK]
186
-                EXPORT  PVD_IRQHandler             [WEAK]
187
-                EXPORT  TAMPER_IRQHandler          [WEAK]
188
-                EXPORT  RTC_IRQHandler             [WEAK]
189
-                EXPORT  FLASH_IRQHandler           [WEAK]
190
-                EXPORT  RCC_IRQHandler             [WEAK]
191
-                EXPORT  EXTI0_IRQHandler           [WEAK]
192
-                EXPORT  EXTI1_IRQHandler           [WEAK]
193
-                EXPORT  EXTI2_IRQHandler           [WEAK]
194
-                EXPORT  EXTI3_IRQHandler           [WEAK]
195
-                EXPORT  EXTI4_IRQHandler           [WEAK]
196
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
197
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
198
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
199
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
200
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
201
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
202
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
203
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
204
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
205
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
206
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
207
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
208
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
209
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
210
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
211
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
212
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
213
-                EXPORT  TIM2_IRQHandler            [WEAK]
214
-                EXPORT  TIM3_IRQHandler            [WEAK]
215
-                EXPORT  TIM4_IRQHandler            [WEAK]
216
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
217
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
218
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
219
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
220
-                EXPORT  SPI1_IRQHandler            [WEAK]
221
-                EXPORT  SPI2_IRQHandler            [WEAK]
222
-                EXPORT  USART1_IRQHandler          [WEAK]
223
-                EXPORT  USART2_IRQHandler          [WEAK]
224
-                EXPORT  USART3_IRQHandler          [WEAK]
225
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
226
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
227
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
228
-
229
-WWDG_IRQHandler
230
-PVD_IRQHandler
231
-TAMPER_IRQHandler
232
-RTC_IRQHandler
233
-FLASH_IRQHandler
234
-RCC_IRQHandler
235
-EXTI0_IRQHandler
236
-EXTI1_IRQHandler
237
-EXTI2_IRQHandler
238
-EXTI3_IRQHandler
239
-EXTI4_IRQHandler
240
-DMA1_Channel1_IRQHandler
241
-DMA1_Channel2_IRQHandler
242
-DMA1_Channel3_IRQHandler
243
-DMA1_Channel4_IRQHandler
244
-DMA1_Channel5_IRQHandler
245
-DMA1_Channel6_IRQHandler
246
-DMA1_Channel7_IRQHandler
247
-ADC1_2_IRQHandler
248
-USB_HP_CAN1_TX_IRQHandler
249
-USB_LP_CAN1_RX0_IRQHandler
250
-CAN1_RX1_IRQHandler
251
-CAN1_SCE_IRQHandler
252
-EXTI9_5_IRQHandler
253
-TIM1_BRK_IRQHandler
254
-TIM1_UP_IRQHandler
255
-TIM1_TRG_COM_IRQHandler
256
-TIM1_CC_IRQHandler
257
-TIM2_IRQHandler
258
-TIM3_IRQHandler
259
-TIM4_IRQHandler
260
-I2C1_EV_IRQHandler
261
-I2C1_ER_IRQHandler
262
-I2C2_EV_IRQHandler
263
-I2C2_ER_IRQHandler
264
-SPI1_IRQHandler
265
-SPI2_IRQHandler
266
-USART1_IRQHandler
267
-USART2_IRQHandler
268
-USART3_IRQHandler
269
-EXTI15_10_IRQHandler
270
-RTCAlarm_IRQHandler
271
-USBWakeUp_IRQHandler
272
-
273
-                B       .
274
-
275
-                ENDP
276
-
277
-                ALIGN
278
-
279
-;*******************************************************************************
280
-; User Stack and Heap initialization
281
-;*******************************************************************************
282
-                 IF      :DEF:__MICROLIB           
283
-                
284
-                 EXPORT  __initial_sp
285
-                 EXPORT  __heap_base
286
-                 EXPORT  __heap_limit
287
-                
288
-                 ELSE
289
-                
290
-                 IMPORT  __use_two_region_memory
291
-                 EXPORT  __user_initial_stackheap
292
-                 
293
-__user_initial_stackheap
294
-
295
-                 LDR     R0, =  Heap_Mem
296
-                 LDR     R1, =(Stack_Mem + Stack_Size)
297
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
298
-                 LDR     R3, = Stack_Mem
299
-                 BX      LR
300
-
301
-                 ALIGN
302
-
303
-                 ENDIF
304
-
305
-                 END
306
-
307
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

+ 0
- 124
software/robot/RTE/Device/STM32F103RB/stm32f10x_conf.h View File

@@ -1,124 +0,0 @@
1
-/**
2
-  ******************************************************************************
3
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 
4
-  * @author  MCD Application Team
5
-  * @version V3.5.0
6
-  * @date    08-April-2011
7
-  * @brief   Library configuration file.
8
-  ******************************************************************************
9
-  * @attention
10
-  *
11
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17
-  *
18
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19
-  ******************************************************************************
20
-  */
21
-
22
-/* Define to prevent recursive inclusion -------------------------------------*/
23
-#ifndef __STM32F10x_CONF_H
24
-#define __STM32F10x_CONF_H
25
-
26
-/* Run Time Environment will set specific #define for each selected module below */
27
-#include "RTE_Components.h"
28
-
29
-#ifdef RTE_DEVICE_STDPERIPH_ADC
30
-#include "stm32f10x_adc.h"
31
-#endif
32
-#ifdef RTE_DEVICE_STDPERIPH_BKP
33
-#include "stm32f10x_bkp.h"
34
-#endif
35
-#ifdef RTE_DEVICE_STDPERIPH_CAN
36
-#include "stm32f10x_can.h"
37
-#endif
38
-#ifdef RTE_DEVICE_STDPERIPH_CEC
39
-#include "stm32f10x_cec.h"
40
-#endif
41
-#ifdef RTE_DEVICE_STDPERIPH_CRC
42
-#include "stm32f10x_crc.h"
43
-#endif
44
-#ifdef RTE_DEVICE_STDPERIPH_DAC
45
-#include "stm32f10x_dac.h"
46
-#endif
47
-#ifdef RTE_DEVICE_STDPERIPH_DBGMCU
48
-#include "stm32f10x_dbgmcu.h"
49
-#endif
50
-#ifdef RTE_DEVICE_STDPERIPH_DMA
51
-#include "stm32f10x_dma.h"
52
-#endif
53
-#ifdef RTE_DEVICE_STDPERIPH_EXTI
54
-#include "stm32f10x_exti.h"
55
-#endif
56
-#ifdef RTE_DEVICE_STDPERIPH_FLASH
57
-#include "stm32f10x_flash.h"
58
-#endif
59
-#ifdef RTE_DEVICE_STDPERIPH_FSMC
60
-#include "stm32f10x_fsmc.h"
61
-#endif
62
-#ifdef RTE_DEVICE_STDPERIPH_GPIO
63
-#include "stm32f10x_gpio.h"
64
-#endif
65
-#ifdef RTE_DEVICE_STDPERIPH_I2C
66
-#include "stm32f10x_i2c.h"
67
-#endif
68
-#ifdef RTE_DEVICE_STDPERIPH_IWDG
69
-#include "stm32f10x_iwdg.h"
70
-#endif
71
-#ifdef RTE_DEVICE_STDPERIPH_PWR
72
-#include "stm32f10x_pwr.h"
73
-#endif
74
-#ifdef RTE_DEVICE_STDPERIPH_RCC
75
-#include "stm32f10x_rcc.h"
76
-#endif
77
-#ifdef RTE_DEVICE_STDPERIPH_RTC
78
-#include "stm32f10x_rtc.h"
79
-#endif
80
-#ifdef RTE_DEVICE_STDPERIPH_SDIO
81
-#include "stm32f10x_sdio.h"
82
-#endif
83
-#ifdef RTE_DEVICE_STDPERIPH_SPI
84
-#include "stm32f10x_spi.h"
85
-#endif
86
-#ifdef RTE_DEVICE_STDPERIPH_TIM
87
-#include "stm32f10x_tim.h"
88
-#endif
89
-#ifdef RTE_DEVICE_STDPERIPH_USART
90
-#include "stm32f10x_usart.h"
91
-#endif
92
-#ifdef RTE_DEVICE_STDPERIPH_WWDG
93
-#include "stm32f10x_wwdg.h"
94
-#endif
95
-#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
96
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
97
-#endif
98
-
99
-/* Exported types ------------------------------------------------------------*/
100
-/* Exported constants --------------------------------------------------------*/
101
-/* Uncomment the line below to expanse the "assert_param" macro in the 
102
-   Standard Peripheral Library drivers code */
103
-/* #define USE_FULL_ASSERT    1 */
104
-
105
-/* Exported macro ------------------------------------------------------------*/
106
-#ifdef  USE_FULL_ASSERT
107
-
108
-/**
109
-  * @brief  The assert_param macro is used for function's parameters check.
110
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
111
-  *         the name of the source file and the source line number of the call 
112
-  *         that failed. If expr is true, it returns no value.
113
-  * @retval None
114
-  */
115
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
116
-/* Exported functions ------------------------------------------------------- */
117
-  void assert_failed(uint8_t* file, uint32_t line);
118
-#else
119
-  #define assert_param(expr) ((void)0)
120
-#endif /* USE_FULL_ASSERT */
121
-
122
-#endif /* __STM32F10x_CONF_H */
123
-
124
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 0
- 20
software/robot/RTE/_Target_1/RTE_Components.h View File

@@ -1,20 +0,0 @@
1
-
2
-/*
3
- * Auto generated Run-Time-Environment Component Configuration File
4
- *      *** Do not modify ! ***
5
- *
6
- * Project: 'dumber2' 
7
- * Target:  'Target 1' 
8
- */
9
-
10
-#ifndef RTE_COMPONENTS_H
11
-#define RTE_COMPONENTS_H
12
-
13
-
14
-/*
15
- * Define the Device Header File: 
16
- */
17
-#define CMSIS_device_header "stm32f10x.h"
18
-
19
-
20
-#endif /* RTE_COMPONENTS_H */

+ 0
- 109
software/robot/SPI.c View File

@@ -1,109 +0,0 @@
1
-#include "system_dumby.h"
2
-#include <stm32f10x.h>
3
-#include "SPI.h"
4
-
5
-
6
-/**
7
-	* @brief 	Initisalise les pin du GIO en entrée et sortie :
8
-	*				 	PA5 : Clock généré par le maitre
9
-	*	 			 	PA6	: Master Iutput Slave Onput (MISO)
10
-	*					PA7	:	Master Output Slave Input (MOSI)
11
-	*/
12
-
13
-void MAP_pinSpi(void)
14
-{
15
-	GPIO_InitTypeDef Init_Structure;
16
-	
17
-	Init_Structure.GPIO_Pin = GPIO_Pin_5;
18
-	Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
19
-	Init_Structure.GPIO_Speed=GPIO_Speed_50MHz;
20
-	GPIO_Init(GPIOA, &Init_Structure);
21
-	
22
-	Init_Structure.GPIO_Pin = GPIO_Pin_6;
23
-  Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP;
24
-  GPIO_Init(GPIOA, &Init_Structure);
25
-	
26
-	
27
-	Init_Structure.GPIO_Pin = GPIO_Pin_7;
28
-  Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
29
-  GPIO_Init(GPIOA, &Init_Structure);
30
-	
31
-	Init_Structure.GPIO_Pin = GPIO_Pin_13;
32
-	Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
33
-	Init_Structure.GPIO_Speed=GPIO_Speed_50MHz;
34
-	GPIO_Init(GPIOC, &Init_Structure);
35
-	
36
-	
37
-	// A suprimmer aprés le test
38
-	
39
-	Init_Structure.GPIO_Pin = GPIO_Pin_13;
40
-	Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
41
-	Init_Structure.GPIO_Speed=GPIO_Speed_50MHz;
42
-	GPIO_Init(GPIOB, &Init_Structure);
43
-	
44
-	Init_Structure.GPIO_Pin = GPIO_Pin_14;
45
-  Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP;
46
-  GPIO_Init(GPIOB, &Init_Structure);
47
-		
48
-	
49
-	Init_Structure.GPIO_Pin = GPIO_Pin_15;
50
-  Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
51
-  GPIO_Init(GPIOB, &Init_Structure);
52
-	
53
-
54
-	
55
-	
56
-}
57
-
58
-
59
-
60
-/**
61
-	* @brief 	Configure le periphérique SPI. FullDuplex et Slave Mode;
62
-	* 				Pour tester le SPI on testera les envoi et les recepetions avec l'aide du SPI2.
63
-	*					Il sera donc initialiser. Et reboucler.
64
-	*					
65
-	*/
66
-void INIT_SPI(void)
67
-{
68
-	SPI_InitTypeDef SPI_InitStructure;
69
-	
70
-	SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
71
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
72
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
73
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
74
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
75
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
76
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
77
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
78
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
79
-  SPI_Init(SPI1, &SPI_InitStructure);
80
-	
81
-	SPI_Cmd(SPI1, ENABLE);
82
-	
83
-	
84
-	// A suprimmer aprés le test
85
-	SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
86
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
87
-  SPI_Init(SPI2, &SPI_InitStructure);
88
-}
89
-
90
-/**
91
-	*	@brief Configure le Rx de l'esclave (Stm32)
92
-	* 			 
93
-	*/
94
-
95
-void INIT_IT_SPI(void)
96
-{
97
-	NVIC_InitTypeDef NVIC_InitStructure;
98
-
99
-  /* 1 bit for pre-emption priority, 3 bits for subpriority */
100
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
101
-
102
-	/* Configure and enable SPI_SLAVE interrupt --------------------------------*/
103
-  NVIC_InitStructure.NVIC_IRQChannel = SPI1_IRQn;
104
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
105
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
106
-  NVIC_Init(&NVIC_InitStructure);
107
-	SPI_I2S_ITConfig(SPI1, SPI_I2S_IT_RXNE, ENABLE);
108
-
109
-}

+ 0
- 10
software/robot/SPI.h View File

@@ -1,10 +0,0 @@
1
-#ifndef cmde_usart_H
2
-#define cmde_usart_H
3
-
4
-void INIT_SPI(void);
5
-void MAP_pinSpi(void);
6
-
7
-
8
-
9
-#endif 
10
-

+ 0
- 61
software/robot/cmde_spi.c View File

@@ -1,61 +0,0 @@
1
-#include "system_dumby.h"
2
-#include <stm32f10x.h>
3
-#include <string.h>
4
-
5
-#define TBufferSPI   16
6
-SPI_InitTypeDef SPI_InitStructure;
7
-uint16_t tailleT=0;
8
-uint16_t tailleR=0;
9
-char TSPIBuffer[TBufferSPI]={'S','A','L','U','T',0x0D};
10
-char RSPIBuffer[TBufferSPI];
11
-
12
-void SPI_INIT(void)
13
-{
14
-	//Init SPI
15
-	SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
16
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
17
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
18
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
19
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
20
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
21
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
22
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
23
-  SPI_InitStructure.SPI_CRCPolynomial = 0;
24
-  SPI_Init(SPI1, &SPI_InitStructure);
25
-	
26
-	 /* Enable SPI1 */
27
-  SPI_Cmd(SPI1, ENABLE);
28
-}
29
-
30
-
31
-/*
32
-		Le caractére 13 ou 0x0D ou retour chariot, ne peut être reçu ni envoyer.
33
-*/
34
-void SPI_SEND(void)
35
-{
36
-		if(TSPIBuffer[tailleT]!=0x0D)
37
-		{
38
-			while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
39
-			SPI_I2S_SendData(SPI1, TSPIBuffer[tailleT]);
40
-			tailleT++;
41
-		}
42
-		else
43
-		{
44
-			tailleT=0;
45
-		}
46
-
47
-}
48
-
49
-void SPI_RECEP(void)
50
-{		
51
-		  if(SPI_I2S_ReceiveData(SPI1)!=0x0D)
52
-			{
53
-				while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
54
-				RSPIBuffer[tailleR] = SPI_I2S_ReceiveData(SPI1);
55
-				tailleR++;
56
-			}
57
-			else
58
-			{
59
-				tailleR=0;
60
-			}
61
-}

+ 0
- 10
software/robot/cmde_spi.h View File

@@ -1,10 +0,0 @@
1
-#ifndef CMDE_SPI_H
2
-#define CMDE_SPI_H
3
-
4
-#include "stm32f10x.h"
5
-
6
-void SPI_INIT(void);
7
-void SPI_SEND(void);
8
-void SPI_RECEP(void);
9
-
10
-#endif /* CMDE_SPI_H */

+ 0
- 196
software/robot/cmde_usart.c View File

@@ -1,196 +0,0 @@
1
-#include "system_dumby.h"
2
-#include <stm32f10x.h>
3
-#include <string.h>
4
-#include "cmde_usart.h"
5
-#include "Battery.h"
6
-#include "motor.h"
7
-#include <math.h>
8
-#include "MAE.h"
9
-#include <stdlib.h>
10
-#include "gestionCmde.h"
11
-
12
-#define TBuffer   30
13
-
14
-/** @Note
15
-	* Ce fichier contient les fonctions lié à la gestion de la communications avec l'USART :
16
-	* - Fonction definissant les E/S lié à l'usart.
17
-	* - Initialisation de la dma pour l'envoi
18
-	* - Initialisation de façon non bloquante de la reception en polling
19
-	* - Gestions des commandes
20
-	*/
21
-char sendString[TBuffer];
22
-char receiptString[TBuffer];
23
-char message[TBuffer]; // Le traitement de l'emission se fera dans se tableau. On le transferera à la variable sendString au dernier moment de l'envoi.
24
-uint16_t cpt_Rx =0;
25
-uint16_t i;
26
-
27
-// test de k
28
-uint16_t test;
29
-
30
-
31
-
32
-/**
33
-	* @brief 			La fonction mapUsartPin va venir configurer le E/S du GPIO pour correspondre avec le schéma electrique en ressource.
34
-	*							PB7 Analog Input / PB6 Alternate function output.
35
-	*
36
-	* @param  		Aucun
37
-	* @retval 		Aucun
38
-	*/
39
-void MAP_UsartPin()
40
-{
41
-	GPIO_InitTypeDef Init_Structure;
42
-	/// Configure Output ALTERNATE FONCTION PPULL PORT B6 Tx
43
-	Init_Structure.GPIO_Pin = GPIO_Pin_6;
44
-	Init_Structure.GPIO_Mode = GPIO_Mode_AF_PP;
45
-	Init_Structure.GPIO_Speed=GPIO_Speed_50MHz;
46
-	GPIO_Init(GPIOB, &Init_Structure);
47
-	
48
-	/// Configure B7 Rx
49
-	Init_Structure.GPIO_Pin = GPIO_Pin_7;
50
-  Init_Structure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
51
-  GPIO_Init(GPIOB, &Init_Structure);
52
-}
53
-
54
-
55
-
56
-/**
57
-	* @brief 	Initialise la DMA de l'usart avec le buffer d'envoi sentString
58
-	*	
59
-	* @param  Aucun
60
-	* @retval Aucun
61
-	*/
62
-void INIT_DMASend(void)
63
-{
64
-	DMA_InitTypeDef DMA_InitStructure;
65
-  uint32_t i=0;
66
-	
67
-  DMA_DeInit(DMA1_Channel4);
68
-  DMA_InitStructure.DMA_PeripheralBaseAddr = 0x40013804;
69
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)sendString;
70
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
71
-  //DMA_InitStructure.DMA_BufferSize =16;
72
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
73
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
74
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
75
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
76
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
77
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
78
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
79
-  
80
-	
81
-	/* Recherche de la longueur de la chaine a envoyer */
82
-	while ( sendString[i]!=0x0D) 
83
-	{
84
-		i=i+1;
85
-	}
86
-	
87
-	if (i< TBuffer) DMA_InitStructure.DMA_BufferSize =i+1; // I+1 car on arrete la boucle au moment où l'on trouve CR. Mais il faut bien l'envoyer ...
88
-	else DMA_InitStructure.DMA_BufferSize =0; // Hummm, ca semble moisi ce truc ! On a trouvé CR apres la fin du buffer alloué, la chaine n'a pas l'air bien formée
89
-	
90
-	DMA_Init(DMA1_Channel4, &DMA_InitStructure);
91
-}
92
-
93
-void INIT_IT_UsartReceive(void)
94
-{
95
-	   NVIC_InitTypeDef NVIC_InitStructure;
96
-
97
-  /* Enable the USARTz Interrupt */
98
-  NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
99
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
100
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
101
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
102
-  NVIC_Init(&NVIC_InitStructure);
103
-}
104
-
105
-/**
106
-	* @brief Initialise l'UART avec les paramétres suivants : 9600 bauds / 1bits de stop / pas de partité ou de controle
107
-	*	
108
-	* @param  Aucun
109
-	* @retval Aucun
110
-	*/
111
-
112
-void INIT_USART(void)
113
-{
114
-		USART_InitTypeDef USART_InitStructure;
115
-	
116
-		USART_InitStructure.USART_BaudRate = 9600;
117
-		USART_InitStructure.USART_WordLength = USART_WordLength_8b;
118
-		USART_InitStructure.USART_StopBits = USART_StopBits_1;
119
-		USART_InitStructure.USART_Parity = USART_Parity_No;
120
-		USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
121
-		USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
122
-			
123
-		USART_Init(USART1, &USART_InitStructure);
124
-			
125
-		USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE);
126
-		USART_Cmd(USART1, ENABLE);
127
-		GPIO_PinRemapConfig(GPIO_Remap_USART1,ENABLE);
128
-		USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
129
-}
130
-
131
-/**
132
-	* @brief Recevoir les commandes UART sur Rx. Met à jour la position de la virgule et de la taille de la commande.
133
-	*	
134
-	* @param  Aucun
135
-	* @varGlobal cpt_Rx, virgule
136
-	* @retval Aucun
137
-	*/
138
-
139
-void USART1_IRQHandler(void)
140
-{
141
-	volatile uint16_t tmp;
142
-	
143
-	if(USART_GetITStatus(USART1,USART_IT_RXNE) !=RESET)
144
-	{
145
-		receiptString[cpt_Rx] = USART_ReceiveData(USART1);
146
-		if(cpt_Rx<16)
147
-			cpt_Rx++;
148
-		
149
-		if(receiptString[cpt_Rx-1]==13)
150
-		{
151
-			if(verifyCheckSum()==0)
152
-			{
153
-				manageCmd();
154
-			}
155
-			else
156
-				strcpy(sendString,UNKNOW_ANS);
157
-			
158
-			if(Dumber.AddOn == FALSE)
159
-			{
160
-					inclusionCheckSum();
161
-					sendDataUSART();
162
-			}
163
-			
164
-			for( i = 0 ; i <cpt_Rx+1;i++)
165
-				receiptString[i]=0;
166
-			cpt_Rx=0;
167
-		}
168
-	}
169
-	// Code pour éviter les caractéres fantôme
170
-	tmp = USART1->SR;
171
-	tmp = USART1->CR1;
172
-	tmp = USART1->CR2;
173
-	tmp = USART1->CR3;
174
-	tmp = USART1->BRR;
175
-	tmp = USART1->GTPR;
176
-	tmp = USART1->SR;
177
-	
178
-	USART_ClearFlag(USART1, USART_FLAG_RXNE);
179
-}
180
-
181
-/**
182
-	* @brief Chargement du buffer Tx dans la DMA et envoi via l'USART
183
-	*	
184
-	* @param  Aucun
185
-	* @retval Aucun
186
-	*/
187
-void sendDataUSART(void)
188
-{
189
-	INIT_DMASend();
190
-	DMA_Cmd(DMA1_Channel4, ENABLE);
191
-	while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET)
192
-	{
193
-	}
194
-	for(i=0; i<TBuffer;i++)
195
-		sendString[i]=0;
196
-}

+ 0
- 0
software/robot/cmde_usart.h View File


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