Browse Source

Initial commit

Neluji 8 months ago
commit
c3308df689
59 changed files with 56040 additions and 0 deletions
  1. 4
    0
      .gitignore
  2. 57
    0
      Inc/stm32_assert.h
  3. 10238
    0
      Inc/stm32f103xb.h
  4. 220
    0
      Inc/stm32f1xx.h
  5. 46
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      Inc/stm32f1xx_it.h
  6. 98
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      Inc/system_stm32f1xx.h
  7. 3932
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      LLDrivers/inc/stm32f1xx_ll_adc.h
  8. 1015
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      LLDrivers/inc/stm32f1xx_ll_bus.h
  9. 640
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      LLDrivers/inc/stm32f1xx_ll_cortex.h
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      LLDrivers/inc/stm32f1xx_ll_crc.h
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      LLDrivers/inc/stm32f1xx_ll_dac.h
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      LLDrivers/inc/stm32f1xx_ll_dma.h
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      LLDrivers/inc/stm32f1xx_ll_exti.h
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      LLDrivers/inc/stm32f1xx_ll_fsmc.h
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      LLDrivers/inc/stm32f1xx_ll_gpio.h
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      LLDrivers/inc/stm32f1xx_ll_i2c.h
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      LLDrivers/inc/stm32f1xx_ll_iwdg.h
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      LLDrivers/inc/stm32f1xx_ll_pwr.h
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      LLDrivers/inc/stm32f1xx_ll_rcc.h
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      LLDrivers/inc/stm32f1xx_ll_rtc.h
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      LLDrivers/inc/stm32f1xx_ll_sdmmc.h
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      LLDrivers/inc/stm32f1xx_ll_spi.h
  23. 574
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      LLDrivers/inc/stm32f1xx_ll_system.h
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      LLDrivers/inc/stm32f1xx_ll_tim.h
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      LLDrivers/inc/stm32f1xx_ll_usart.h
  26. 651
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      LLDrivers/inc/stm32f1xx_ll_usb.h
  27. 266
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      LLDrivers/inc/stm32f1xx_ll_utils.h
  28. 318
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      LLDrivers/inc/stm32f1xx_ll_wwdg.h
  29. 886
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      LLDrivers/src/stm32f1xx_ll_adc.c
  30. 108
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      LLDrivers/src/stm32f1xx_ll_crc.c
  31. 274
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      LLDrivers/src/stm32f1xx_ll_dac.c
  32. 314
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      LLDrivers/src/stm32f1xx_ll_dma.c
  33. 215
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      LLDrivers/src/stm32f1xx_ll_exti.c
  34. 985
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      LLDrivers/src/stm32f1xx_ll_fsmc.c
  35. 253
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      LLDrivers/src/stm32f1xx_ll_gpio.c
  36. 221
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      LLDrivers/src/stm32f1xx_ll_i2c.c
  37. 86
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      LLDrivers/src/stm32f1xx_ll_pwr.c
  38. 474
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      LLDrivers/src/stm32f1xx_ll_rcc.c
  39. 544
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      LLDrivers/src/stm32f1xx_ll_rtc.c
  40. 1521
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      LLDrivers/src/stm32f1xx_ll_sdmmc.c
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      LLDrivers/src/stm32f1xx_ll_spi.c
  42. 1198
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      LLDrivers/src/stm32f1xx_ll_tim.c
  43. 446
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      LLDrivers/src/stm32f1xx_ll_usart.c
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      LLDrivers/src/stm32f1xx_ll_usb.c
  45. 606
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      LLDrivers/src/stm32f1xx_ll_utils.c
  46. 97
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      MDK-ARM/DebugConfig/NUCLEO-F103RB_STM32F103RB_1.0.0.dbgconf
  47. 97
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      MDK-ARM/DebugConfig/Simulateur_STM32F103RB_1.0.0.dbgconf
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      MDK-ARM/Project.uvoptx
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      MDK-ARM/Project.uvprojx
  50. 21
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      MDK-ARM/RTE/_NUCLEO-F103RB/RTE_Components.h
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      MDK-ARM/RTE/_Simulateur/RTE_Components.h
  52. 307
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      MDK-ARM/startup_stm32f103xb.s
  53. 183
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      MyDrivers/MyTimer.c
  54. 70
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      MyDrivers/MyTimer.h
  55. 143
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      README.md
  56. 713
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      Release_Notes.html
  57. 1
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      Services/services.txt
  58. 139
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      Src/main.c
  59. 419
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      Src/system_stm32f1xx.c

+ 4
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.gitignore View File

@@ -0,0 +1,4 @@
1
+*.lst
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+*.scvd
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+*.uvguix.*
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+/MDK-ARM/NUCLEO-F103RB

+ 57
- 0
Inc/stm32_assert.h View File

@@ -0,0 +1,57 @@
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+/**
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+  ******************************************************************************
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+  * @file    stm32_assert.h
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+  * @author  MCD Application Team
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+  * @brief   STM32 assert template file.
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+  *          This file should be copied to the application folder and renamed
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+  *          to stm32_assert.h.
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+  ******************************************************************************
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+  * @attention
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+  *
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+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
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+  * All rights reserved.</center></h2>
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+  *
14
+  * This software component is licensed by ST under BSD 3-Clause license,
15
+  * the "License"; You may not use this file except in compliance with the
16
+  * License. You may obtain a copy of the License at:
17
+  *                        opensource.org/licenses/BSD-3-Clause
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+  *
19
+  ******************************************************************************
20
+  */
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+
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+/* Define to prevent recursive inclusion -------------------------------------*/
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+#ifndef __STM32_ASSERT_H
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+#define __STM32_ASSERT_H
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+
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+#ifdef __cplusplus
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+ extern "C" {
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+#endif
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+
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+/* Exported types ------------------------------------------------------------*/
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+/* Exported constants --------------------------------------------------------*/
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+/* Includes ------------------------------------------------------------------*/
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+/* Exported macro ------------------------------------------------------------*/
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+#ifdef  USE_FULL_ASSERT
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+/**
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+  * @brief  The assert_param macro is used for function's parameters check.
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+  * @param  expr: If expr is false, it calls assert_failed function
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+  *         which reports the name of the source file and the source
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+  *         line number of the call that failed.
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+  *         If expr is true, it returns no value.
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+  * @retval None
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+  */
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+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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+/* Exported functions ------------------------------------------------------- */
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+  void assert_failed(uint8_t* file, uint32_t line);
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+#else
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+  #define assert_param(expr) ((void)0U)
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+#endif /* USE_FULL_ASSERT */
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+
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+#ifdef __cplusplus
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+}
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+#endif
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+
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+#endif /* __STM32_ASSERT_H */
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+
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+
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+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Inc/stm32f103xb.h
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+ 220
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Inc/stm32f1xx.h View File

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+/**
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+  ******************************************************************************
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+  * @file    stm32f1xx.h
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+  * @author  MCD Application Team
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+  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
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+  *
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+  *          The file is the unique include file that the application programmer
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+  *          is using in the C source code, usually in main.c. This file contains:
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+  *            - Configuration section that allows to select:
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+  *              - The STM32F1xx device used in the target application
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+  *              - To use or not the peripheral’s drivers in application code(i.e. 
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+  *                code will be based on direct access to peripheral’s registers 
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+  *                rather than drivers API), this option is controlled by 
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+  *                "#define USE_HAL_DRIVER"
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+  *  
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+  ******************************************************************************
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+  * @attention
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+  *
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+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
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+  * All rights reserved.</center></h2>
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+  *
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+  * This software component is licensed by ST under BSD 3-Clause license,
23
+  * the "License"; You may not use this file except in compliance with the
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+  * License. You may obtain a copy of the License at:
25
+  *                        opensource.org/licenses/BSD-3-Clause
26
+  *
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+  ******************************************************************************
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+  */
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+
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+/** @addtogroup CMSIS
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+  * @{
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+  */
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+
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+/** @addtogroup stm32f1xx
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+  * @{
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+  */
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+    
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+#ifndef __STM32F1XX_H
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+#define __STM32F1XX_H
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+
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+#ifdef __cplusplus
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+ extern "C" {
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+#endif /* __cplusplus */
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+  
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+/** @addtogroup Library_configuration_section
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+  * @{
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+  */
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+
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+/**
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+  * @brief STM32 Family
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+  */
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+#if !defined (STM32F1)
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+#define STM32F1
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+#endif /* STM32F1 */
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+
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+/* Uncomment the line below according to the target STM32L device used in your 
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+   application 
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+  */
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+
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+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
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+    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
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+    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
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+  /* #define STM32F100xB  */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
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+  /* #define STM32F100xE */    /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
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+  /* #define STM32F101x6  */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
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+  /* #define STM32F101xB  */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
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+  /* #define STM32F101xE */    /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 
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+  /* #define STM32F101xG  */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
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+  /* #define STM32F102x6 */    /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
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+  /* #define STM32F102xB  */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
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+  /* #define STM32F103x6  */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
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+  /* #define STM32F103xB  */   /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
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+  /* #define STM32F103xE */    /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
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+  /* #define STM32F103xG  */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
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+  /* #define STM32F105xC */    /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
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+  /* #define STM32F107xC  */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  
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+#endif
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+
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+/*  Tip: To avoid modifying this file each time you need to switch between these
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+        devices, you can define the device in your toolchain compiler preprocessor.
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+  */
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+  
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+#if !defined  (USE_HAL_DRIVER)
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+/**
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+ * @brief Comment the line below if you will not use the peripherals drivers.
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+   In this case, these drivers will not be included and the application code will 
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+   be based on direct access to peripherals registers 
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+   */
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+  /*#define USE_HAL_DRIVER */
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+#endif /* USE_HAL_DRIVER */
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+
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+/**
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+  * @brief CMSIS Device version number V4.3.1
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+  */
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+#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */
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+#define __STM32F1_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
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+#define __STM32F1_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
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+#define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
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+#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
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+                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
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+                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
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+                                       |(__STM32F1_CMSIS_VERSION_RC))
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+
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+/**
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+  * @}
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+  */
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+
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+/** @addtogroup Device_Included
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+  * @{
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+  */
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+
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+#if defined(STM32F100xB)
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+  #include "stm32f100xb.h"
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+#elif defined(STM32F100xE)
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+  #include "stm32f100xe.h"
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+#elif defined(STM32F101x6)
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+  #include "stm32f101x6.h"
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+#elif defined(STM32F101xB)
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+  #include "stm32f101xb.h"
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+#elif defined(STM32F101xE)
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+  #include "stm32f101xe.h"
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+#elif defined(STM32F101xG)
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+  #include "stm32f101xg.h"
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+#elif defined(STM32F102x6)
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+  #include "stm32f102x6.h"
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+#elif defined(STM32F102xB)
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+  #include "stm32f102xb.h"
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+#elif defined(STM32F103x6)
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+  #include "stm32f103x6.h"
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+#elif defined(STM32F103xB)
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+  #include "stm32f103xb.h"
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+#elif defined(STM32F103xE)
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+  #include "stm32f103xe.h"
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+#elif defined(STM32F103xG)
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+  #include "stm32f103xg.h"
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+#elif defined(STM32F105xC)
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+  #include "stm32f105xc.h"
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+#elif defined(STM32F107xC)
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+  #include "stm32f107xc.h"
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+#else
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+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
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+#endif
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+
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+/**
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+  * @}
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+  */
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+
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+/** @addtogroup Exported_types
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+  * @{
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+  */  
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+typedef enum 
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+{
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+  RESET = 0, 
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+  SET = !RESET
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+} FlagStatus, ITStatus;
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+
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+typedef enum 
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+{
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+  DISABLE = 0, 
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+  ENABLE = !DISABLE
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+} FunctionalState;
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+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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+
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+typedef enum
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+{
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+  SUCCESS = 0U,
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+  ERROR = !SUCCESS
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+} ErrorStatus;
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+
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+/**
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+  * @}
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+  */
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+
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+
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+/** @addtogroup Exported_macros
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+  * @{
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+  */
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+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
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+
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+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
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+
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+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
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+
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+#define CLEAR_REG(REG)        ((REG) = (0x0))
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+
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+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
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+
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+#define READ_REG(REG)         ((REG))
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+
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+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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+
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+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
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+
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+
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+/**
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+  * @}
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+  */
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+
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+#if defined (USE_HAL_DRIVER)
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+ #include "stm32f1xx_hal.h"
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+#endif /* USE_HAL_DRIVER */
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+
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+
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+#ifdef __cplusplus
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+}
206
+#endif /* __cplusplus */
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+
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+#endif /* __STM32F1xx_H */
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+/**
210
+  * @}
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+  */
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+
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+/**
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+  * @}
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+  */
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+  
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+
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+
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+
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+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Inc/stm32f1xx_it.h View File

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+/**
2
+  ******************************************************************************
3
+  * @file    Examples_LL/GPIO/GPIO_InfiniteLedToggling/Inc/stm32f1xx_it.h
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+  * @author  MCD Application Team
5
+  * @brief   This file contains the headers of the interrupt handlers.
6
+	* !! modif : include main.h enlevé
7
+  ******************************************************************************
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+  * @attention
9
+  *
10
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
11
+  * All rights reserved.</center></h2>
12
+  *
13
+  * This software component is licensed by ST under BSD 3-Clause license,
14
+  * the "License"; You may not use this file except in compliance with the
15
+  * License. You may obtain a copy of the License at:
16
+  *                        opensource.org/licenses/BSD-3-Clause
17
+  *
18
+  ******************************************************************************
19
+  */
20
+
21
+/* Define to prevent recursive inclusion -------------------------------------*/
22
+#ifndef __STM32F1xx_IT_H
23
+#define __STM32F1xx_IT_H
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+
25
+#ifdef __cplusplus
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+extern "C" {
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+#endif
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+
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+
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+void NMI_Handler(void);
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+void HardFault_Handler(void);
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+void MemManage_Handler(void);
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+void BusFault_Handler(void);
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+void UsageFault_Handler(void);
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+void SVC_Handler(void);
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+void DebugMon_Handler(void);
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+void PendSV_Handler(void);
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+void SysTick_Handler(void);
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+
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+#ifdef __cplusplus
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+}
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+#endif
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+
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+#endif /* __STM32F1xx_IT_H */
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+
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+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Inc/system_stm32f1xx.h View File

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+/**
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+  ******************************************************************************
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+  * @file    system_stm32f10x.h
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+  * @author  MCD Application Team
5
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
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+  ******************************************************************************
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+  * @attention
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+  *
9
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
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+
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+/** @addtogroup CMSIS
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+  * @{
22
+  */
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+
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+/** @addtogroup stm32f10x_system
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+  * @{
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+  */  
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+  
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+/**
29
+  * @brief Define to prevent recursive inclusion
30
+  */
31
+#ifndef __SYSTEM_STM32F10X_H
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+#define __SYSTEM_STM32F10X_H
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+
34
+#ifdef __cplusplus
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+ extern "C" {
36
+#endif 
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+
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+/** @addtogroup STM32F10x_System_Includes
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+  * @{
40
+  */
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+
42
+/**
43
+  * @}
44
+  */
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+
46
+
47
+/** @addtogroup STM32F10x_System_Exported_types
48
+  * @{
49
+  */
50
+
51
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
52
+extern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */
53
+extern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */
54
+
55
+/**
56
+  * @}
57
+  */
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+
59
+/** @addtogroup STM32F10x_System_Exported_Constants
60
+  * @{
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+  */
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+
63
+/**
64
+  * @}
65
+  */
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+
67
+/** @addtogroup STM32F10x_System_Exported_Macros
68
+  * @{
69
+  */
70
+
71
+/**
72
+  * @}
73
+  */
74
+
75
+/** @addtogroup STM32F10x_System_Exported_Functions
76
+  * @{
77
+  */
78
+  
79
+extern void SystemInit(void);
80
+extern void SystemCoreClockUpdate(void);
81
+/**
82
+  * @}
83
+  */
84
+
85
+#ifdef __cplusplus
86
+}
87
+#endif
88
+
89
+#endif /*__SYSTEM_STM32F10X_H */
90
+
91
+/**
92
+  * @}
93
+  */
94
+  
95
+/**
96
+  * @}
97
+  */  
98
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 3932
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LLDrivers/inc/stm32f1xx_ll_adc.h
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+ 1015
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LLDrivers/inc/stm32f1xx_ll_cortex.h View File

@@ -0,0 +1,640 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f1xx_ll_cortex.h
4
+  * @author  MCD Application Team
5
+  * @brief   Header file of CORTEX LL module.
6
+  @verbatim
7
+  ==============================================================================
8
+                     ##### How to use this driver #####
9
+  ==============================================================================
10
+    [..]
11
+    The LL CORTEX driver contains a set of generic APIs that can be
12
+    used by user:
13
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
14
+          functions
15
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
16
+      (+) MPU API to configure and enable regions
17
+          (MPU services provided only on some devices)
18
+      (+) API to access to MCU info (CPUID register)
19
+      (+) API to enable fault handler (SHCSR accesses)
20
+
21
+  @endverbatim
22
+  ******************************************************************************
23
+  * @attention
24
+  *
25
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
26
+  * All rights reserved.</center></h2>
27
+  *
28
+  * This software component is licensed by ST under BSD 3-Clause license,
29
+  * the "License"; You may not use this file except in compliance with the
30
+  * License. You may obtain a copy of the License at:
31
+  *                        opensource.org/licenses/BSD-3-Clause
32
+  *
33
+  ******************************************************************************
34
+  */
35
+
36
+/* Define to prevent recursive inclusion -------------------------------------*/
37
+#ifndef __STM32F1xx_LL_CORTEX_H
38
+#define __STM32F1xx_LL_CORTEX_H
39
+
40
+#ifdef __cplusplus
41
+extern "C" {
42
+#endif
43
+
44
+/* Includes ------------------------------------------------------------------*/
45
+#include "stm32f1xx.h"
46
+
47
+/** @addtogroup STM32F1xx_LL_Driver
48
+  * @{
49
+  */
50
+
51
+/** @defgroup CORTEX_LL CORTEX
52
+  * @{
53
+  */
54
+
55
+/* Private types -------------------------------------------------------------*/
56
+/* Private variables ---------------------------------------------------------*/
57
+
58
+/* Private constants ---------------------------------------------------------*/
59
+
60
+/* Private macros ------------------------------------------------------------*/
61
+
62
+/* Exported types ------------------------------------------------------------*/
63
+/* Exported constants --------------------------------------------------------*/
64
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
65
+  * @{
66
+  */
67
+
68
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
69
+  * @{
70
+  */
71
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
72
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
73
+/**
74
+  * @}
75
+  */
76
+
77
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
78
+  * @{
79
+  */
80
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
81
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
82
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
83
+/**
84
+  * @}
85
+  */
86
+
87
+#if __MPU_PRESENT
88
+
89
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
90
+  * @{
91
+  */
92
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
93
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
94
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
95
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
96
+/**
97
+  * @}
98
+  */
99
+
100
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
101
+  * @{
102
+  */
103
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
104
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
105
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
106
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
107
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
108
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
109
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
110
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
111
+/**
112
+  * @}
113
+  */
114
+
115
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
116
+  * @{
117
+  */
118
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
119
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
120
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
121
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
122
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
123
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
124
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
125
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
126
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
127
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
128
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
129
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
130
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
131
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
132
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
133
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
134
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
135
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
136
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
137
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
138
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
139
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
140
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
141
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
142
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
143
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
144
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
145
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
146
+/**
147
+  * @}
148
+  */
149
+
150
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
151
+  * @{
152
+  */
153
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
154
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
155
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
156
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
157
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
158
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
159
+/**
160
+  * @}
161
+  */
162
+
163
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
164
+  * @{
165
+  */
166
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
167
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
168
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
169
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
170
+/**
171
+  * @}
172
+  */
173
+
174
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
175
+  * @{
176
+  */
177
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
178
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
179
+/**
180
+  * @}
181
+  */
182
+
183
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
184
+  * @{
185
+  */
186
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
187
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
188
+/**
189
+  * @}
190
+  */
191
+
192
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
193
+  * @{
194
+  */
195
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
196
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
197
+/**
198
+  * @}
199
+  */
200
+
201
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
202
+  * @{
203
+  */
204
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
205
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
206
+/**
207
+  * @}
208
+  */
209
+#endif /* __MPU_PRESENT */
210
+/**
211
+  * @}
212
+  */
213
+
214
+/* Exported macro ------------------------------------------------------------*/
215
+
216
+/* Exported functions --------------------------------------------------------*/
217
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
218
+  * @{
219
+  */
220
+
221
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
222
+  * @{
223
+  */
224
+
225
+/**
226
+  * @brief  This function checks if the Systick counter flag is active or not.
227
+  * @note   It can be used in timeout function on application side.
228
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
229
+  * @retval State of bit (1 or 0).
230
+  */
231
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
232
+{
233
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
234
+}
235
+
236
+/**
237
+  * @brief  Configures the SysTick clock source
238
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
239
+  * @param  Source This parameter can be one of the following values:
240
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
241
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
242
+  * @retval None
243
+  */
244
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
245
+{
246
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
247
+  {
248
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
249
+  }
250
+  else
251
+  {
252
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
253
+  }
254
+}
255
+
256
+/**
257
+  * @brief  Get the SysTick clock source
258
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
259
+  * @retval Returned value can be one of the following values:
260
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
261
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
262
+  */
263
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
264
+{
265
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
266
+}
267
+
268
+/**
269
+  * @brief  Enable SysTick exception request
270
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
271
+  * @retval None
272
+  */
273
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
274
+{
275
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
276
+}
277
+
278
+/**
279
+  * @brief  Disable SysTick exception request
280
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
281
+  * @retval None
282
+  */
283
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
284
+{
285
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
286
+}
287
+
288
+/**
289
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
290
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
291
+  * @retval State of bit (1 or 0).
292
+  */
293
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
294
+{
295
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
296
+}
297
+
298
+/**
299
+  * @}
300
+  */
301
+
302
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
303
+  * @{
304
+  */
305
+
306
+/**
307
+  * @brief  Processor uses sleep as its low power mode
308
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
309
+  * @retval None
310
+  */
311
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
312
+{
313
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
314
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
315
+}
316
+
317
+/**
318
+  * @brief  Processor uses deep sleep as its low power mode
319
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
320
+  * @retval None
321
+  */
322
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
323
+{
324
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
325
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
326
+}
327
+
328
+/**
329
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
330
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
331
+  *         empty main application.
332
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
333
+  * @retval None
334
+  */
335
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
336
+{
337
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
338
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
339
+}
340
+
341
+/**
342
+  * @brief  Do not sleep when returning to Thread mode.
343
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
344
+  * @retval None
345
+  */
346
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
347
+{
348
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
349
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
350
+}
351
+
352
+/**
353
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
354
+  *         processor.
355
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
356
+  * @retval None
357
+  */
358
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
359
+{
360
+  /* Set SEVEONPEND bit of Cortex System Control Register */
361
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
362
+}
363
+
364
+/**
365
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
366
+  *         excluded
367
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
368
+  * @retval None
369
+  */
370
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
371
+{
372
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
373
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
374
+}
375
+
376
+/**
377
+  * @}
378
+  */
379
+
380
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
381
+  * @{
382
+  */
383
+
384
+/**
385
+  * @brief  Enable a fault in System handler control register (SHCSR)
386
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
387
+  * @param  Fault This parameter can be a combination of the following values:
388
+  *         @arg @ref LL_HANDLER_FAULT_USG
389
+  *         @arg @ref LL_HANDLER_FAULT_BUS
390
+  *         @arg @ref LL_HANDLER_FAULT_MEM
391
+  * @retval None
392
+  */
393
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
394
+{
395
+  /* Enable the system handler fault */
396
+  SET_BIT(SCB->SHCSR, Fault);
397
+}
398
+
399
+/**
400
+  * @brief  Disable a fault in System handler control register (SHCSR)
401
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
402
+  * @param  Fault This parameter can be a combination of the following values:
403
+  *         @arg @ref LL_HANDLER_FAULT_USG
404
+  *         @arg @ref LL_HANDLER_FAULT_BUS
405
+  *         @arg @ref LL_HANDLER_FAULT_MEM
406
+  * @retval None
407
+  */
408
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
409
+{
410
+  /* Disable the system handler fault */
411
+  CLEAR_BIT(SCB->SHCSR, Fault);
412
+}
413
+
414
+/**
415
+  * @}
416
+  */
417
+
418
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
419
+  * @{
420
+  */
421
+
422
+/**
423
+  * @brief  Get Implementer code
424
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
425
+  * @retval Value should be equal to 0x41 for ARM
426
+  */
427
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
428
+{
429
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
430
+}
431
+
432
+/**
433
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
434
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
435
+  * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
436
+  */
437
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
438
+{
439
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
440
+}
441
+
442
+/**
443
+  * @brief  Get Constant number
444
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
445
+  * @retval Value should be equal to 0xF for Cortex-M3 devices
446
+  */
447
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
448
+{
449
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
450
+}
451
+
452
+/**
453
+  * @brief  Get Part number
454
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
455
+  * @retval Value should be equal to 0xC23 for Cortex-M3
456
+  */
457
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
458
+{
459
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
460
+}
461
+
462
+/**
463
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
464
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
465
+  * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
466
+  */
467
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
468
+{
469
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
470
+}
471
+
472
+/**
473
+  * @}
474
+  */
475
+
476
+#if __MPU_PRESENT
477
+/** @defgroup CORTEX_LL_EF_MPU MPU
478
+  * @{
479
+  */
480
+
481
+/**
482
+  * @brief  Enable MPU with input options
483
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
484
+  * @param  Options This parameter can be one of the following values:
485
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
486
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
487
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
488
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
489
+  * @retval None
490
+  */
491
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
492
+{
493
+  /* Enable the MPU*/
494
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
495
+  /* Ensure MPU settings take effects */
496
+  __DSB();
497
+  /* Sequence instruction fetches using update settings */
498
+  __ISB();
499
+}
500
+
501
+/**
502
+  * @brief  Disable MPU
503
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
504
+  * @retval None
505
+  */
506
+__STATIC_INLINE void LL_MPU_Disable(void)
507
+{
508
+  /* Make sure outstanding transfers are done */
509
+  __DMB();
510
+  /* Disable MPU*/
511
+  WRITE_REG(MPU->CTRL, 0U);
512
+}
513
+
514
+/**
515
+  * @brief  Check if MPU is enabled or not
516
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
517
+  * @retval State of bit (1 or 0).
518
+  */
519
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
520
+{
521
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
522
+}
523
+
524
+/**
525
+  * @brief  Enable a MPU region
526
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
527
+  * @param  Region This parameter can be one of the following values:
528
+  *         @arg @ref LL_MPU_REGION_NUMBER0
529
+  *         @arg @ref LL_MPU_REGION_NUMBER1
530
+  *         @arg @ref LL_MPU_REGION_NUMBER2
531
+  *         @arg @ref LL_MPU_REGION_NUMBER3
532
+  *         @arg @ref LL_MPU_REGION_NUMBER4
533
+  *         @arg @ref LL_MPU_REGION_NUMBER5
534
+  *         @arg @ref LL_MPU_REGION_NUMBER6
535
+  *         @arg @ref LL_MPU_REGION_NUMBER7
536
+  * @retval None
537
+  */
538
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
539
+{
540
+  /* Set Region number */
541
+  WRITE_REG(MPU->RNR, Region);
542
+  /* Enable the MPU region */
543
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
544
+}
545
+
546
+/**
547
+  * @brief  Configure and enable a region
548
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
549
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
550
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
551
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
552
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
553
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
554
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
555
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
556
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
557
+  * @param  Region This parameter can be one of the following values:
558
+  *         @arg @ref LL_MPU_REGION_NUMBER0
559
+  *         @arg @ref LL_MPU_REGION_NUMBER1
560
+  *         @arg @ref LL_MPU_REGION_NUMBER2
561
+  *         @arg @ref LL_MPU_REGION_NUMBER3
562
+  *         @arg @ref LL_MPU_REGION_NUMBER4
563
+  *         @arg @ref LL_MPU_REGION_NUMBER5
564
+  *         @arg @ref LL_MPU_REGION_NUMBER6
565
+  *         @arg @ref LL_MPU_REGION_NUMBER7
566
+  * @param  Address Value of region base address
567
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
568
+  * @param  Attributes This parameter can be a combination of the following values:
569
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
570
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
571
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
572
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
573
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
574
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
575
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
576
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
577
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
578
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
579
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
580
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
581
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
582
+  * @retval None
583
+  */
584
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
585
+{
586
+  /* Set Region number */
587
+  WRITE_REG(MPU->RNR, Region);
588
+  /* Set base address */
589
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
590
+  /* Configure MPU */
591
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
592
+}
593
+
594
+/**
595
+  * @brief  Disable a region
596
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
597
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
598
+  * @param  Region This parameter can be one of the following values:
599
+  *         @arg @ref LL_MPU_REGION_NUMBER0
600
+  *         @arg @ref LL_MPU_REGION_NUMBER1
601
+  *         @arg @ref LL_MPU_REGION_NUMBER2
602
+  *         @arg @ref LL_MPU_REGION_NUMBER3
603
+  *         @arg @ref LL_MPU_REGION_NUMBER4
604
+  *         @arg @ref LL_MPU_REGION_NUMBER5
605
+  *         @arg @ref LL_MPU_REGION_NUMBER6
606
+  *         @arg @ref LL_MPU_REGION_NUMBER7
607
+  * @retval None
608
+  */
609
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
610
+{
611
+  /* Set Region number */
612
+  WRITE_REG(MPU->RNR, Region);
613
+  /* Disable the MPU region */
614
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
615
+}
616
+
617
+/**
618
+  * @}
619
+  */
620
+
621
+#endif /* __MPU_PRESENT */
622
+/**
623
+  * @}
624
+  */
625
+
626
+/**
627
+  * @}
628
+  */
629
+
630
+/**
631
+  * @}
632
+  */
633
+
634
+#ifdef __cplusplus
635
+}
636
+#endif
637
+
638
+#endif /* __STM32F1xx_LL_CORTEX_H */
639
+
640
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 204
- 0
LLDrivers/inc/stm32f1xx_ll_crc.h View File

@@ -0,0 +1,204 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f1xx_ll_crc.h
4
+  * @author  MCD Application Team
5
+  * @brief   Header file of CRC LL module.
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+
20
+/* Define to prevent recursive inclusion -------------------------------------*/
21
+#ifndef STM32F1xx_LL_CRC_H
22
+#define STM32F1xx_LL_CRC_H
23
+
24
+#ifdef __cplusplus
25
+extern "C" {
26
+#endif
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f1xx.h"
30
+
31
+/** @addtogroup STM32F1xx_LL_Driver
32
+  * @{
33
+  */
34
+
35
+#if defined(CRC)
36
+
37
+/** @defgroup CRC_LL CRC
38
+  * @{
39
+  */
40
+
41
+/* Private types -------------------------------------------------------------*/
42
+/* Private variables ---------------------------------------------------------*/
43
+/* Private constants ---------------------------------------------------------*/
44
+/* Private macros ------------------------------------------------------------*/
45
+
46
+/* Exported types ------------------------------------------------------------*/
47
+/* Exported constants --------------------------------------------------------*/
48
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
49
+  * @{
50
+  */
51
+
52
+/**
53
+  * @}
54
+  */
55
+
56
+/* Exported macro ------------------------------------------------------------*/
57
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
58
+  * @{
59
+  */
60
+
61
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
62
+  * @{
63
+  */
64
+
65
+/**
66
+  * @brief  Write a value in CRC register
67
+  * @param  __INSTANCE__ CRC Instance
68
+  * @param  __REG__ Register to be written
69
+  * @param  __VALUE__ Value to be written in the register
70
+  * @retval None
71
+  */
72
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
73
+
74
+/**
75
+  * @brief  Read a value in CRC register
76
+  * @param  __INSTANCE__ CRC Instance
77
+  * @param  __REG__ Register to be read
78
+  * @retval Register value
79
+  */
80
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
81
+/**
82
+  * @}
83
+  */
84
+
85
+/**
86
+  * @}
87
+  */
88
+
89
+
90
+/* Exported functions --------------------------------------------------------*/
91
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
92
+  * @{
93
+  */
94
+
95
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
96
+  * @{
97
+  */
98
+
99
+/**
100
+  * @brief  Reset the CRC calculation unit.
101
+  * @note   If Programmable Initial CRC value feature
102
+  *         is available, also set the Data Register to the value stored in the
103
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
104
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
105
+  * @param  CRCx CRC Instance
106
+  * @retval None
107
+  */
108
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
109
+{
110
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
111
+}
112
+
113
+/**
114
+  * @}
115
+  */
116
+
117
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
118
+  * @{
119
+  */
120
+
121
+/**
122
+  * @brief  Write given 32-bit data to the CRC calculator
123
+  * @rmtoll DR           DR            LL_CRC_FeedData32
124
+  * @param  CRCx CRC Instance
125
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
126
+  * @retval None
127
+  */
128
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
129
+{
130
+  WRITE_REG(CRCx->DR, InData);
131
+}
132
+
133
+/**
134
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
135
+  * @rmtoll DR           DR            LL_CRC_ReadData32
136
+  * @param  CRCx CRC Instance
137
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
138
+  */
139
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
140
+{
141
+  return (uint32_t)(READ_REG(CRCx->DR));
142
+}
143
+
144
+/**
145
+  * @brief  Return data stored in the Independent Data(IDR) register.
146
+  * @note   This register can be used as a temporary storage location for one byte.
147
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
148
+  * @param  CRCx CRC Instance
149
+  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
150
+  */
151
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
152
+{
153
+  return (uint32_t)(READ_REG(CRCx->IDR));
154
+}
155
+
156
+/**
157
+  * @brief  Store data in the Independent Data(IDR) register.
158
+  * @note   This register can be used as a temporary storage location for one byte.
159
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
160
+  * @param  CRCx CRC Instance
161
+  * @param  InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
162
+  * @retval None
163
+  */
164
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
165
+{
166
+  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
167
+}
168
+/**
169
+  * @}
170
+  */
171
+
172
+#if defined(USE_FULL_LL_DRIVER)
173
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
174
+  * @{
175
+  */
176
+
177
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
178
+
179
+/**
180
+  * @}
181
+  */
182
+#endif /* USE_FULL_LL_DRIVER */
183
+
184
+/**
185
+  * @}
186
+  */
187
+
188
+/**
189
+  * @}
190
+  */
191
+
192
+#endif /* defined(CRC) */
193
+
194
+/**
195
+  * @}
196
+  */
197
+
198
+#ifdef __cplusplus
199
+}
200
+#endif
201
+
202
+#endif /* STM32F1xx_LL_CRC_H */
203
+
204
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1326
- 0
LLDrivers/inc/stm32f1xx_ll_dac.h
File diff suppressed because it is too large
View File


+ 1960
- 0
LLDrivers/inc/stm32f1xx_ll_dma.h
File diff suppressed because it is too large
View File


+ 888
- 0
LLDrivers/inc/stm32f1xx_ll_exti.h View File

@@ -0,0 +1,888 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f1xx_ll_exti.h
4
+  * @author  MCD Application Team
5
+  * @brief   Header file of EXTI LL module.
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+
20
+/* Define to prevent recursive inclusion -------------------------------------*/
21
+#ifndef STM32F1xx_LL_EXTI_H
22
+#define STM32F1xx_LL_EXTI_H
23
+
24
+#ifdef __cplusplus
25
+extern "C" {
26
+#endif
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f1xx.h"
30
+
31
+/** @addtogroup STM32F1xx_LL_Driver
32
+  * @{
33
+  */
34
+
35
+#if defined (EXTI)
36
+
37
+/** @defgroup EXTI_LL EXTI
38
+  * @{
39
+  */
40
+
41
+/* Private types -------------------------------------------------------------*/
42
+/* Private variables ---------------------------------------------------------*/
43
+/* Private constants ---------------------------------------------------------*/
44
+/* Private Macros ------------------------------------------------------------*/
45
+#if defined(USE_FULL_LL_DRIVER)
46
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
47
+  * @{
48
+  */
49
+/**
50
+  * @}
51
+  */
52
+#endif /*USE_FULL_LL_DRIVER*/
53
+/* Exported types ------------------------------------------------------------*/
54
+#if defined(USE_FULL_LL_DRIVER)
55
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
56
+  * @{
57
+  */
58
+typedef struct
59
+{
60
+
61
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
62
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
63
+
64
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
65
+                                     This parameter can be set either to ENABLE or DISABLE */
66
+
67
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
68
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
69
+
70
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
71
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
72
+} LL_EXTI_InitTypeDef;
73
+
74
+/**
75
+  * @}
76
+  */
77
+#endif /*USE_FULL_LL_DRIVER*/
78
+
79
+/* Exported constants --------------------------------------------------------*/
80
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
81
+  * @{
82
+  */
83
+
84
+/** @defgroup EXTI_LL_EC_LINE LINE
85
+  * @{
86
+  */
87
+#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
88
+#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
89
+#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
90
+#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
91
+#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
92
+#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
93
+#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
94
+#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
95
+#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
96
+#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
97
+#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
98
+#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
99
+#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
100
+#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
101
+#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
102
+#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
103
+#if defined(EXTI_IMR_IM16)
104
+#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
105
+#endif
106
+#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
107
+#if defined(EXTI_IMR_IM18)
108
+#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
109
+#endif
110
+#if defined(EXTI_IMR_IM19)
111
+#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
112
+#endif
113
+#if defined(EXTI_IMR_IM20)
114
+#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
115
+#endif
116
+#if defined(EXTI_IMR_IM21)
117
+#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
118
+#endif
119
+#if defined(EXTI_IMR_IM22)
120
+#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
121
+#endif
122
+#if defined(EXTI_IMR_IM23)
123
+#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
124
+#endif
125
+#if defined(EXTI_IMR_IM24)
126
+#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
127
+#endif
128
+#if defined(EXTI_IMR_IM25)
129
+#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
130
+#endif
131
+#if defined(EXTI_IMR_IM26)
132
+#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
133
+#endif
134
+#if defined(EXTI_IMR_IM27)
135
+#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
136
+#endif
137
+#if defined(EXTI_IMR_IM28)
138
+#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
139
+#endif
140
+#if defined(EXTI_IMR_IM29)
141
+#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
142
+#endif
143
+#if defined(EXTI_IMR_IM30)
144
+#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
145
+#endif
146
+#if defined(EXTI_IMR_IM31)
147
+#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
148
+#endif
149
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
150
+
151
+
152
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
153
+
154
+#if defined(USE_FULL_LL_DRIVER)
155
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
156
+#endif /*USE_FULL_LL_DRIVER*/
157
+
158
+/**
159
+  * @}
160
+  */
161
+#if defined(USE_FULL_LL_DRIVER)
162
+
163
+/** @defgroup EXTI_LL_EC_MODE Mode
164
+  * @{
165
+  */
166
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00) /*!< Interrupt Mode */
167
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01) /*!< Event Mode */
168
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02) /*!< Interrupt & Event Mode */
169
+/**
170
+  * @}
171
+  */
172
+
173
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
174
+  * @{
175
+  */
176
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00) /*!< No Trigger Mode */
177
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01) /*!< Trigger Rising Mode */
178
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02) /*!< Trigger Falling Mode */
179
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
180
+
181
+/**
182
+  * @}
183
+  */
184
+
185
+
186
+#endif /*USE_FULL_LL_DRIVER*/
187
+
188
+
189
+/**
190
+  * @}
191
+  */
192
+
193
+/* Exported macro ------------------------------------------------------------*/
194
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
195
+  * @{
196
+  */
197
+
198
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
199
+  * @{
200
+  */
201
+
202
+/**
203
+  * @brief  Write a value in EXTI register
204
+  * @param  __REG__ Register to be written
205
+  * @param  __VALUE__ Value to be written in the register
206
+  * @retval None
207
+  */
208
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
209
+
210
+/**
211
+  * @brief  Read a value in EXTI register
212
+  * @param  __REG__ Register to be read
213
+  * @retval Register value
214
+  */
215
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
216
+/**
217
+  * @}
218
+  */
219
+
220
+
221
+/**
222
+  * @}
223
+  */
224
+
225
+
226
+
227
+/* Exported functions --------------------------------------------------------*/
228
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
229
+ * @{
230
+ */
231
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
232
+  * @{
233
+  */
234
+
235
+/**
236
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
237
+  * @note The reset value for the direct or internal lines (see RM)
238
+  *       is set to 1 in order to enable the interrupt by default.
239
+  *       Bits are set automatically at Power on.
240
+  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
241
+  * @param  ExtiLine This parameter can be one of the following values:
242
+  *         @arg @ref LL_EXTI_LINE_0
243
+  *         @arg @ref LL_EXTI_LINE_1
244
+  *         @arg @ref LL_EXTI_LINE_2
245
+  *         @arg @ref LL_EXTI_LINE_3
246
+  *         @arg @ref LL_EXTI_LINE_4
247
+  *         @arg @ref LL_EXTI_LINE_5
248
+  *         @arg @ref LL_EXTI_LINE_6
249
+  *         @arg @ref LL_EXTI_LINE_7
250
+  *         @arg @ref LL_EXTI_LINE_8
251
+  *         @arg @ref LL_EXTI_LINE_9
252
+  *         @arg @ref LL_EXTI_LINE_10
253
+  *         @arg @ref LL_EXTI_LINE_11
254
+  *         @arg @ref LL_EXTI_LINE_12
255
+  *         @arg @ref LL_EXTI_LINE_13
256
+  *         @arg @ref LL_EXTI_LINE_14
257
+  *         @arg @ref LL_EXTI_LINE_15
258
+  *         @arg @ref LL_EXTI_LINE_16
259
+  *         @arg @ref LL_EXTI_LINE_17
260
+  *         @arg @ref LL_EXTI_LINE_18
261
+  *         @arg @ref LL_EXTI_LINE_19
262
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
263
+  * @note   Please check each device line mapping for EXTI Line availability
264
+  * @retval None
265
+  */
266
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
267
+{
268
+  SET_BIT(EXTI->IMR, ExtiLine);
269
+}
270
+
271
+/**
272
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
273
+  * @note The reset value for the direct or internal lines (see RM)
274
+  *       is set to 1 in order to enable the interrupt by default.
275
+  *       Bits are set automatically at Power on.
276
+  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
277
+  * @param  ExtiLine This parameter can be one of the following values:
278
+  *         @arg @ref LL_EXTI_LINE_0
279
+  *         @arg @ref LL_EXTI_LINE_1
280
+  *         @arg @ref LL_EXTI_LINE_2
281
+  *         @arg @ref LL_EXTI_LINE_3
282
+  *         @arg @ref LL_EXTI_LINE_4
283
+  *         @arg @ref LL_EXTI_LINE_5
284
+  *         @arg @ref LL_EXTI_LINE_6
285
+  *         @arg @ref LL_EXTI_LINE_7
286
+  *         @arg @ref LL_EXTI_LINE_8
287
+  *         @arg @ref LL_EXTI_LINE_9
288
+  *         @arg @ref LL_EXTI_LINE_10
289
+  *         @arg @ref LL_EXTI_LINE_11
290
+  *         @arg @ref LL_EXTI_LINE_12
291
+  *         @arg @ref LL_EXTI_LINE_13
292
+  *         @arg @ref LL_EXTI_LINE_14
293
+  *         @arg @ref LL_EXTI_LINE_15
294
+  *         @arg @ref LL_EXTI_LINE_16
295
+  *         @arg @ref LL_EXTI_LINE_17
296
+  *         @arg @ref LL_EXTI_LINE_18
297
+  *         @arg @ref LL_EXTI_LINE_19
298
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
299
+  * @note   Please check each device line mapping for EXTI Line availability
300
+  * @retval None
301
+  */
302
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
303
+{
304
+  CLEAR_BIT(EXTI->IMR, ExtiLine);
305
+}
306
+
307
+
308
+/**
309
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
310
+  * @note The reset value for the direct or internal lines (see RM)
311
+  *       is set to 1 in order to enable the interrupt by default.
312
+  *       Bits are set automatically at Power on.
313
+  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
314
+  * @param  ExtiLine This parameter can be one of the following values:
315
+  *         @arg @ref LL_EXTI_LINE_0
316
+  *         @arg @ref LL_EXTI_LINE_1
317
+  *         @arg @ref LL_EXTI_LINE_2
318
+  *         @arg @ref LL_EXTI_LINE_3
319
+  *         @arg @ref LL_EXTI_LINE_4
320
+  *         @arg @ref LL_EXTI_LINE_5
321
+  *         @arg @ref LL_EXTI_LINE_6
322
+  *         @arg @ref LL_EXTI_LINE_7
323
+  *         @arg @ref LL_EXTI_LINE_8
324
+  *         @arg @ref LL_EXTI_LINE_9
325
+  *         @arg @ref LL_EXTI_LINE_10
326
+  *         @arg @ref LL_EXTI_LINE_11
327
+  *         @arg @ref LL_EXTI_LINE_12
328
+  *         @arg @ref LL_EXTI_LINE_13
329
+  *         @arg @ref LL_EXTI_LINE_14
330
+  *         @arg @ref LL_EXTI_LINE_15
331
+  *         @arg @ref LL_EXTI_LINE_16
332
+  *         @arg @ref LL_EXTI_LINE_17
333
+  *         @arg @ref LL_EXTI_LINE_18
334
+  *         @arg @ref LL_EXTI_LINE_19
335
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
336
+  * @note   Please check each device line mapping for EXTI Line availability
337
+  * @retval State of bit (1 or 0).
338
+  */
339
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
340
+{
341
+  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
342
+}
343
+
344
+
345
+/**
346
+  * @}
347
+  */
348
+
349
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
350
+  * @{
351
+  */
352
+
353
+/**
354
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
355
+  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
356
+  * @param  ExtiLine This parameter can be one of the following values:
357
+  *         @arg @ref LL_EXTI_LINE_0
358
+  *         @arg @ref LL_EXTI_LINE_1
359
+  *         @arg @ref LL_EXTI_LINE_2
360
+  *         @arg @ref LL_EXTI_LINE_3
361
+  *         @arg @ref LL_EXTI_LINE_4
362
+  *         @arg @ref LL_EXTI_LINE_5
363
+  *         @arg @ref LL_EXTI_LINE_6
364
+  *         @arg @ref LL_EXTI_LINE_7
365
+  *         @arg @ref LL_EXTI_LINE_8
366
+  *         @arg @ref LL_EXTI_LINE_9
367
+  *         @arg @ref LL_EXTI_LINE_10
368
+  *         @arg @ref LL_EXTI_LINE_11
369
+  *         @arg @ref LL_EXTI_LINE_12
370
+  *         @arg @ref LL_EXTI_LINE_13
371
+  *         @arg @ref LL_EXTI_LINE_14
372
+  *         @arg @ref LL_EXTI_LINE_15
373
+  *         @arg @ref LL_EXTI_LINE_16
374
+  *         @arg @ref LL_EXTI_LINE_17
375
+  *         @arg @ref LL_EXTI_LINE_18
376
+  *         @arg @ref LL_EXTI_LINE_19
377
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
378
+  * @note   Please check each device line mapping for EXTI Line availability
379
+  * @retval None
380
+  */
381
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
382
+{
383
+  SET_BIT(EXTI->EMR, ExtiLine);
384
+
385
+}
386
+
387
+
388
+/**
389
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
390
+  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
391
+  * @param  ExtiLine This parameter can be one of the following values:
392
+  *         @arg @ref LL_EXTI_LINE_0
393
+  *         @arg @ref LL_EXTI_LINE_1
394
+  *         @arg @ref LL_EXTI_LINE_2
395
+  *         @arg @ref LL_EXTI_LINE_3
396
+  *         @arg @ref LL_EXTI_LINE_4
397
+  *         @arg @ref LL_EXTI_LINE_5
398
+  *         @arg @ref LL_EXTI_LINE_6
399
+  *         @arg @ref LL_EXTI_LINE_7
400
+  *         @arg @ref LL_EXTI_LINE_8
401
+  *         @arg @ref LL_EXTI_LINE_9
402
+  *         @arg @ref LL_EXTI_LINE_10
403
+  *         @arg @ref LL_EXTI_LINE_11
404
+  *         @arg @ref LL_EXTI_LINE_12
405
+  *         @arg @ref LL_EXTI_LINE_13
406
+  *         @arg @ref LL_EXTI_LINE_14
407
+  *         @arg @ref LL_EXTI_LINE_15
408
+  *         @arg @ref LL_EXTI_LINE_16
409
+  *         @arg @ref LL_EXTI_LINE_17
410
+  *         @arg @ref LL_EXTI_LINE_18
411
+  *         @arg @ref LL_EXTI_LINE_19
412
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
413
+  * @note   Please check each device line mapping for EXTI Line availability
414
+  * @retval None
415
+  */
416
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
417
+{
418
+  CLEAR_BIT(EXTI->EMR, ExtiLine);
419
+}
420
+
421
+
422
+/**
423
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
424
+  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
425
+  * @param  ExtiLine This parameter can be one of the following values:
426
+  *         @arg @ref LL_EXTI_LINE_0
427
+  *         @arg @ref LL_EXTI_LINE_1
428
+  *         @arg @ref LL_EXTI_LINE_2
429
+  *         @arg @ref LL_EXTI_LINE_3
430
+  *         @arg @ref LL_EXTI_LINE_4
431
+  *         @arg @ref LL_EXTI_LINE_5
432
+  *         @arg @ref LL_EXTI_LINE_6
433
+  *         @arg @ref LL_EXTI_LINE_7
434
+  *         @arg @ref LL_EXTI_LINE_8
435
+  *         @arg @ref LL_EXTI_LINE_9
436
+  *         @arg @ref LL_EXTI_LINE_10
437
+  *         @arg @ref LL_EXTI_LINE_11
438
+  *         @arg @ref LL_EXTI_LINE_12
439
+  *         @arg @ref LL_EXTI_LINE_13
440
+  *         @arg @ref LL_EXTI_LINE_14
441
+  *         @arg @ref LL_EXTI_LINE_15
442
+  *         @arg @ref LL_EXTI_LINE_16
443
+  *         @arg @ref LL_EXTI_LINE_17
444
+  *         @arg @ref LL_EXTI_LINE_18
445
+  *         @arg @ref LL_EXTI_LINE_19
446
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
447
+  * @note   Please check each device line mapping for EXTI Line availability
448
+  * @retval State of bit (1 or 0).
449
+  */
450
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
451
+{
452
+  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
453
+
454
+}
455
+
456
+
457
+/**
458
+  * @}
459
+  */
460
+
461
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
462
+  * @{
463
+  */
464
+
465
+/**
466
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
467
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
468
+  *       generated on these lines. If a rising edge on a configurable interrupt
469
+  *       line occurs during a write operation in the EXTI_RTSR register, the
470
+  *       pending bit is not set.
471
+  *       Rising and falling edge triggers can be set for
472
+  *       the same interrupt line. In this case, both generate a trigger
473
+  *       condition.
474
+  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
475
+  * @param  ExtiLine This parameter can be a combination of the following values:
476
+  *         @arg @ref LL_EXTI_LINE_0
477
+  *         @arg @ref LL_EXTI_LINE_1
478
+  *         @arg @ref LL_EXTI_LINE_2
479
+  *         @arg @ref LL_EXTI_LINE_3
480
+  *         @arg @ref LL_EXTI_LINE_4
481
+  *         @arg @ref LL_EXTI_LINE_5
482
+  *         @arg @ref LL_EXTI_LINE_6
483
+  *         @arg @ref LL_EXTI_LINE_7
484
+  *         @arg @ref LL_EXTI_LINE_8
485
+  *         @arg @ref LL_EXTI_LINE_9
486
+  *         @arg @ref LL_EXTI_LINE_10
487
+  *         @arg @ref LL_EXTI_LINE_11
488
+  *         @arg @ref LL_EXTI_LINE_12
489
+  *         @arg @ref LL_EXTI_LINE_13
490
+  *         @arg @ref LL_EXTI_LINE_14
491
+  *         @arg @ref LL_EXTI_LINE_15
492
+  *         @arg @ref LL_EXTI_LINE_16
493
+  *         @arg @ref LL_EXTI_LINE_18
494
+  *         @arg @ref LL_EXTI_LINE_19
495
+  * @note   Please check each device line mapping for EXTI Line availability
496
+  * @retval None
497
+  */
498
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
499
+{
500
+  SET_BIT(EXTI->RTSR, ExtiLine);
501
+
502
+}
503
+
504
+
505
+/**
506
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
507
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
508
+  *       generated on these lines. If a rising edge on a configurable interrupt
509
+  *       line occurs during a write operation in the EXTI_RTSR register, the
510
+  *       pending bit is not set.
511
+  *       Rising and falling edge triggers can be set for
512
+  *       the same interrupt line. In this case, both generate a trigger
513
+  *       condition.
514
+  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
515
+  * @param  ExtiLine This parameter can be a combination of the following values:
516
+  *         @arg @ref LL_EXTI_LINE_0
517
+  *         @arg @ref LL_EXTI_LINE_1
518
+  *         @arg @ref LL_EXTI_LINE_2
519
+  *         @arg @ref LL_EXTI_LINE_3
520
+  *         @arg @ref LL_EXTI_LINE_4
521
+  *         @arg @ref LL_EXTI_LINE_5
522
+  *         @arg @ref LL_EXTI_LINE_6
523
+  *         @arg @ref LL_EXTI_LINE_7
524
+  *         @arg @ref LL_EXTI_LINE_8
525
+  *         @arg @ref LL_EXTI_LINE_9
526
+  *         @arg @ref LL_EXTI_LINE_10
527
+  *         @arg @ref LL_EXTI_LINE_11
528
+  *         @arg @ref LL_EXTI_LINE_12
529
+  *         @arg @ref LL_EXTI_LINE_13
530
+  *         @arg @ref LL_EXTI_LINE_14
531
+  *         @arg @ref LL_EXTI_LINE_15
532
+  *         @arg @ref LL_EXTI_LINE_16
533
+  *         @arg @ref LL_EXTI_LINE_18
534
+  *         @arg @ref LL_EXTI_LINE_19
535
+  * @note   Please check each device line mapping for EXTI Line availability
536
+  * @retval None
537
+  */
538
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
539
+{
540
+  CLEAR_BIT(EXTI->RTSR, ExtiLine);
541
+
542
+}
543
+
544
+
545
+/**
546
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
547
+  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
548
+  * @param  ExtiLine This parameter can be a combination of the following values:
549
+  *         @arg @ref LL_EXTI_LINE_0
550
+  *         @arg @ref LL_EXTI_LINE_1
551
+  *         @arg @ref LL_EXTI_LINE_2
552
+  *         @arg @ref LL_EXTI_LINE_3
553
+  *         @arg @ref LL_EXTI_LINE_4
554
+  *         @arg @ref LL_EXTI_LINE_5
555
+  *         @arg @ref LL_EXTI_LINE_6
556
+  *         @arg @ref LL_EXTI_LINE_7
557
+  *         @arg @ref LL_EXTI_LINE_8
558
+  *         @arg @ref LL_EXTI_LINE_9
559
+  *         @arg @ref LL_EXTI_LINE_10
560
+  *         @arg @ref LL_EXTI_LINE_11
561
+  *         @arg @ref LL_EXTI_LINE_12
562
+  *         @arg @ref LL_EXTI_LINE_13
563
+  *         @arg @ref LL_EXTI_LINE_14
564
+  *         @arg @ref LL_EXTI_LINE_15
565
+  *         @arg @ref LL_EXTI_LINE_16
566
+  *         @arg @ref LL_EXTI_LINE_18
567
+  *         @arg @ref LL_EXTI_LINE_19
568
+  * @note   Please check each device line mapping for EXTI Line availability
569
+  * @retval State of bit (1 or 0).
570
+  */
571
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
572
+{
573
+  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
574
+}
575
+
576
+
577
+/**
578
+  * @}
579
+  */
580
+
581
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
582
+  * @{
583
+  */
584
+
585
+/**
586
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
587
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
588
+  *       generated on these lines. If a falling edge on a configurable interrupt
589
+  *       line occurs during a write operation in the EXTI_FTSR register, the
590
+  *       pending bit is not set.
591
+  *       Rising and falling edge triggers can be set for
592
+  *       the same interrupt line. In this case, both generate a trigger
593
+  *       condition.
594
+  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
595
+  * @param  ExtiLine This parameter can be a combination of the following values:
596
+  *         @arg @ref LL_EXTI_LINE_0
597
+  *         @arg @ref LL_EXTI_LINE_1
598
+  *         @arg @ref LL_EXTI_LINE_2
599
+  *         @arg @ref LL_EXTI_LINE_3
600
+  *         @arg @ref LL_EXTI_LINE_4
601
+  *         @arg @ref LL_EXTI_LINE_5
602
+  *         @arg @ref LL_EXTI_LINE_6
603
+  *         @arg @ref LL_EXTI_LINE_7
604
+  *         @arg @ref LL_EXTI_LINE_8
605
+  *         @arg @ref LL_EXTI_LINE_9
606
+  *         @arg @ref LL_EXTI_LINE_10
607
+  *         @arg @ref LL_EXTI_LINE_11
608
+  *         @arg @ref LL_EXTI_LINE_12
609
+  *         @arg @ref LL_EXTI_LINE_13
610
+  *         @arg @ref LL_EXTI_LINE_14
611
+  *         @arg @ref LL_EXTI_LINE_15
612
+  *         @arg @ref LL_EXTI_LINE_16
613
+  *         @arg @ref LL_EXTI_LINE_18
614
+  *         @arg @ref LL_EXTI_LINE_19
615
+  * @note   Please check each device line mapping for EXTI Line availability
616
+  * @retval None
617
+  */
618
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
619
+{
620
+  SET_BIT(EXTI->FTSR, ExtiLine);
621
+}
622
+
623
+
624
+/**
625
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
626
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
627
+  *       generated on these lines. If a Falling edge on a configurable interrupt
628
+  *       line occurs during a write operation in the EXTI_FTSR register, the
629
+  *       pending bit is not set.
630
+  *       Rising and falling edge triggers can be set for the same interrupt line.
631
+  *       In this case, both generate a trigger condition.
632
+  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
633
+  * @param  ExtiLine This parameter can be a combination of the following values:
634
+  *         @arg @ref LL_EXTI_LINE_0
635
+  *         @arg @ref LL_EXTI_LINE_1
636
+  *         @arg @ref LL_EXTI_LINE_2
637
+  *         @arg @ref LL_EXTI_LINE_3
638
+  *         @arg @ref LL_EXTI_LINE_4
639
+  *         @arg @ref LL_EXTI_LINE_5
640
+  *         @arg @ref LL_EXTI_LINE_6
641
+  *         @arg @ref LL_EXTI_LINE_7
642
+  *         @arg @ref LL_EXTI_LINE_8
643
+  *         @arg @ref LL_EXTI_LINE_9
644
+  *         @arg @ref LL_EXTI_LINE_10
645
+  *         @arg @ref LL_EXTI_LINE_11
646
+  *         @arg @ref LL_EXTI_LINE_12
647
+  *         @arg @ref LL_EXTI_LINE_13
648
+  *         @arg @ref LL_EXTI_LINE_14
649
+  *         @arg @ref LL_EXTI_LINE_15
650
+  *         @arg @ref LL_EXTI_LINE_16
651
+  *         @arg @ref LL_EXTI_LINE_18
652
+  *         @arg @ref LL_EXTI_LINE_19
653
+  * @note   Please check each device line mapping for EXTI Line availability
654
+  * @retval None
655
+  */
656
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
657
+{
658
+  CLEAR_BIT(EXTI->FTSR, ExtiLine);
659
+}
660
+
661
+
662
+/**
663
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
664
+  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
665
+  * @param  ExtiLine This parameter can be a combination of the following values:
666
+  *         @arg @ref LL_EXTI_LINE_0
667
+  *         @arg @ref LL_EXTI_LINE_1
668
+  *         @arg @ref LL_EXTI_LINE_2
669
+  *         @arg @ref LL_EXTI_LINE_3
670
+  *         @arg @ref LL_EXTI_LINE_4
671
+  *         @arg @ref LL_EXTI_LINE_5
672
+  *         @arg @ref LL_EXTI_LINE_6
673
+  *         @arg @ref LL_EXTI_LINE_7
674
+  *         @arg @ref LL_EXTI_LINE_8
675
+  *         @arg @ref LL_EXTI_LINE_9
676
+  *         @arg @ref LL_EXTI_LINE_10
677
+  *         @arg @ref LL_EXTI_LINE_11
678
+  *         @arg @ref LL_EXTI_LINE_12
679
+  *         @arg @ref LL_EXTI_LINE_13
680
+  *         @arg @ref LL_EXTI_LINE_14
681
+  *         @arg @ref LL_EXTI_LINE_15
682
+  *         @arg @ref LL_EXTI_LINE_16
683
+  *         @arg @ref LL_EXTI_LINE_18
684
+  *         @arg @ref LL_EXTI_LINE_19
685
+  * @note   Please check each device line mapping for EXTI Line availability
686
+  * @retval State of bit (1 or 0).
687
+  */
688
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
689
+{
690
+  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
691
+}
692
+
693
+
694
+/**
695
+  * @}
696
+  */
697
+
698
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
699
+  * @{
700
+  */
701
+
702
+/**
703
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
704
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
705
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
706
+  *       resulting in an interrupt request generation.
707
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
708
+  *       register (by writing a 1 into the bit)
709
+  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
710
+  * @param  ExtiLine This parameter can be a combination of the following values:
711
+  *         @arg @ref LL_EXTI_LINE_0
712
+  *         @arg @ref LL_EXTI_LINE_1
713
+  *         @arg @ref LL_EXTI_LINE_2
714
+  *         @arg @ref LL_EXTI_LINE_3
715
+  *         @arg @ref LL_EXTI_LINE_4
716
+  *         @arg @ref LL_EXTI_LINE_5
717
+  *         @arg @ref LL_EXTI_LINE_6
718
+  *         @arg @ref LL_EXTI_LINE_7
719
+  *         @arg @ref LL_EXTI_LINE_8
720
+  *         @arg @ref LL_EXTI_LINE_9
721
+  *         @arg @ref LL_EXTI_LINE_10
722
+  *         @arg @ref LL_EXTI_LINE_11
723
+  *         @arg @ref LL_EXTI_LINE_12
724
+  *         @arg @ref LL_EXTI_LINE_13
725
+  *         @arg @ref LL_EXTI_LINE_14
726
+  *         @arg @ref LL_EXTI_LINE_15
727
+  *         @arg @ref LL_EXTI_LINE_16
728
+  *         @arg @ref LL_EXTI_LINE_18
729
+  *         @arg @ref LL_EXTI_LINE_19
730
+  * @note   Please check each device line mapping for EXTI Line availability
731
+  * @retval None
732
+  */
733
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
734
+{
735
+  SET_BIT(EXTI->SWIER, ExtiLine);
736
+}
737
+
738
+
739
+/**
740
+  * @}
741
+  */
742
+
743
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
744
+  * @{
745
+  */
746
+
747
+/**
748
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
749
+  * @note This bit is set when the selected edge event arrives on the interrupt
750
+  *       line. This bit is cleared by writing a 1 to the bit.
751
+  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
752
+  * @param  ExtiLine This parameter can be a combination of the following values:
753
+  *         @arg @ref LL_EXTI_LINE_0
754
+  *         @arg @ref LL_EXTI_LINE_1
755
+  *         @arg @ref LL_EXTI_LINE_2
756
+  *         @arg @ref LL_EXTI_LINE_3
757
+  *         @arg @ref LL_EXTI_LINE_4
758
+  *         @arg @ref LL_EXTI_LINE_5
759
+  *         @arg @ref LL_EXTI_LINE_6
760
+  *         @arg @ref LL_EXTI_LINE_7
761
+  *         @arg @ref LL_EXTI_LINE_8
762
+  *         @arg @ref LL_EXTI_LINE_9
763
+  *         @arg @ref LL_EXTI_LINE_10
764
+  *         @arg @ref LL_EXTI_LINE_11
765
+  *         @arg @ref LL_EXTI_LINE_12
766
+  *         @arg @ref LL_EXTI_LINE_13
767
+  *         @arg @ref LL_EXTI_LINE_14
768
+  *         @arg @ref LL_EXTI_LINE_15
769
+  *         @arg @ref LL_EXTI_LINE_16
770
+  *         @arg @ref LL_EXTI_LINE_18
771
+  *         @arg @ref LL_EXTI_LINE_19
772
+  * @note   Please check each device line mapping for EXTI Line availability
773
+  * @retval State of bit (1 or 0).
774
+  */
775
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
776
+{
777
+  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
778
+}
779
+
780
+
781
+/**
782
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
783
+  * @note This bit is set when the selected edge event arrives on the interrupt
784
+  *       line. This bit is cleared by writing a 1 to the bit.
785
+  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
786
+  * @param  ExtiLine This parameter can be a combination of the following values:
787
+  *         @arg @ref LL_EXTI_LINE_0
788
+  *         @arg @ref LL_EXTI_LINE_1
789
+  *         @arg @ref LL_EXTI_LINE_2
790
+  *         @arg @ref LL_EXTI_LINE_3
791
+  *         @arg @ref LL_EXTI_LINE_4
792
+  *         @arg @ref LL_EXTI_LINE_5
793
+  *         @arg @ref LL_EXTI_LINE_6
794
+  *         @arg @ref LL_EXTI_LINE_7
795
+  *         @arg @ref LL_EXTI_LINE_8
796
+  *         @arg @ref LL_EXTI_LINE_9
797
+  *         @arg @ref LL_EXTI_LINE_10
798
+  *         @arg @ref LL_EXTI_LINE_11
799
+  *         @arg @ref LL_EXTI_LINE_12
800
+  *         @arg @ref LL_EXTI_LINE_13
801
+  *         @arg @ref LL_EXTI_LINE_14
802
+  *         @arg @ref LL_EXTI_LINE_15
803
+  *         @arg @ref LL_EXTI_LINE_16
804
+  *         @arg @ref LL_EXTI_LINE_18
805
+  *         @arg @ref LL_EXTI_LINE_19
806
+  * @note   Please check each device line mapping for EXTI Line availability
807
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
808
+  */
809
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
810
+{
811
+  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
812
+}
813
+
814
+
815
+/**
816
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
817
+  * @note This bit is set when the selected edge event arrives on the interrupt
818
+  *       line. This bit is cleared by writing a 1 to the bit.
819
+  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
820
+  * @param  ExtiLine This parameter can be a combination of the following values:
821
+  *         @arg @ref LL_EXTI_LINE_0
822
+  *         @arg @ref LL_EXTI_LINE_1
823
+  *         @arg @ref LL_EXTI_LINE_2
824
+  *         @arg @ref LL_EXTI_LINE_3
825
+  *         @arg @ref LL_EXTI_LINE_4
826
+  *         @arg @ref LL_EXTI_LINE_5
827
+  *         @arg @ref LL_EXTI_LINE_6
828
+  *         @arg @ref LL_EXTI_LINE_7
829
+  *         @arg @ref LL_EXTI_LINE_8
830
+  *         @arg @ref LL_EXTI_LINE_9
831
+  *         @arg @ref LL_EXTI_LINE_10
832
+  *         @arg @ref LL_EXTI_LINE_11
833
+  *         @arg @ref LL_EXTI_LINE_12
834
+  *         @arg @ref LL_EXTI_LINE_13
835
+  *         @arg @ref LL_EXTI_LINE_14
836
+  *         @arg @ref LL_EXTI_LINE_15
837
+  *         @arg @ref LL_EXTI_LINE_16
838
+  *         @arg @ref LL_EXTI_LINE_18
839
+  *         @arg @ref LL_EXTI_LINE_19
840
+  * @note   Please check each device line mapping for EXTI Line availability
841
+  * @retval None
842
+  */
843
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
844
+{
845
+  WRITE_REG(EXTI->PR, ExtiLine);
846
+}
847
+
848
+
849
+/**
850
+  * @}
851
+  */
852
+
853
+#if defined(USE_FULL_LL_DRIVER)
854
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
855
+  * @{
856
+  */
857
+
858
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
859
+uint32_t LL_EXTI_DeInit(void);
860
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
861
+
862
+
863
+/**
864
+  * @}
865
+  */
866
+#endif /* USE_FULL_LL_DRIVER */
867
+
868
+/**
869
+  * @}
870
+  */
871
+
872
+/**
873
+  * @}
874
+  */
875
+
876
+#endif /* EXTI */
877
+
878
+/**
879
+  * @}
880
+  */
881
+
882
+#ifdef __cplusplus
883
+}
884
+#endif
885
+
886
+#endif /* STM32F1xx_LL_EXTI_H */
887
+
888
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 951
- 0
LLDrivers/inc/stm32f1xx_ll_fsmc.h View File

@@ -0,0 +1,951 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f1xx_ll_fsmc.h
4
+  * @author  MCD Application Team
5
+  * @brief   Header file of FSMC HAL module.
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                       opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+
20
+/* Define to prevent recursive inclusion -------------------------------------*/
21
+#ifndef STM32F1xx_LL_FSMC_H
22
+#define STM32F1xx_LL_FSMC_H
23
+
24
+#ifdef __cplusplus
25
+extern "C" {
26
+#endif
27
+
28
+/* Includes ------------------------------------------------------------------*/
29
+#include "stm32f1xx_hal_def.h"
30
+
31
+/** @addtogroup STM32F1xx_HAL_Driver
32
+  * @{
33
+  */
34
+
35
+/** @addtogroup FSMC_LL
36
+  * @{
37
+  */
38
+
39
+/** @addtogroup FSMC_LL_Private_Macros
40
+  * @{
41
+  */
42
+#if defined FSMC_BANK1
43
+
44
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
45
+                                       ((__BANK__) == FSMC_NORSRAM_BANK2) || \
46
+                                       ((__BANK__) == FSMC_NORSRAM_BANK3) || \
47
+                                       ((__BANK__) == FSMC_NORSRAM_BANK4))
48
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
49
+                             ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
50
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
51
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
52
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
53
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
54
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
55
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
56
+#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
57
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
58
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
59
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
60
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_1024))
61
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
62
+                                      ((__MODE__) == FSMC_ACCESS_MODE_B) || \
63
+                                      ((__MODE__) == FSMC_ACCESS_MODE_C) || \
64
+                                      ((__MODE__) == FSMC_ACCESS_MODE_D))
65
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
66
+                                     ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
67
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
68
+                                            ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
69
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
70
+                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE))     
71
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
72
+                                               ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
73
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
74
+                                               ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
75
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
76
+                                         ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
77
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
78
+                                        ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
79
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
80
+                                    ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
81
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
82
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
83
+                                       ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
84
+#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
85
+                                            ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
86
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
87
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
88
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
89
+#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
90
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
91
+#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
92
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
93
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
94
+
95
+#endif /* FSMC_BANK1 */
96
+#if defined(FSMC_BANK3)
97
+
98
+#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
99
+#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
100
+                                          ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
101
+#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
102
+                                             ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
103
+#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
104
+                                     ((__STATE__) == FSMC_NAND_ECC_ENABLE))
105
+
106
+#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
107
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
108
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
109
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
110
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
111
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
112
+#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
113
+#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
114
+#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
115
+#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
116
+#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
117
+#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
118
+#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
119
+
120
+#endif /* FSMC_BANK3 */
121
+#if defined(FSMC_BANK4)
122
+#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
123
+
124
+#endif /* FSMC_BANK4 */
125
+
126
+/**
127
+  * @}
128
+  */
129
+
130
+/* Exported typedef ----------------------------------------------------------*/
131
+
132
+/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
133
+  * @{
134
+  */
135
+
136
+#if defined FSMC_BANK1
137
+#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
138
+#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
139
+#endif /* FSMC_BANK1 */
140
+#if defined(FSMC_BANK3)
141
+#define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
142
+#endif /* FSMC_BANK3 */
143
+#if defined(FSMC_BANK4)
144
+#define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
145
+#endif /* FSMC_BANK4 */
146
+
147
+#if defined FSMC_BANK1
148
+#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
149
+#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
150
+#endif /* FSMC_BANK1 */
151
+#if defined(FSMC_BANK3)
152
+#define FSMC_NAND_DEVICE                FSMC_Bank2_3
153
+#endif /* FSMC_BANK3 */
154
+#if defined(FSMC_BANK4)
155
+#define FSMC_PCCARD_DEVICE              FSMC_Bank4
156
+#endif /* FSMC_BANK4 */
157
+
158
+#if defined FSMC_BANK1
159
+/**
160
+  * @brief  FSMC NORSRAM Configuration Structure definition
161
+  */
162
+typedef struct
163
+{
164
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
165
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
166
+
167
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
168
+                                              multiplexed on the data bus or not.
169
+                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
170
+
171
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
172
+                                              the corresponding memory device.
173
+                                              This parameter can be a value of @ref FSMC_Memory_Type                      */
174
+
175
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
176
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
177
+
178
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
179
+                                              valid only with synchronous burst Flash memories.
180
+                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
181
+
182
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
183
+                                              the Flash memory in burst mode.
184
+                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
185
+
186
+  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
187
+                                              memory, valid only when accessing Flash memories in burst mode.
188
+                                              This parameter can be a value of @ref FSMC_Wrap_Mode                        */
189
+
190
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
191
+                                              clock cycle before the wait state or during the wait state,
192
+                                              valid only when accessing memories in burst mode.
193
+                                              This parameter can be a value of @ref FSMC_Wait_Timing                      */
194
+
195
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
196
+                                              This parameter can be a value of @ref FSMC_Write_Operation                  */
197
+
198
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
199
+                                              signal, valid for Flash memory access in burst mode.
200
+                                              This parameter can be a value of @ref FSMC_Wait_Signal                      */
201
+
202
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
203
+                                              This parameter can be a value of @ref FSMC_Extended_Mode                    */
204
+
205
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
206
+                                              valid only with asynchronous Flash memories.
207
+                                              This parameter can be a value of @ref FSMC_AsynchronousWait                 */
208
+
209
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
210
+                                              This parameter can be a value of @ref FSMC_Write_Burst                      */
211
+
212
+
213
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
214
+                                              This parameter can be a value of @ref FSMC_Page_Size                        */
215
+}FSMC_NORSRAM_InitTypeDef;
216
+
217
+/**
218
+  * @brief  FSMC NORSRAM Timing parameters structure definition
219
+  */
220
+typedef struct
221
+{
222
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
223
+                                              the duration of the address setup time.
224
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
225
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
226
+
227
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
228
+                                              the duration of the address hold time.
229
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
230
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
231
+
232
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
233
+                                              the duration of the data setup time.
234
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
235
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
236
+                                              NOR Flash memories.                                                        */
237
+
238
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
239
+                                              the duration of the bus turnaround.
240
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
241
+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
242
+
243
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
244
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
245
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
246
+                                              accesses.                                                                  */
247
+
248
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
249
+                                              to the memory before getting the first data.
250
+                                              The parameter value depends on the memory type as shown below:
251
+                                              - It must be set to 0 in case of a CRAM
252
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
253
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
254
+                                                with synchronous burst mode enable                                       */
255
+
256
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
257
+                                              This parameter can be a value of @ref FSMC_Access_Mode                      */
258
+}FSMC_NORSRAM_TimingTypeDef;
259
+#endif /* FSMC_BANK1 */
260
+
261
+#if defined(FSMC_BANK3)
262
+/**
263
+  * @brief  FSMC NAND Configuration Structure definition
264
+  */
265
+typedef struct
266
+{
267
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
268
+                                        This parameter can be a value of @ref FSMC_NAND_Bank                    */
269
+
270
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
271
+                                        This parameter can be any value of @ref FSMC_Wait_feature               */
272
+
273
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
274
+                                        This parameter can be any value of @ref FSMC_NAND_Data_Width            */
275
+
276
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
277
+                                        This parameter can be any value of @ref FSMC_ECC                        */
278
+
279
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
280
+                                        This parameter can be any value of @ref FSMC_ECC_Page_Size              */
281
+
282
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
283
+                                        delay between CLE low and RE low.
284
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
285
+
286
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
287
+                                        delay between ALE low and RE low.
288
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
289
+}FSMC_NAND_InitTypeDef;
290
+#endif
291
+
292
+#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
293
+/**
294
+  * @brief  FSMC NAND Timing parameters structure definition
295
+  */
296
+typedef struct
297
+{
298
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
299
+                                      the command assertion for NAND-Flash read or write access
300
+                                      to common/Attribute or I/O memory space (depending on
301
+                                      the memory space timing to be configured).
302
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
303
+
304
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
305
+                                      command for NAND-Flash read or write access to
306
+                                      common/Attribute or I/O memory space (depending on the
307
+                                      memory space timing to be configured).
308
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
309
+
310
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
311
+                                      (and data for write access) after the command de-assertion
312
+                                      for NAND-Flash read or write access to common/Attribute
313
+                                      or I/O memory space (depending on the memory space timing
314
+                                      to be configured).
315
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
316
+
317
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
318
+                                      data bus is kept in HiZ after the start of a NAND-Flash
319
+                                      write access to common/Attribute or I/O memory space (depending
320
+                                      on the memory space timing to be configured).
321
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
322
+}FSMC_NAND_PCC_TimingTypeDef;
323
+#endif /* FSMC_BANK3 */
324
+
325
+#if defined(FSMC_BANK4)
326
+/** 
327
+  * @brief FSMC PCCARD Configuration Structure definition
328
+  */ 
329
+typedef struct
330
+{
331
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
332
+                                        This parameter can be any value of @ref FSMC_Wait_feature      */
333
+
334
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
335
+                                        delay between CLE low and RE low.
336
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
337
+
338
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
339
+                                        delay between ALE low and RE low.
340
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
341
+}FSMC_PCCARD_InitTypeDef;
342
+#endif
343
+
344
+/**
345
+  * @}
346
+  */
347
+
348
+/* Exported constants --------------------------------------------------------*/
349
+/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
350
+  * @{
351
+  */
352
+#if defined FSMC_BANK1
353
+
354
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
355
+  * @{
356
+  */
357
+
358
+/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
359
+  * @{
360
+  */
361
+#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000U)
362
+#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002U)
363
+#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004U)
364
+#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006U)
365
+/**
366
+  * @}
367
+  */
368
+
369
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
370
+  * @{
371
+  */
372
+#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000U)
373
+#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002U)
374
+/**
375
+  * @}
376
+  */