diff --git a/Article_Scientifique/main.tex b/Article_Scientifique/main.tex index c82c15d..a23795a 100644 --- a/Article_Scientifique/main.tex +++ b/Article_Scientifique/main.tex @@ -290,73 +290,83 @@ challenging. \subsection{Pin Compatibility Verification: L476 vs F405} -Before modifying the PCB, a thorough pin compatibility check was -performed between the STM32L476 and the STM32F405 -(original Cheap FOCer-2 design). The following aspects were examined: +Before starting the PCB modifications, a pin compatibility study was carried out between the STM32L476 +used on the Rocacher tile and the STM32F405 originally used in the Cheap FOCer-2 design. The objective +was to verify that the main functions required by the VESC firmware could still be used after replacing +the original microcontroller. + +The verification mainly focused on: \begin{itemize} - \item Physical pinout in LQFP64 package. - \item Alternate functions for PWM timers. - \item USB DP/DM pins (PA11/PA12). - \item Analog inputs for current sensing. - \item UART for BLE communication. + \item Physical pinout compatibility in the LQFP64 package, + \item PWM timer for Alternate functions, + \item USB DP/DM pins (PA11/PA12), + \item Analog inputs for current sensing, + \item UART communication for BLE integration. \end{itemize} -Three pin conflicts were identified and resolved as follows. +During this analysis, three main pin conflicts were identified. -First, the SPI\_MISO function on PA6 for the STM32F405 conflicts with a -DAC output on the same pin for the STM32L476 tile. Since this pin is -used for current sensing via SPI in the original Cheap FOCer-2 design, -the SPI communication was remapped to PA5 on the L476, which provides a -compatible alternate function. +The first conflict concerned the SPI\_MISO signal on pin PA6. In the original STM32F405 design, this pin is +used for SPI communication related to current sensing. On the STM32L476 tile, the same pin is associated with +a DAC output, creating a functional conflict. To solve this issue, the SPI communication line was remapped +to PA5 on the L476, which offers a compatible alternate function. -Second, the gate driver enable signal (EN\_GATE) was originally assigned -to PB5 on the F405. This pin is not accessible on the L476 -tile. The signal was therefore moved to PC5, which is available and -can be configured as a standard GPIO output. +The second issue concerned the EN\_GATE signal. In the original design, this signal was connected to PB5 on +the STM32F405. However, this pin is not accessible on the L476 tile. The signal was therefore moved to PC5, +configured as a standard GPIO output. -Third, Hall sensor C was originally connected to PC8 (TIM8) on the F405. -This pin is not available on the L476 tile. The Hall sensor input was -therefore reassigned to PB3, configured as TIM2\_CH2, which provides -the necessary input capture functionality for Hall signal decoding. +Finally, Hall sensor C was originally connected to PC8 (TIM8) on the STM32F405. Since this pin is not available +on the tile connector, the Hall sensor input was reassigned to PB3 using the TIM2\_CH2 alternate function, +which preserves the input capture capability required for Hall sensor decoding. -All other critical functions (PWM timers, complementary PWM, enable -signals, encoder inputs, UART, USB, and CAN) remain fully compatible -between the two microcontrollers. The ADC channel differences between -the F405 (ADC123/ADC12) and the L476 (ADC3) must still be handled in -firmware, as noted previously. +All other important functions remained compatible between the two microcontrollers, including PWM generation, +complementary PWM outputs, encoder inputs, UART, USB, and CAN communication. Some differences between the ADC +peripherals of the STM32F405 and STM32L476 still remain and will require firmware adaptations in future work. \subsection{Schematic Design and KiCad Implementation} -The original Cheap FOCer-2 schematic was modified in KiCad to replace the -integrated F405 with connectors for the L476 tile. The main modifications -included: +The original Cheap FOCer-2 schematic was modified in KiCad in order to replace the integrated STM32F405 +microcontroller with connectors for the Rocacher STM32L476 tile. The objective was to make the control part more +modular and easier to replace without modifying the power stage of the board. + +The main modifications performed on the schematic were: \begin{itemize} - \item Removal of the F405 and its associated passive components. - \item Addition of two 20-pin headers to receive the Rocacher tile. - \item Re-routing of PWM, ADC, and USB signals to the headers. + \item Removal of the STM32F405 and its associated passive components. + \item Addition of two 20-pin headers for the L476 tile connection. + \item Re-routing of PWM, ADC, USB, and communication signals toward the headers. \end{itemize} -The schematic passed Electrical Rule Check (ERC) with no errors. +Special attention was given to the routing of critical control signals, especially the PWM outputs used for +motor commutation and the analog signals used for current sensing. + +After the modifications, the schematic was verified using the KiCad Electrical Rule Check (ERC). No electrical +errors were detected during this verification step, which validated the consistency of the schematic before +starting the PCB routing phase. \subsection{Routing Challenges and Current Status} -The PCB layout was then started. The original Cheap FOCer-2 routing is -very dense. Inserting connectors for the removable tile while maintaining signal integrity proved -difficult. +After validating the schematic, the PCB routing phase was started in KiCad. The original Cheap FOCer-2 board +uses a very compact layout with dense routing around the STM32F405 microcontroller and the power stage. +Integrating connectors for a removable STM32L476 tile introduced several additional routing constraints. -The main issues encountered were: +One of the main difficulties was maintaining proper signal routing while keeping enough space for the tile +connectors and preserving the integrity of the control signals. Particular attention had to be given to the PWM +signals, current sensing traces, and power connections. + +Several issues were encountered during the routing process: \begin{itemize} - \item Some footprints for the tile connectors did not appear correctly - in the layout after schematic import. - \item Routing of high-current paths (battery, motor phases) around the - connectors required additional vias, increasing resistance. - \item Decoupling capacitors had to be repositioned, raising concerns - about switching noise. + \item Some connector footprints associated with the tile did not appear correctly after importing the schematic + into the PCB layout. + \item The routing of high-current paths, especially the battery and motor phase connections, become more complex + due to the additional connectors and required extra vias. + \item Some Decoupling capacitors had to be repositioned, which could potentially affect switching noise and power + supply stability. \end{itemize} -Currently, the schematic is validated, and the layout is under -development. Once routing is completed, the board will be manufactured -and tested with the VESC firmware adapted to the L476 tile. + +At the current stage of the project, the schematic has been validated and the PCB layout is still under development. +Once the routing is completed, the board will be manufactured and tested using the VESC firmware adapted for the +STM32L476 tile. % ************************************** SOFTWARE AND CONNECTIVITY *****************************************************