forked from acco/chti23
steb debute 2 + pwm
This commit is contained in:
parent
d40bdf526d
commit
2304e386e9
5 changed files with 40 additions and 29 deletions
|
@ -6,25 +6,43 @@
|
||||||
;Section RAM (read only) :
|
;Section RAM (read only) :
|
||||||
area mesdata,data,readonly
|
area mesdata,data,readonly
|
||||||
|
|
||||||
|
IMPORT GPIOC_Set
|
||||||
|
IMPORT GPIOC_Clear
|
||||||
|
|
||||||
;Section RAM (read write):
|
;Section RAM (read write):
|
||||||
area maram,data,readwrite
|
area maram,data,readwrite
|
||||||
|
|
||||||
|
FlagCligno DCW 0
|
||||||
|
|
||||||
; ===============================================================================================
|
; ===============================================================================================
|
||||||
|
|
||||||
|
EXPORT timer_callback
|
||||||
|
|
||||||
|
|
||||||
;Section ROM code (read only) :
|
;Section ROM code (read only) :
|
||||||
area moncode,code,readonly
|
area moncode,code,readonly
|
||||||
; écrire le code ici
|
; écrire le code ici
|
||||||
|
|
||||||
|
timer_callback proc
|
||||||
|
push {lr}
|
||||||
|
mov r0, #12
|
||||||
|
ldr r2, =FlagCligno
|
||||||
|
ldr r1, [r2]
|
||||||
|
cmp r1, #1
|
||||||
|
bne Reset
|
||||||
|
mov r1, #0
|
||||||
|
str r1, [r2]
|
||||||
|
bl GPIOC_Set
|
||||||
|
pop {lr}
|
||||||
|
bx lr
|
||||||
|
Reset
|
||||||
|
mov r1, #1
|
||||||
|
str r1, [r2]
|
||||||
|
bl GPIOC_Clear
|
||||||
|
pop {lr}
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
END
|
||||||
END
|
|
|
@ -42,21 +42,3 @@ while (1)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
char FlagCligno;
|
|
||||||
|
|
||||||
void timer_callback(void)
|
|
||||||
{
|
|
||||||
if (FlagCligno==1)
|
|
||||||
{
|
|
||||||
FlagCligno=0;
|
|
||||||
GPIOC_Set(12);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
FlagCligno=1;
|
|
||||||
GPIOC_Clear(12);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
|
@ -6,6 +6,7 @@
|
||||||
;Section RAM (read only) :
|
;Section RAM (read only) :
|
||||||
area mesdata,data,readonly
|
area mesdata,data,readonly
|
||||||
|
|
||||||
|
IMPORT PWM_Set_Value_TIM3_Ch3
|
||||||
IMPORT LongueurSon
|
IMPORT LongueurSon
|
||||||
IMPORT Son
|
IMPORT Son
|
||||||
|
|
||||||
|
@ -26,6 +27,7 @@ SortieSon DCW 0
|
||||||
; écrire le code ici
|
; écrire le code ici
|
||||||
|
|
||||||
CallbackSon proc
|
CallbackSon proc
|
||||||
|
push {lr}
|
||||||
ldr r0, =IndexSon ; r0 = &IndexSon
|
ldr r0, =IndexSon ; r0 = &IndexSon
|
||||||
ldrh r1, [r0] ; r1 = IndexSon
|
ldrh r1, [r0] ; r1 = IndexSon
|
||||||
|
|
||||||
|
@ -46,6 +48,9 @@ NoReset
|
||||||
str r1, [r0] ; IndexSon++;
|
str r1, [r0] ; IndexSon++;
|
||||||
ldr r0, =SortieSon ; r0 = &SortieSon
|
ldr r0, =SortieSon ; r0 = &SortieSon
|
||||||
strh r2, [r0] ; SortieSon = ce qu'on veut
|
strh r2, [r0] ; SortieSon = ce qu'on veut
|
||||||
|
mov r0, r2
|
||||||
|
bl PWM_Set_Value_TIM3_Ch3
|
||||||
|
pop {lr}
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
ENDP
|
ENDP
|
||||||
|
|
|
@ -12,9 +12,10 @@ int main(void)
|
||||||
// Après exécution : le coeur CPU est clocké à 72MHz ainsi que tous les timers
|
// Après exécution : le coeur CPU est clocké à 72MHz ainsi que tous les timers
|
||||||
CLOCK_Configure();
|
CLOCK_Configure();
|
||||||
GPIO_Configure(GPIOB, 0, OUTPUT, ALT_PPULL);
|
GPIO_Configure(GPIOB, 0, OUTPUT, ALT_PPULL);
|
||||||
PWM_Init_ff(TIM3, 3, 720);
|
PWM_Init_ff(TIM3, 3, 720); // f_PWM = 72MHz/720 = 100kHz
|
||||||
Timer_1234_Init_ff(TIM4, 6552); // (91*10^-6)*(72*10^6) = 6552
|
Timer_1234_Init_ff(TIM4, 6552); // periode_son/f_CPU = (91*10^-6)*(72*10^6) = 6552
|
||||||
Active_IT_Debordement_Timer(TIM4, 2, CallbackSon);
|
Active_IT_Debordement_Timer(TIM4, 2, CallbackSon);
|
||||||
|
|
||||||
//============================================================================
|
//============================================================================
|
||||||
|
|
||||||
while (1)
|
while (1)
|
||||||
|
|
|
@ -215,7 +215,12 @@
|
||||||
<Wi>
|
<Wi>
|
||||||
<IntNumber>0</IntNumber>
|
<IntNumber>0</IntNumber>
|
||||||
<FirstString>`SortieSon</FirstString>
|
<FirstString>`SortieSon</FirstString>
|
||||||
<SecondString>008000000000000000000000000000905D78864100000000000000000000000000000000536F72746965536F6E00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004100000001000000000000000000F03F0D0000000000000000000000000000000000000094080008</SecondString>
|
<SecondString>008000000000000000000000000000905D78864100000000000000000000000000000000536F72746965536F6E00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004100000001000000000000000000E03F170000000000000000000000000000000000000094080008</SecondString>
|
||||||
|
</Wi>
|
||||||
|
<Wi>
|
||||||
|
<IntNumber>1</IntNumber>
|
||||||
|
<FirstString>((portb & 0x00000001) & 0x11111111) >> 0</FirstString>
|
||||||
|
<SecondString>00800000000000000000000000000000E0FFEF400100000000000000000000000000000028706F72746220262030783030303030303031290000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000002000000000000000000E03F1700000000000000000000000000000000000000540A0008</SecondString>
|
||||||
</Wi>
|
</Wi>
|
||||||
</LogicAnalyzers>
|
</LogicAnalyzers>
|
||||||
<DebugDescription>
|
<DebugDescription>
|
||||||
|
|
Loading…
Reference in a new issue