87 lines
3 KiB
VHDL
87 lines
3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12.05.2023 16:14:24
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-- Design Name:
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-- Module Name: ALU - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALU is
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
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B : in STD_LOGIC_VECTOR (7 downto 0);
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Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0);
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S : out STD_LOGIC_VECTOR (7 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end ALU;
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-- Instruction code
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-- ADD x"01"
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-- MUL x"02"
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-- SUB x"03"
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-- DIV x"04"
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-- INF x"09"
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-- SUP x"0A"
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-- EQ x"0B"
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-- NOT x"0C"
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-- AND x"0D"
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-- OR x"0E"
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-- XOR x"0F"
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architecture Behavioral of ALU is
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signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
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begin
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process(A, B, Ctrl_Alu)
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begin
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N <= '0';
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O <= '0';
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Z <= '0';
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C <= '0';
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case Ctrl_Alu is
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when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD
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when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL
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when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB
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when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV
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when x"09" => if A < B then res <= x"0001"; else res <= x"0000"; end if;
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when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if;
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when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if;
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when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if;
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when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; else res <= x"0000"; end if;
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when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; else res <= x"0000"; end if;
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when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; else res <= x"0000"; end if;
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when others => res <= x"0000";
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end case;
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end process;
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S <= res(7 downto 0);
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end Behavioral;
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