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Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15.05.2023 14:29:58
-- Design Name:
-- Module Name: Pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pipeline is
Port (Clk : in STD_LOGIC);
end Pipeline;
architecture Behavioral of Pipeline is
component IP is
port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 1
LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 0
Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal rst : STD_LOGIC := '0';
component InstructionMemory
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '1');
component Stage_Li_Di
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
In_B : in STD_LOGIC_VECTOR (7 downto 0);
In_C : in STD_LOGIC_VECTOR (7 downto 0);
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component Registers
Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
Addr_W : in STD_LOGIC_VECTOR (3 downto 0);
W : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (7 downto 0);
QB : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component Stage_Di_Ex
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
In_B : in STD_LOGIC_VECTOR (7 downto 0);
In_C : in STD_LOGIC_VECTOR (7 downto 0);
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0);
S : out STD_LOGIC_VECTOR (7 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC;
JumpFlag : inout STD_LOGIC
);
end component;
signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag, Jump_Flag : STD_LOGIC;
component Stage_Ex_Mem
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
In_B : in STD_LOGIC_VECTOR (7 downto 0);
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Mem_RW : STD_LOGIC;
signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
component DataMemory
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
Data_in : in STD_LOGIC_VECTOR (7 downto 0);
Rw : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component Stage_Mem_Re
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
In_B : in STD_LOGIC_VECTOR (7 downto 0);
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component AleaControler is
Port ( Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0);
A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0);
B_DI : in STD_LOGIC_VECTOR (7 downto 0);
C_DI : in STD_LOGIC_VECTOR (7 downto 0);
CNTRL : out STD_LOGIC
);
end component;
signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Re_W : STD_LOGIC;
-- to control jumping and where to jump
signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal jump : STD_LOGIC := '0';
signal nop_Cntrl : STD_LOGIC;
signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
signal Di_Op_Final : STD_LOGIC_VECTOR (7 downto 0) := (others => '1');
begin
-- instructionPointer
inst_point : IP port map (
CLK=> clk,
Dout=> IP_out,
Din => addr_to_jump,
RST => rst,
EN => nop_Cntrl,
LOAD => jump);
-- instructionMemory
MemInst : InstructionMemory PORT MAP (
Addr => IP_out,
Clk => Clk,
Inst_out => Li);
-- Stage_Li_Di
Stage1 : Stage_Li_Di PORT MAP (
In_A => Li(23 downto 16),
In_B => Li(15 downto 8),
In_C => Li(7 downto 0),
In_Op => OP_LI_DI,
Clk => Clk,
Out_A => Di_A,
Out_B => Di_B,
Out_Op => Di_Op,
Out_C => Di_C);
-- Registers
StageRegisters : Registers PORT MAP (
Addr_A => Di_B(3 downto 0), -- because the registers are on 4 bits
Addr_B => Di_C(3 downto 0),
Addr_W => Re_A(3 downto 0),
W => Re_W,
Data => Re_B,
Rst => Rst,
Clk => Clk,
QA => Di_RegB,
QB => Di_C2);
-- Stage DI/EX
Stage2 : Stage_Di_Ex PORT MAP (
In_A => Di_A,
In_B => Di_FinalB,
In_C => Di_C2,
In_Op => Di_Op_Final,
Clk => Clk,
Out_A => Ex_A,
Out_B => Ex_B,
Out_Op => Ex_Op,
Out_C => Ex_C);
-- ALU
Ual : ALU PORT MAP (
A => Ex_B,
B => Ex_C,
Ctrl_Alu => Ex_Ctrl_ALu,
S => Ex_Res_Alu,
N => S_NFlag,
O => S_OFlag,
Z => S_ZFlag,
C => S_CFlag,
JumpFlag => Jump_Flag);
-- Stage Ex/Mem
Stage3 : Stage_Ex_Mem PORT MAP (
In_A => Ex_A,
In_B => Ex_FinalB,
In_Op => Ex_Op,
Clk => Clk,
Out_A => Mem_A,
Out_B => Mem_B,
Out_Op => Mem_Op);
-- DataMemory
DataMem : DataMemory PORT MAP (
Addr => Mem_Addr,
Data_in => Mem_B,
Rw => Mem_RW,
Rst => Rst,
Clk => Clk,
Data_out => Mem_Data_Out);
-- Stage Mem/RE
Stage4 : Stage_Mem_Re PORT MAP (
In_A => Mem_A,
In_B => Mem_FinalB,
In_Op => Mem_Op,
Clk => Clk,
Out_A => Re_A,
Out_B => Re_B,
Out_Op => Re_Op);
-- Instruction code
-- ADD x"01"
-- MUL x"02"
-- SUB x"03"
-- DIV x"04"
-- COP x"05"
-- AFC x"06"
-- LOAD x"07"OP_DI
-- STORE x"08"
-- INF x"09"
-- SUP x"0A"
-- EQ x"0B"
-- NOT x"0C"
-- AND x"0D"
-- OR x"0E"
-- JMP x"0F"
-- JMF x"10"
-- CAL x"11"
-- RET x"12"
-- PRI x"13"
-- NOP x"FF"
-- Mux post registers
Di_FinalB <= Di_B when
Di_OP = x"06" or -- AFC
Di_OP = x"07" -- LOAD
else Di_RegB;
-- Mux post ALU
Ex_FinalB <= Ex_B when
Ex_Op = x"06" --AFC
or Ex_Op = x"05" --COP
or Ex_Op = x"07" --LOAD
or Ex_Op = x"08" --STORE
else Ex_Res_Alu;
-- LC pre ALU
Ex_Ctrl_ALu <= x"00" when Ex_Op = x"05" or Ex_Op = x"06" or Ex_Op = x"07" or Ex_Op = x"08" --(not using ALU)
else Ex_Op;
-- Mux post data memory
Mem_FinalB <= Mem_B when
Mem_Op = x"06" --AFC
or Mem_Op = x"05" --COP
or Mem_Op = x"01" --ADD
or Mem_Op = x"03" -- SUB
or Mem_Op = x"02" -- MUL
or Mem_Op = x"04" -- DIV
else Mem_Data_out ; --LOAD & STORE
-- Mux pre data memory
Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD
else Mem_A; --STORE
-- LC pre data memory
Mem_RW <= '0' when Mem_Op = x"08" --STORE
else '1'; --STORE
-- LC post Pip_Mem_Re
Re_W <= '0' when Re_Op = x"08" or Re_Op = x"ff" --STORE
else '1';
CU : AleaControler port map (
Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, Op_Re => Mem_Op,
A_EX => Di_A, A_Mem => Ex_A, A_Re => Mem_A,
B_DI => Li(15 downto 8),
C_DI => Li(7 downto 0),
CNTRL => nop_Cntrl);
-- in case of alea : replace li(31 downto 24) by NOP
OP_LI_DI <= X"ff" when (nop_Cntrl='1' or
(Di_Op = x"10" and Jump_Flag = '1')) -- to prevent JMF
else Li(31 downto 24);
-- jump JMP
addr_to_jump <= DI_A when (DI_OP = x"0F") -- JMP
else Di_B when (Di_Op = x"10" and Jump_Flag = '0') -- JMF
else (others => '0');
jump <= '1' when DI_OP = x"0F" -- JMP
or (Di_Op = x"10" and Jump_Flag = '0') -- JMF
else '0';
-- case of JMF not triggering
Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1')
else Di_Op;
end Behavioral;
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