53 lines
2.1 KiB
VHDL
53 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15.05.2023 13:55:29
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-- Design Name:
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-- Module Name: InstructionMemory - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity InstructionMemory is
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Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
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Clk : in STD_LOGIC;
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Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
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end InstructionMemory;
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architecture Behavioral of InstructionMemory is
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type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
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signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000"));
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begin
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process
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begin
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wait until clk'event and clk = '1';
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Inst_out <= Mem(to_integer(unsigned(Addr)));
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end process;
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end Behavioral;
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