471 lines
29 KiB
Text
471 lines
29 KiB
Text
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*** Running vivado
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with args -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace
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****** Vivado v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source Pipeline.tcl -notrace
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Command: link_design -top Pipeline -part xc7a35tcpg236-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.2
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INFO: [Device 21-403] Loading part xc7a35tcpg236-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
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WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
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CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
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Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
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WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
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CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
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Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
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Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 6 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: 1e379f571
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Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 1e379f571
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Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 224c05fcb
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Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 237fe1223
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Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 237fe1223
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Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 141d47eb5
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Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 141d47eb5
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Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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Ending Logic Optimization Task | Checksum: 141d47eb5
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Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 141d47eb5
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 141d47eb5
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
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INFO: [Common 17-83] Releasing license: Implementation
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23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594
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INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx
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Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'.
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INFO: [DRC 23-27] Running DRC with 6 threads
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INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [DRC 23-27] Running DRC with 6 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 6 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db
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Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd
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Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0
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Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0
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Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 1 Placer Initialization | Checksum: e4604ef0
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Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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Phase 2 Global Placement
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Phase 2.1 Floorplanning
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Phase 2.1 Floorplanning | Checksum: e4604ef0
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Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
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WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
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Phase 2 Global Placement | Checksum: 15cb247ff
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 3 Detail Placement | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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Phase 4.1 Post Commit Optimization | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 112e53995
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 4.4 Final Placement Cleanup
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Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
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Ending Placer Task | Checksum: 8268151a
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535
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INFO: [Common 17-83] Releasing license: Implementation
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41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535
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INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537
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INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb
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report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 6 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs
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Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: 77742d47
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437
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Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: 77742d47
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: 77742d47
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422
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Number of Nodes with overlaps = 0
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Phase 2 Router Initialization | Checksum: 16523de4e
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412
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Phase 3 Initial Routing
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Phase 3 Initial Routing | Checksum: 11b0f7581
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 97
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Number of Nodes with overlaps = 0
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Phase 4.1 Global Iteration 0 | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 4 Rip-up And Reroute | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 6 Post Hold Fix | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.153313 %
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Global Horizontal Routing Utilization = 0.172046 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
|
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
|
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----------------
|
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Congested clusters found at Level 0
|
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
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Direction: East
|
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----------------
|
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Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
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Direction: West
|
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----------------
|
|
Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
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Phase 7 Route finalize | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: 14cade65a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412
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|
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: 16fad2baa
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
|
route_design completed successfully
|
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route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430
|
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INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Writing XDEF routing.
|
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Writing XDEF routing logical nets.
|
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427
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|
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
|
|
Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
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INFO: [DRC 23-27] Running DRC with 6 threads
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt.
|
|
report_drc completed successfully
|
|
INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx
|
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Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx
|
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INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
INFO: [DRC 23-133] Running Methodology with 6 threads
|
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt.
|
|
report_methodology completed successfully
|
|
INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx
|
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Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx
|
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WARNING: [Power 33-232] No user defined clocks were found in the design!
|
|
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running Vector-less Activity Propagation...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
|
report_power completed successfully
|
|
INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
|
|
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt
|
|
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
|
|
Command: write_bitstream -force Pipeline.bit
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
|
Running DRC as a precondition to command write_bitstream
|
|
INFO: [DRC 23-27] Running DRC with 6 threads
|
|
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
|
|
|
set_property CFGBVS value1 [current_design]
|
|
#where value1 is either VCCO or GND
|
|
|
|
set_property CONFIG_VOLTAGE value2 [current_design]
|
|
#where value2 is the voltage provided to configuration bank 0
|
|
|
|
Refer to the device configuration user guide for more information.
|
|
WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2.
|
|
WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7.
|
|
WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
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|
WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 6 threads.
|
|
Loading data files...
|
|
Loading site data...
|
|
Loading route data...
|
|
Processing options...
|
|
Creating bitmap...
|
|
Creating bitstream...
|
|
Writing bitstream ./Pipeline.bit...
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
|
write_bitstream completed successfully
|
|
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368
|
|
INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023...
|