153 lines
7.7 KiB
Text
153 lines
7.7 KiB
Text
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
----------------------------------------------------------------------------------------------------------------------------------------------
|
|
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
|
|
| Date : Wed May 31 17:58:13 2023
|
|
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
|
|
| Command : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx
|
|
| Design : Pipeline
|
|
| Device : xc7a35tcpg236-1
|
|
| Design State : routed
|
|
| Grade : commercial
|
|
| Process : typical
|
|
| Characterization : Production
|
|
----------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
Power Report
|
|
|
|
Table of Contents
|
|
-----------------
|
|
1. Summary
|
|
1.1 On-Chip Components
|
|
1.2 Power Supply Summary
|
|
1.3 Confidence Level
|
|
2. Settings
|
|
2.1 Environment
|
|
2.2 Clock Constraints
|
|
3. Detailed Reports
|
|
3.1 By Hierarchy
|
|
|
|
1. Summary
|
|
----------
|
|
|
|
+--------------------------+--------------+
|
|
| Total On-Chip Power (W) | 3.334 |
|
|
| Design Power Budget (W) | Unspecified* |
|
|
| Power Budget Margin (W) | NA |
|
|
| Dynamic (W) | 3.253 |
|
|
| Device Static (W) | 0.081 |
|
|
| Effective TJA (C/W) | 5.0 |
|
|
| Max Ambient (C) | 68.3 |
|
|
| Junction Temperature (C) | 41.7 |
|
|
| Confidence Level | Low |
|
|
| Setting File | --- |
|
|
| Simulation Activity File | --- |
|
|
| Design Nets Matched | NA |
|
|
+--------------------------+--------------+
|
|
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
|
|
|
|
|
1.1 On-Chip Components
|
|
----------------------
|
|
|
|
+----------------+-----------+----------+-----------+-----------------+
|
|
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
|
+----------------+-----------+----------+-----------+-----------------+
|
|
| Slice Logic | 1.294 | 831 | --- | --- |
|
|
| LUT as Logic | 1.166 | 371 | 20800 | 1.78 |
|
|
| CARRY4 | 0.105 | 33 | 8150 | 0.40 |
|
|
| Register | 0.018 | 342 | 41600 | 0.82 |
|
|
| BUFG | 0.006 | 1 | 32 | 3.13 |
|
|
| F7/F8 Muxes | <0.001 | 19 | 32600 | 0.06 |
|
|
| Others | 0.000 | 13 | --- | --- |
|
|
| Signals | 1.154 | 691 | --- | --- |
|
|
| I/O | 0.804 | 13 | 106 | 12.26 |
|
|
| Static Power | 0.081 | | | |
|
|
| Total | 3.334 | | | |
|
|
+----------------+-----------+----------+-----------+-----------------+
|
|
|
|
|
|
1.2 Power Supply Summary
|
|
------------------------
|
|
|
|
+-----------+-------------+-----------+-------------+------------+
|
|
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
|
+-----------+-------------+-----------+-------------+------------+
|
|
| Vccint | 1.000 | 2.486 | 2.468 | 0.018 |
|
|
| Vccaux | 1.800 | 0.042 | 0.029 | 0.013 |
|
|
| Vcco33 | 3.300 | 0.223 | 0.222 | 0.001 |
|
|
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
|
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
|
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
|
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
|
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
|
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
|
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 |
|
|
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
|
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
|
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
|
+-----------+-------------+-----------+-------------+------------+
|
|
|
|
|
|
1.3 Confidence Level
|
|
--------------------
|
|
|
|
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
|
| User Input Data | Confidence | Details | Action |
|
|
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
|
| Design implementation state | High | Design is routed | |
|
|
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
|
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
|
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
|
| Device models | High | Device models are Production | |
|
|
| | | | |
|
|
| Overall confidence level | Low | | |
|
|
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
2. Settings
|
|
-----------
|
|
|
|
2.1 Environment
|
|
---------------
|
|
|
|
+-----------------------+--------------------------+
|
|
| Ambient Temp (C) | 25.0 |
|
|
| ThetaJA (C/W) | 5.0 |
|
|
| Airflow (LFM) | 250 |
|
|
| Heat Sink | medium (Medium Profile) |
|
|
| ThetaSA (C/W) | 4.6 |
|
|
| Board Selection | medium (10"x10") |
|
|
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
|
| Board Temperature (C) | 25.0 |
|
|
+-----------------------+--------------------------+
|
|
|
|
|
|
2.2 Clock Constraints
|
|
---------------------
|
|
|
|
+-------+--------+-----------------+
|
|
| Clock | Domain | Constraint (ns) |
|
|
+-------+--------+-----------------+
|
|
|
|
|
|
3. Detailed Reports
|
|
-------------------
|
|
|
|
3.1 By Hierarchy
|
|
----------------
|
|
|
|
+------------------+-----------+
|
|
| Name | Power (W) |
|
|
+------------------+-----------+
|
|
| Pipeline | 3.253 |
|
|
| DataMem | 0.035 |
|
|
| Stage1 | 0.205 |
|
|
| Stage2 | 1.072 |
|
|
| Stage3 | 0.208 |
|
|
| Stage4 | 0.140 |
|
|
| StageRegisters | 0.099 |
|
|
| Ual | 0.165 |
|
|
| inst_point | 0.416 |
|
|
+------------------+-----------+
|
|
|
|
|