145 lines
4 KiB
VHDL
145 lines
4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12.05.2023 17:40:52
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-- Design Name:
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-- Module Name: Test_Alu - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Alu is
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-- Port ( );
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end Test_Alu;
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architecture Behavioral of Test_Alu is
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component ALU
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Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
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B : in STD_LOGIC_VECTOR (7 downto 0);
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Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); -- 000 + / 001 - / 010 * / 100 Div
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S : out STD_LOGIC_VECTOR (7 downto 0);
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N : out STD_LOGIC;
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O : out STD_LOGIC;
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Z : out STD_LOGIC;
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C : out STD_LOGIC);
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end component;
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-- inputs
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signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal local_Ctrl_Alu : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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--outputs
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signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal local_N : STD_LOGIC := '0';
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signal local_O : STD_LOGIC := '0';
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signal local_Z : STD_LOGIC := '0';
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signal local_C : STD_LOGIC := '0';
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-- constant Clock_period : time := 10ns;
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begin
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-- instantiate
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instance : ALU PORT MAP (
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A => local_A,
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B => local_B,
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Ctrl_Alu => local_Ctrl_Alu,
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S => local_S,
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N => local_N,
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O => local_O,
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Z => local_Z,
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C => local_C
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);
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local_Ctrl_Alu <= x"01", -- ADD
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x"02" after 40 ns, -- MUL
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x"03" after 60 ns, -- SUB
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x"04" after 90 ns, -- DIV
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x"09" after 120 ns, -- INF
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x"0A" after 140 ns, -- SUP
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x"0B" after 160 ns, -- EQ
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x"0C" after 180 ns, -- NOT
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x"0D" after 210 ns, -- XOR
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x"0E" after 240 ns, -- OR
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x"0F" after 270 ns; -- XOR
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local_A <= x"00",
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x"00" after 10 ns,
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x"0A" after 20 ns,
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x"96" after 30 ns,
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x"1D" after 40 ns,
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x"0A" after 50 ns,
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x"0B" after 60 ns,
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x"0F" after 70 ns,
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x"19" after 80 ns,
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x"12" after 90 ns,
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x"18" after 100 ns,
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x"19" after 110 ns,
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x"10" after 120 ns,
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x"20" after 130 ns,
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x"10" after 150 ns,
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x"0A" after 160 ns,
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x"0B" after 170 ns,
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x"01" after 180 ns,
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x"25" after 190 ns,
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x"00" after 200 ns,
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x"0A" after 210 ns,
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x"00" after 230 ns,
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x"0A" after 240 ns,
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x"00" after 260 ns,
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x"0A" after 270 ns,
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x"00" after 290 ns;
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local_B <= x"00",
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x"00" after 10 ns,
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x"82" after 20 ns,
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x"A0" after 30 ns,
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x"09" after 40 ns,
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x"04" after 50 ns,
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x"0B" after 60 ns,
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x"12" after 70 ns,
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x"0B" after 80 ns,
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x"00" after 90 ns,
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x"06" after 100 ns,
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x"07" after 110 ns,
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x"20" after 120 ns,
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x"10" after 130 ns,
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x"20" after 150 ns,
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x"0A" after 160 ns,
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x"02" after 170 ns,
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x"00" after 190 ns,
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x"0B" after 210 ns,
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x"00" after 220 ns,
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x"0B" after 240 ns,
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x"00" after 250 ns,
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x"0B" after 270 ns,
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x"00" after 280 ns;
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end Behavioral;
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