619 lines
52 KiB
Text
619 lines
52 KiB
Text
#-----------------------------------------------------------
|
|
# Vivado v2018.2 (64-bit)
|
|
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|
# Start of session at: Wed May 31 17:56:19 2023
|
|
# Process ID: 144089
|
|
# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
|
# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
|
# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
|
|
# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
|
#-----------------------------------------------------------
|
|
source Pipeline.tcl -notrace
|
|
Command: synth_design -top Pipeline -part xc7a35tcpg236-1
|
|
Starting synth_design
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
|
INFO: Launching helper process for spawning children vivado processes
|
|
INFO: Helper process launched with PID 144101
|
|
---------------------------------------------------------------------------------
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.828 ; free physical = 7354 ; free virtual = 19137
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40]
|
|
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:182]
|
|
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
|
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
|
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:192]
|
|
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
|
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
|
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:198]
|
|
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
|
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
|
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:210]
|
|
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49]
|
|
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49]
|
|
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:224]
|
|
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
|
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
|
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:236]
|
|
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64]
|
|
WARNING: [Synth 8-614] signal 'JumpFlagIn' is read in the process but is not in the sensitivity list [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:68]
|
|
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64]
|
|
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:249]
|
|
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
|
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
|
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
|
|
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
|
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
|
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:268]
|
|
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
|
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
|
INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:339]
|
|
INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
|
|
INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40]
|
|
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40]
|
|
WARNING: [Synth 8-3331] design InstructionMemory has unconnected port Clk
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7345 ; free virtual = 19128
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report Check Netlist:
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
| |Item |Errors |Warnings |Status |Description |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
|
|
Processing XDC Constraints
|
|
Initializing timing engine
|
|
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
|
|
WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-507] No nets matched 'Stage2/Jump_Flag'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Pipeline_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/Pipeline_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
Completed Processing XDC Constraints
|
|
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000 ; free physical = 7109 ; free virtual = 18892
|
|
---------------------------------------------------------------------------------
|
|
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Loading Part and Timing Information
|
|
---------------------------------------------------------------------------------
|
|
Loading part: xc7a35tcpg236-1
|
|
---------------------------------------------------------------------------------
|
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying 'set_property' XDC Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
|
|
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7161 ; free virtual = 18945
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 9 Bit Adders := 1
|
|
2 Input 8 Bit Adders := 2
|
|
3 Input 8 Bit Adders := 1
|
|
+---Registers :
|
|
8 Bit Registers := 287
|
|
+---Muxes :
|
|
257 Input 32 Bit Muxes := 1
|
|
2 Input 8 Bit Muxes := 13
|
|
2 Input 1 Bit Muxes := 279
|
|
12 Input 1 Bit Muxes := 3
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Hierarchical Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Hierarchical RTL Component report
|
|
Module Pipeline
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
2 Input 8 Bit Muxes := 7
|
|
2 Input 1 Bit Muxes := 1
|
|
Module IP
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 8 Bit Adders := 1
|
|
+---Registers :
|
|
8 Bit Registers := 1
|
|
+---Muxes :
|
|
2 Input 8 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 1
|
|
Module InstructionMemory
|
|
Detailed RTL Component Info :
|
|
+---Muxes :
|
|
257 Input 32 Bit Muxes := 1
|
|
Module Stage_Li_Di
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 4
|
|
Module Registers
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 16
|
|
+---Muxes :
|
|
2 Input 8 Bit Muxes := 3
|
|
2 Input 1 Bit Muxes := 16
|
|
Module Stage_Di_Ex
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 4
|
|
Module ALU
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 9 Bit Adders := 1
|
|
3 Input 8 Bit Adders := 1
|
|
2 Input 8 Bit Adders := 1
|
|
+---Muxes :
|
|
2 Input 8 Bit Muxes := 2
|
|
2 Input 1 Bit Muxes := 5
|
|
12 Input 1 Bit Muxes := 3
|
|
Module Stage_Ex_Mem
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 3
|
|
Module DataMemory
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 256
|
|
+---Muxes :
|
|
2 Input 1 Bit Muxes := 256
|
|
Module Stage_Mem_Re
|
|
Detailed RTL Component Info :
|
|
+---Registers :
|
|
8 Bit Registers := 3
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Hierarchical Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 90 (col length:60)
|
|
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
Warning: Parallel synthesis criteria is not met
|
|
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
|
|
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
|
|
INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[5]' (FD) to 'Stage1/Out_Op_reg[7]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[7]' (FD) to 'Stage1/Out_Op_reg[6]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[6]' (FD) to 'Stage2/Out_Op_reg[7]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[7]' (FD) to 'Stage2/Out_Op_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[6]' (FD) to 'Stage3/Out_Op_reg[7]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[7]' (FD) to 'Stage3/Out_Op_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[6]' (FD) to 'Stage4/Out_Op_reg[7]'
|
|
INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[7]' (FD) to 'Stage4/Out_Op_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[46][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[47][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[44][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[45][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[42][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[43][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[40][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[41][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[38][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[39][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[36][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[37][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[34][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[35][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[32][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[33][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[62][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[63][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[60][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[61][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[58][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[59][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[56][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[57][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[54][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[55][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[52][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[53][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[50][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[51][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[48][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[49][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[30][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[31][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[28][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[29][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[26][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[27][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[24][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[25][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[22][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[23][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[20][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[21][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[18][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[19][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[16][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[17][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[238][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[239][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[236][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[237][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[234][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[235][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[232][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[233][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[230][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[231][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[228][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[229][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[226][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[227][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[224][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[225][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[254][0]' (FDRE) to 'DataMem/Mem_reg[255][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[255][0]' (FDRE) to 'DataMem/Mem_reg[253][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[252][0]' (FDRE) to 'DataMem/Mem_reg[253][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[253][0]' (FDRE) to 'DataMem/Mem_reg[251][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[250][0]' (FDRE) to 'DataMem/Mem_reg[251][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[251][0]' (FDRE) to 'DataMem/Mem_reg[249][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[248][0]' (FDRE) to 'DataMem/Mem_reg[249][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[249][0]' (FDRE) to 'DataMem/Mem_reg[247][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[246][0]' (FDRE) to 'DataMem/Mem_reg[247][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[247][0]' (FDRE) to 'DataMem/Mem_reg[245][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[244][0]' (FDRE) to 'DataMem/Mem_reg[245][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[245][0]' (FDRE) to 'DataMem/Mem_reg[243][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[242][0]' (FDRE) to 'DataMem/Mem_reg[243][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[243][0]' (FDRE) to 'DataMem/Mem_reg[241][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[240][0]' (FDRE) to 'DataMem/Mem_reg[241][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[241][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[206][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[207][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[204][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[205][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[202][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[203][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[200][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[201][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[198][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[199][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[196][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[197][0]' (FDRE) to 'DataMem/Mem_reg[223][0]'
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][0] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][1] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][2] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][3] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][4] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][5] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][6] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[153][7] )
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][0]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][1]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][2]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][3]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][4]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][5]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][6]) is unused and will be removed from module Pipeline.
|
|
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[153][7]) is unused and will be removed from module Pipeline.
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7123 ; free virtual = 18911
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18799
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18798
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report Check Netlist:
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
| |Item |Errors |Warnings |Status |Description |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
|
+------+------------------+-------+---------+-------+------------------+
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report RTL Partitions:
|
|
+-+--------------+------------+----------+
|
|
| |RTL Partition |Replication |Instances |
|
|
+-+--------------+------------+----------+
|
|
+-+--------------+------------+----------+
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+-+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+-+--------------+----------+
|
|
+-+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+-------+------+
|
|
| |Cell |Count |
|
|
+------+-------+------+
|
|
|1 |BUFG | 1|
|
|
|2 |CARRY4 | 33|
|
|
|3 |LUT2 | 51|
|
|
|4 |LUT3 | 67|
|
|
|5 |LUT4 | 41|
|
|
|6 |LUT5 | 55|
|
|
|7 |LUT6 | 209|
|
|
|8 |MUXF7 | 19|
|
|
|9 |FDRE | 330|
|
|
|10 |FDSE | 12|
|
|
|11 |IBUF | 5|
|
|
|12 |OBUF | 8|
|
|
+------+-------+------+
|
|
|
|
Report Instance Areas:
|
|
+------+-----------------+-------------+------+
|
|
| |Instance |Module |Cells |
|
|
+------+-----------------+-------------+------+
|
|
|1 |top | | 831|
|
|
|2 | DataMem |DataMemory | 168|
|
|
|3 | Stage1 |Stage_Li_Di | 35|
|
|
|4 | Stage2 |Stage_Di_Ex | 213|
|
|
|5 | Stage3 |Stage_Ex_Mem | 63|
|
|
|6 | Stage4 |Stage_Mem_Re | 37|
|
|
|7 | StageRegisters |Registers | 230|
|
|
|8 | Ual |ALU | 35|
|
|
|9 | inst_point |IP | 36|
|
|
+------+-----------------+-------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 10 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1651.219 ; gain = 139.453 ; free physical = 7056 ; free virtual = 18845
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7056 ; free virtual = 18845
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
270 Infos, 15 Warnings, 3 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 1659.227 ; gain = 499.406 ; free physical = 7043 ; free virtual = 18832
|
|
WARNING: [Constraints 18-5210] No constraint will be written out.
|
|
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
|
|
report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1683.238 ; gain = 0.000 ; free physical = 7046 ; free virtual = 18834
|
|
INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:57:07 2023...
|