61 lines
No EOL
1.5 KiB
VHDL
61 lines
No EOL
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21.03.2023 15:57:28
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-- Design Name:
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-- Module Name: compteur_8bits - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity IP is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC; -- rst when 1
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LOAD : in STD_LOGIC;
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EN : in STD_LOGIC; -- enable when 0
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Din : in STD_LOGIC_VECTOR (7 downto 0);
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Dout : out STD_LOGIC_VECTOR (7 downto 0));
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end IP;
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architecture Behavioral of IP is
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signal aux: STD_LOGIC_VECTOR (7 downto 0) := x"00";
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begin
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process
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begin
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wait until rising_edge(CLK);
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if (RST = '1') then
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aux <= x"00";
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elsif (LOAD = '1') then
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aux <= Din;
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elsif (EN = '0') then
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aux <= aux + x"01";
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end if;
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end process;
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Dout <= aux;
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end Behavioral; |