#----------------------------------------------------------- # Vivado v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 # Start of session at: Sun May 14 22:48:29 2023 # Process ID: 846737 # Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl # Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds # Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou #----------------------------------------------------------- source ALU.tcl -notrace Command: synth_design -top ALU -part xc7a35tcpg236-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 846814 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46] INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 INFO: [Device 21-403] Loading part xc7a35tcpg236-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753 --------------------------------------------------------------------------------- WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 16 Bit Adders := 1 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module ALU Detailed RTL Component Info : +---Adders : 3 Input 16 Bit Adders := 1 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |CARRY4 | 18| |2 |LUT2 | 31| |3 |LUT3 | 6| |4 |LUT4 | 41| |5 |LUT5 | 12| |6 |LUT6 | 52| |7 |LD | 16| |8 |IBUF | 19| |9 |OBUF | 12| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 207| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 16 instances were transformed. LD => LDCE: 16 instances INFO: [Common 17-83] Releasing license: Synthesis 11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596 WARNING: [Constraints 18-5210] No constraint will be written out. INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594 INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...