clock clock control signals label Clk Clk nop_Cntrl nop_Cntrl rst rst JumpFlag JumpFlag LI label Li[31:0] Li[31:0] IP_out[7:0] IP_out[7:0] OP_LI_DI[7:0] OP_LI_DI[7:0] DI label Di_A[7:0] Di_A[7:0] Di_Op[7:0] Di_Op[7:0] Di_B[7:0] Di_B[7:0] Di_C[7:0] Di_C[7:0] Di_RegB[7:0] Di_RegB[7:0] Di_FinalB[7:0] Di_FinalB[7:0] Di_C2[7:0] Di_C2[7:0] Ex label Ex_A[7:0] Ex_A[7:0] Ex_Op[7:0] Ex_Op[7:0] Ex_B[7:0] Ex_B[7:0] Ex_C[7:0] Ex_C[7:0] Ex_Ctrl_ALu[7:0] Ex_Ctrl_ALu[7:0] Ex_Res_Alu[7:0] Ex_Res_Alu[7:0] Ex_FinalB[7:0] Ex_FinalB[7:0] S_NFlag S_NFlag S_Oflag S_Oflag S_CFlag S_CFlag S_ZFlag S_ZFlag Mem label Mem_A[7:0] Mem_A[7:0] Mem_Op[7:0] Mem_Op[7:0] Mem_B[7:0] Mem_B[7:0] Mem_RW Mem_RW Mem_Addr[7:0] Mem_Addr[7:0] Mem_Data_Out[7:0] Mem_Data_Out[7:0] UNSIGNEDDECRADIX Mem_FinalB[7:0] Mem_FinalB[7:0] Re label Re_A[7:0] Re_A[7:0] Re_Op[7:0] Re_Op[7:0] Re_B[7:0] Re_B[7:0] Re_W Re_W addr_to_jump[7:0] addr_to_jump[7:0] jump jump W W registers label [0][7:0] [0][7:0] [1][7:0] [1][7:0] [2][7:0] [2][7:0] [3][7:0] [3][7:0] [4][7:0] [4][7:0] [5][7:0] [5][7:0] memory label [0][7:0] [0][7:0] SIGNEDDECRADIX [1][7:0] [1][7:0] [2][7:0] [2][7:0] [3][7:0] [3][7:0] SIGNEDDECRADIX [4][7:0] [4][7:0]