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-- Company: 
-- Engineer: 
-- 
-- Create Date: 21.03.2023 15:57:28
-- Design Name: 
-- Module Name: compteur_8bits - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IP is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC; -- rst when 1
           LOAD : in STD_LOGIC;
           EN : in STD_LOGIC; -- enable when 0
           Din : in STD_LOGIC_VECTOR (7 downto 0);
           Dout : out STD_LOGIC_VECTOR (7 downto 0));
end IP;

architecture Behavioral of IP is
    signal aux: STD_LOGIC_VECTOR (7 downto 0) := x"00";
begin
    process
    begin
        wait until rising_edge(CLK);
        
        if (RST = '1') then
            aux <= x"00";
        elsif (LOAD = '1') then
            aux <= Din;
        elsif (EN = '0') then
            aux <= aux + x"01";
        end if;
    end process;
    Dout <= aux; 
end Behavioral;