---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12.05.2023 17:40:52 -- Design Name: -- Module Name: Test_Alu - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Test_total is -- Port ( ); end Test_total; architecture Behavioral of test_total is component Pipeline Port (Clk : in STD_LOGIC); end component; constant clock_period : time := 10 ns; signal clock : Std_logic := '0'; begin -- instantiate Pl : Pipeline PORT MAP ( Clk => clock ); Clock_process : process begin clock <= not(clock); wait for 100ns; end process; end Behavioral;