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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12.05.2023 17:40:52
-- Design Name: 
-- Module Name: Test_cpu - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_CPU is
--  Port ( );
end Test_CPU;

architecture Behavioral of test_total is


    component CPU
    Port (Clk : in STD_LOGIC;
        reg_addr : in STD_LOGIC_VECTOR(3 downto 0);
        reg_val : out STD_LOGIC_VECTOR(7 downto 0));
    end component;
    constant clock_period : time := 10 ns;

    signal clock : Std_logic := '0';
    signal a : STD_LOGIC_VECTOR(7 downto 0);
    
begin
    -- instantiate 
    Pl : CPU PORT MAP (
        Clk => clock,
        reg_addr => x"0",
        reg_val => a
    );
    
    Clock_process : process
    begin
        clock <= not(clock);
        wait for 100ns;
    end process;

end Behavioral;