library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Instruction coEX
    -- ADD    00000001
    -- MUL    00000010
    -- SUB    00000011
    -- DIV    00000100
    -- COP    00000101
    -- AFC    00000110
    -- LOAD   00000111
    -- STORE  00001000
    -- INF    00001001
    -- SUP    00001010
    -- EQ     00001011
    -- NOT    00001100
    -- AND    00001101
    -- OR     00001110
    -- NOP    11111111



-- when the just entered instruction causes a problem with an instruction already in the EX or Mem stage (a write-Back stage would not cause any harm) we:
    -- we freeze IP on the current instruction
    -- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish

entity AleaControler is
  Port (
    -- get the current op and variables from the 3 pipelines stages that can interract
    Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0);
    A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0);
    B_DI : in STD_LOGIC_VECTOR (7 downto 0);
    C_DI : in STD_LOGIC_VECTOR (7 downto 0);
    
    CNTRL : out STD_LOGIC);
end AleaControler;


architecture Behavioral of AleaControler is
    signal alea_DI_EX, alea_DI_MEM: STD_LOGIC;
    signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC;
begin
        CNTRL <=   -- either a problem between the 1st and 2nd or 1st and 3rd
          '1' when 
                  -- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
                  (
                      -- check Op1 & Op2
                      ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_EX /= x"08" and Op_EX /= x"ff")) and 
      
                      -- check Registers are the same
                      ((A_Ex = B_DI) or (A_EX = C_DI))
                  ) or
                  
                  -- read after write : Op1 other than STORE/NOP, op3 other than AFC/NOP, R(write) = R(read)
                  (
                      -- check Op1 & Op2
                      ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Mem /= x"08" and Op_Mem /= x"ff")) and 
      
                      -- check Registers are the same
                      ((A_Mem = B_DI) or (A_Mem = C_DI))
                  ) or
                   
                   -- read after write : Op1 other than STORE/NOP, op4 other than AFC/NOP, R(write) = R(read)
                   (
                       -- check Op1 & Op2
                       ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Re /= x"08" and Op_Re /= x"ff")) and 
       
                       -- check Registers are the same
                       ((A_Re = B_DI) or (A_Re = C_DI))
                   )            
             else '0';
end Behavioral;