----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12.05.2023 17:40:52
-- Design Name: 
-- Module Name: Test_Alu - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Alu is
--  Port ( );
end Test_Alu;

architecture Behavioral of Test_Alu is


    component ALU
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); -- 000 + / 001 - / 010 * / 100 Div 
           S : out STD_LOGIC_VECTOR (7 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
    end component;
    
    -- inputs
     signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
     signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
     signal local_Ctrl_Alu : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
     
     --outputs 
     signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
     signal local_N : STD_LOGIC := '0';
     signal local_O : STD_LOGIC := '0';
     signal local_Z : STD_LOGIC := '0';
     signal local_C : STD_LOGIC := '0';
 
 -- constant Clock_period : time := 10ns;
 
begin
 
-- instantiate 
instance : ALU PORT MAP (
    A => local_A,
    B => local_B,
    Ctrl_Alu => local_Ctrl_Alu,
    S => local_S,
    N => local_N,
    O => local_O,
    Z => local_Z,
    C => local_C
);

local_Ctrl_Alu <= x"01", -- ADD
            x"02" after 40 ns, -- MUL
            x"03" after 60 ns, -- SUB
            x"04" after 90 ns, -- DIV
            x"09" after 120 ns, -- INF
            x"0A" after 140 ns, -- SUP
            x"0B" after 160 ns, -- EQ
            x"0C" after 180 ns, -- NOT
            x"0D" after 210 ns, -- XOR
            x"0E" after 240 ns, -- OR
            x"0F" after 270 ns; -- XOR
            
local_A <= x"00",
            x"00" after 10 ns,
            x"0A" after 20 ns,
            x"96" after 30 ns,
            x"1D" after 40 ns,
            x"0A" after 50 ns,
            x"0B" after 60 ns,
            x"0F" after 70 ns,
            x"19" after 80 ns,
            x"12" after 90 ns,
            x"18" after 100 ns,
            x"19" after 110 ns,
            x"10" after 120 ns,
            x"20" after 130 ns,
            x"10" after 150 ns,
            x"0A" after 160 ns,
            x"0B" after 170 ns,
            x"01" after 180 ns,
            x"25" after 190 ns,
            x"00" after 200 ns,
            x"0A" after 210 ns,
            x"00" after 230 ns,
            x"0A" after 240 ns,
            x"00" after 260 ns,
            x"0A" after 270 ns,
            x"00" after 290 ns;

local_B <= x"00",
            x"00" after 10 ns,
            x"82" after 20 ns,
            x"A0" after 30 ns,
            x"09" after 40 ns,
            x"04" after 50 ns,
            x"0B" after 60 ns,
            x"12" after 70 ns,
            x"0B" after 80 ns,
            x"00" after 90 ns,
            x"06" after 100 ns,
            x"07" after 110 ns,
            x"20" after 120 ns,
            x"10" after 130 ns,
            x"20" after 150 ns,
            x"0A" after 160 ns,
            x"02" after 170 ns,
            x"00" after 190 ns,
            x"0B" after 210 ns,
            x"00" after 220 ns,
            x"0B" after 240 ns,
            x"00" after 250 ns,
            x"0B" after 270 ns,
            x"00" after 280 ns;
      
           
end Behavioral;