---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15.05.2023 12:56:05 -- Design Name: -- Module Name: registers - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Registers is Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); Addr_B : in STD_LOGIC_VECTOR (3 downto 0); Addr_W : in STD_LOGIC_VECTOR (3 downto 0); W : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (7 downto 0); Rst : in STD_LOGIC; Clk : in STD_LOGIC; QA : out STD_LOGIC_VECTOR (7 downto 0); QB : out STD_LOGIC_VECTOR (7 downto 0)); end Registers; architecture Behavioral of Registers is type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0); signal Regs : Reg_array; begin process begin wait until clk'event and clk = '1'; if Rst = '0' then -- Reset Regs <= (others => x"00"); elsif W = '1' then -- Writing Regs(to_integer(unsigned(Addr_W))) <= Data; end if; end process; QA <= Regs(to_integer(unsigned(Addr_A))) when W = '0' or Addr_W /= Addr_A else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q QB <= Regs(to_integer(unsigned(Addr_B))) when W = '0' or Addr_W /= Addr_B else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q end Behavioral;