----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 15.05.2023 14:29:58
-- Design Name: 
-- Module Name: Pipeline - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Pipeline is
    Port ( Clk : in STD_LOGIC);
end Pipeline;

architecture Behavioral of Pipeline is
    
    signal IP : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal Rst : STD_LOGIC; -- to modify  
    
    component InstructionMemory
    Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
           Clk : in STD_LOGIC;
           Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
    end component;
    
    signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
    
    component Stage_Li_Di
    Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
           In_B : in STD_LOGIC_VECTOR (7 downto 0);
           In_C : in STD_LOGIC_VECTOR (7 downto 0);
           In_Op : in STD_LOGIC_VECTOR (7 downto 0);
           Clk : in STD_LOGIC;
           Out_A : out STD_LOGIC_VECTOR (7 downto 0);
           Out_B : out STD_LOGIC_VECTOR (7 downto 0);
           Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
           Out_C : out STD_LOGIC_VECTOR (7 downto 0)
         );
    end component;
    
    signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    
    component Registers
    Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
           Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
           Addr_W : in STD_LOGIC_VECTOR (3 downto 0);
           W : in STD_LOGIC;
           Data : in STD_LOGIC_VECTOR (7 downto 0);
           Rst : in STD_LOGIC;
           Clk : in STD_LOGIC;
           QA : out STD_LOGIC_VECTOR (7 downto 0);
           QB : out STD_LOGIC_VECTOR (7 downto 0)
         );
    end component;
    
    signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 
    
    component Stage_Di_Ex
    Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
           In_B : in STD_LOGIC_VECTOR (7 downto 0);
           In_C : in STD_LOGIC_VECTOR (7 downto 0);
           In_Op : in STD_LOGIC_VECTOR (7 downto 0);
           Clk : in STD_LOGIC;
           Out_A : out STD_LOGIC_VECTOR (7 downto 0);
           Out_B : out STD_LOGIC_VECTOR (7 downto 0);
           Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
           Out_C : out STD_LOGIC_VECTOR (7 downto 0)
         );
    end component;
    
    signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    
    component ALU
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div 
           S : out STD_LOGIC_VECTOR (7 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
    end component;
    
    signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC;
    
    component Stage_Ex_Mem
    Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
           In_B : in STD_LOGIC_VECTOR (7 downto 0);
           In_Op : in STD_LOGIC_VECTOR (7 downto 0);
           Clk : in STD_LOGIC;
           Out_A : out STD_LOGIC_VECTOR (7 downto 0);
           Out_B : out STD_LOGIC_VECTOR (7 downto 0);
           Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
      );
    end component;
    
    signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal Mem_RW : STD_LOGIC;
    signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    
    component DataMemory
    Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
           Data_in : in STD_LOGIC_VECTOR (7 downto 0);
           Rw : in STD_LOGIC;
           Rst : in STD_LOGIC;
           Clk : in STD_LOGIC;
           Data_out : out STD_LOGIC_VECTOR (7 downto 0));
    end component;
    
    component Stage_Mem_Re
    Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
           In_B : in STD_LOGIC_VECTOR (7 downto 0);
           In_Op : in STD_LOGIC_VECTOR (7 downto 0);
           Clk : in STD_LOGIC;
           Out_A : out STD_LOGIC_VECTOR (7 downto 0);
           Out_B : out STD_LOGIC_VECTOR (7 downto 0);
           Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
      );
    end component;
    
    signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal Re_W : STD_LOGIC;
    
begin

-- instructionMemory
MemInst : InstructionMemory PORT MAP (
    Addr => IP, 
    Clk => Clk,
    Inst_out => Li);

-- Stage_Li_Di
Stage1 : Stage_Li_Di PORT MAP (
    In_A => Li(23 downto 16),
    In_B => Li(15 downto 8),
    In_C => Li(7 downto 0),
    In_Op => Li(31 downto 24),
    Clk => Clk,
    Out_A => Di_A,
    Out_B => Di_B,
    Out_Op => Di_Op,
    Out_C => Di_C);
    
-- Registers
StageRegisters : Registers PORT MAP (
    Addr_A => Di_B,
    Addr_B => Di_C,
    Addr_W => Re_A,
    W => Re_W,
    Data => Re_B,
    Rst => Rst,
    Clk => Clk,
    QA => Di_RegB,
    QB => Di_C2);
    
-- Stage DI/EX
Stage2 : Stage_Di_Ex PORT MAP (
    In_A => Di_A,
    In_B => Di_FinalB,
    In_C => Di_C2,
    In_Op => Di_Op,
    Clk => Clk,
    Out_A => Ex_A,
    Out_B => Ex_B,
    Out_Op => Ex_Op,
    Out_C => Ex_C);
    
-- ALU
Ual : ALU PORT MAP (
    A => Ex_B,
    B => Ex_C,
    Ctrl_Alu => Ex_Ctrl_ALu,
    S => Ex_Res_Alu,
    N => S_NFlag,
    O => S_OFlag,
    Z => S_ZFlag,
    C => S_CFlag);
 
-- Stage Ex/Mem
Stage3 : Stage_Ex_Mem PORT MAP (
    In_A => Ex_A,
    In_B => Ex_FinalB,
    In_Op => Ex_Op,
    Clk => Clk,
    Out_A => Mem_A,
    Out_B => Mem_B,
    Out_Op => Mem_Op);   
 
-- DataMemory
DataMem : DataMemory PORT MAP (
    Addr => Mem_Addr,
    Data_in => Mem_B,
    Rw => Mem_RW,
    Rst => Rst,
    Clk => Clk,
    Data_out => Mem_Data_Out);
    
-- Stage Mem/RE
Stage4 : Stage_Mem_Re PORT MAP (
    In_A => Mem_A,
    In_B => Mem_FinalB, 
    In_Op => Mem_Op,
    Clk => Clk,
    Out_A => Re_A,
    Out_B => Re_B,
    Out_Op => Re_Op);

-- Instruction code
    -- ADD    00000001
    -- MUL    00000010
    -- SUB    00000011
    -- DIV    00000100
    -- COP    00000101
    -- AFC    00000110
    -- LOAD   00000111
    -- STORE  00001000


-- Mux post registers 
Di_FinalB <= Di_B when 
    Di_OP = "00000110" -- AFC
    else Di_RegB;
    
-- Mux post ALU
Ex_FinalB <= Ex_B when 
    Ex_Op = "00000110" --AFC
    or Ex_Op = "00000101" --COP
    or Ex_Op = "00000111" --LOAD
    or Ex_Op = "00001000" --STORE
    else Ex_Res_Alu;

-- LC pre ALU
Ex_Ctrl_ALu <= "000" when Ex_Op = "00000001" --ADD
    else "001" when Ex_Op = "00000011" -- SUB
    else "010" when Ex_Op = "00000010" -- MUL
    else "100" when Ex_Op = "00000100" -- DIV
    else "111"; --ERROR

-- Mux post data memory
Mem_FinalB <= Mem_B when 
    Mem_Op = "00000110" --AFC
    or Mem_Op = "00000101" --COP
    or Mem_Op = "00000001" --ADD
    or Mem_Op = "00000011" -- SUB
    or Mem_Op = "00000010" -- MUL
    or Mem_Op = "00000100" -- DIV
    else Mem_FinalB ; --LOAD & STORE

-- Mux pre data memory
Mem_Addr <= Mem_B when Mem_Op = "00000111" --LOAD
    else Mem_A; --STORE

-- LC pre data memory
Mem_RW <= '1' when Mem_Op = "00000111" --LOAD
    else '0'; --STORE
    
-- LC post Pip_Mem_Re
Re_W <= '0' when Re_Op = "00001000" --STORE
    else '1'; 


end Behavioral;