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-- Company: 
-- Engineer: 
-- 
-- Create Date: 15.05.2023 13:37:41
-- Design Name: 
-- Module Name: DataMemory - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DataMemory is
    Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
           Data_in : in STD_LOGIC_VECTOR (7 downto 0);
           Rw : in STD_LOGIC;
           Rst : in STD_LOGIC;
           Clk : in STD_LOGIC;
           Data_out : out STD_LOGIC_VECTOR (7 downto 0));
end DataMemory;

architecture Behavioral of DataMemory is
    type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
    signal Mem : Mem_array;
begin

    process
    begin
        wait until clk'event and clk = '1';
        if Rst = '0' then -- Reset
             mem <= (others => x"00");
        else if Rw = '1' then --reading
                 Data_out <= Mem(to_integer(unsigned(Addr)));
            else  -- writting
                Mem(to_integer(unsigned(Addr))) <= Data_in;
            end if;
        end if;
    end process;
        

end Behavioral;