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Added translation registers

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This commit is contained in:
alejeune 2023-05-12 15:43:03 +02:00
parent 360f3d29eb
commit f006ac975a
1 changed files with 37 additions and 2 deletions
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37
post-process.py
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@ -19,8 +19,43 @@ opToBinOP = {
def convertToRegister(s): def convertToRegister(s):
l = [] l = []
match s[0]: match s[0]:
case "ADD":
l.append("LOAD R0 "+s[2])
l.append("LOAD R1 "+s[3])
l.append("ADD R0 R0 R1")
l.append("STORE "+s[1]+" R0")
case "MUL":
l.append("LOAD R0 "+s[2])
l.append("LOAD R1 "+s[3])
l.append("MUL R0 R0 R1")
l.append("STORE "+s[1]+" R0")
case "SUB":
l.append("LOAD R0 "+s[2])
l.append("LOAD R1 "+s[3])
l.append("SUB R0 R0 R1")
l.append("STORE "+s[1]+" R0")
case "DIV_INT":
l.append("LOAD R0 "+s[2])
l.append("LOAD R1 "+s[3])
l.append("DIV R0 R0 R1")
l.append("STORE "+s[1]+" R0")
case "COP":
l.append("LOAD R0 "+s[2])
l.append("STORE "+s[1]+" R0")
case "AFC": case "AFC":
# TODO l.append("AFC R0 "+s[2])
l.append("STORE "+s[1]+" R0")
case "JMP":
pass
case "JMF":
pass
case "INF":
l.append("LOAD R0 "+s[2])
l.append("LOAD R1 "+s[3])
l.append("SUB R1 ")
return l
fileInput = open("asm", "r") fileInput = open("asm", "r")