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finished cross compiler for test

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Raphaël LACROIX 2023-05-29 23:43:29 +02:00
parent 8f5be60008
commit e621b754bf
1 changed files with 86 additions and 70 deletions
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152
post-process.py
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@ -1,98 +1,107 @@
import re
opToBinOP = {
"ADD": 1,
"MUL": 2,
"SUB": 3,
"DIV_INT": 4,
"COP": 5,
"AFC": 6,
"JMP": 7,
"JMF": 8,
"INF": 9,
"SUP": 10,
"EQ": 11,
"PRI": 12,
"AND": 13,
"OR": 14,
"NOT": 15
"ADD": "01",
"MUL": "02",
"SUB": "03",
"DIV": "04",
"COP": "05",
"AFC": "06",
"LOAD": "07",
"STORE": "08",
"INF": "09",
"SUP": "0A",
"EQ": "0B",
"NOT": "0C",
"AND": "0D",
"OR": "0E",
"JMP": "0F",
"JMF": "10",
"CAL": "11",
"RET": "12",
"PRI": "13",
"NOP": "FF"
}
def output(s):
fileOutput = open('asm2', 'w')
def output(s, num, oneline=False):
fileOutput = open(f'asm{num}', 'w')
if oneline:
fileOutput.write(s)
else :
fileOutput.write("\n".join(s))
fileOutput.close()
def convertToRegister(s):
# TODO check if there is a /\d_label/ in s[0] and if so adds it back at the start of the output
l = []
if not re.match(r"\d_LABEL .*", s[0]) :
if not re.match(r"\d_LABEL", s[0]):
optionalFlag = ""
incr = 0
op = s[0]
else:
optionalFlag = s[0] + " "
incr = 1
op = s[1]
match s[0]:
match op:
case "ADD":
l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("ADD R0 R0 R1")
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("ADD 0 0 1")
l.append("STORE " + s[1 + incr] + " 0")
case "MUL":
l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("MUL R0 R0 R1")
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("MUL 0 0 1")
l.append("STORE " + s[1 + incr] + " 0")
case "SUB":
l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("SUB R0 R0 R1")
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("SUB 0 0 1")
l.append("STORE " + s[1 + incr] + " 0")
case "DIV_INT":
l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("DIV R0 R0 R1")
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("DIV 0 0 1")
l.append("STORE " + s[1 + incr] + " 0")
case "COP":
l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("STORE " + s[1 + incr] + " 0")
case "AFC":
l.append(optionalFlag+"AFC R0 "+s[2+incr])
l.append("STORE "+s[1+incr]+" R0")
l.append(optionalFlag + "AFC 0 " + s[2 + incr])
l.append("STORE " + s[1 + incr] + " 0")
case "JMP":
pass
l.append(" ".join(s))
case "JMF":
pass
l.append(" ".join(s))
case "INF":
l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("INF R2 R0 R1")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("INF 2 0 1")
case "SUP":
l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("SUP R2 R1 R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("SUP 2 1 0")
case "EQ":
l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("EQ R2 R1 R0")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("EQ 2 1 0")
case "PRI":
l.append("PRI "+s[2+incr])
l.append(optionalFlag + "PRI " + s[2 + incr])
case "AND":
l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("AND R2 R0 R1")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("AND 2 0 1")
case "OR":
l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+incr])
l.append("OR R2 R0 R1")
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("OR 2 0 1")
case "NOT":
l.append("LOAD R0 "+s[2+incr])
l.append("NOT R2 R0")
""" R2 contiendra la valeur qui dit s'il faut sauter ou non """
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("NOT 2 0")
""" R2 will contain the information whether to jump or not"""
return l
@ -107,6 +116,7 @@ fileInput.close()
ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
ASMLinesFinal = [] # will contain the output, register-based, code
for i, l in enumerate(ASMLines):
items = l.split(" ")
if items[0] in ["JMP", "JMF"]:
@ -119,11 +129,11 @@ for i, l in enumerate(ASMLines):
ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo]
ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"])
labelCount += 1
print(ASMLinesLabel)
print("labels : ", ASMLinesLabel)
for i, l in enumerate(ASMLinesLabel):
ASMLinesRegister.extend(convertToRegister(l.split()))
print(ASMLinesRegister)
print("regs : ", ASMLinesRegister)
labels = {}
for i, l in enumerate(ASMLinesRegister):
@ -139,9 +149,15 @@ for i, l in enumerate(ASMLinesRegister):
else:
ASMLinesFinal.append(l)
print(ASMLinesFinal)
output(ASMLinesFinal, 2)
print(ASMLinesRegister)
output(ASMLinesFinal)
# - trucs en registre
# - décaler les Jumps
# - COP -> OPCode
lines = []
for i, l in enumerate(ASMLinesFinal):
arr = l.split()
while len(arr) < 4:
arr.append(0)
lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\")"
print("converted to VHDL-friendly format : " + ASMLinesConverted)
output(ASMLinesConverted, 3, True)