finished cross compiler for test
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Raphaël LACROIX
parent
8f5be60008
commit
e621b754bf
1 changed files with 86 additions and 70 deletions
156
post-process.py
156
post-process.py
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@ -1,98 +1,107 @@
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import re
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import re
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opToBinOP = {
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opToBinOP = {
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"ADD": 1,
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"ADD": "01",
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"MUL": 2,
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"MUL": "02",
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"SUB": 3,
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"SUB": "03",
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"DIV_INT": 4,
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"DIV": "04",
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"COP": 5,
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"COP": "05",
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"AFC": 6,
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"AFC": "06",
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"JMP": 7,
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"LOAD": "07",
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"JMF": 8,
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"STORE": "08",
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"INF": 9,
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"INF": "09",
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"SUP": 10,
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"SUP": "0A",
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"EQ": 11,
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"EQ": "0B",
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"PRI": 12,
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"NOT": "0C",
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"AND": 13,
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"AND": "0D",
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"OR": 14,
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"OR": "0E",
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"NOT": 15
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"JMP": "0F",
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"JMF": "10",
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"CAL": "11",
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"RET": "12",
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"PRI": "13",
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"NOP": "FF"
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}
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}
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def output(s):
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def output(s, num, oneline=False):
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fileOutput = open('asm2', 'w')
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fileOutput = open(f'asm{num}', 'w')
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fileOutput.write("\n".join(s))
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if oneline:
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fileOutput.write(s)
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else :
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fileOutput.write("\n".join(s))
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fileOutput.close()
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fileOutput.close()
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def convertToRegister(s):
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def convertToRegister(s):
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# TODO check if there is a /\d_label/ in s[0] and if so adds it back at the start of the output
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l = []
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l = []
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if not re.match(r"\d_LABEL .*", s[0]) :
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if not re.match(r"\d_LABEL", s[0]):
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optionalFlag = ""
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optionalFlag = ""
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incr = 0
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incr = 0
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op = s[0]
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else:
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else:
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optionalFlag = s[0] + " "
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optionalFlag = s[0] + " "
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incr = 1
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incr = 1
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op = s[1]
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match s[0]:
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match op:
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case "ADD":
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case "ADD":
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l.append(optionalFlag+"LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("ADD R0 R0 R1")
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l.append("ADD 0 0 1")
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "MUL":
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case "MUL":
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l.append(optionalFlag+"LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("MUL R0 R0 R1")
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l.append("MUL 0 0 1")
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "SUB":
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case "SUB":
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l.append(optionalFlag+"LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("SUB R0 R0 R1")
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l.append("SUB 0 0 1")
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "DIV_INT":
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case "DIV_INT":
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l.append(optionalFlag+"LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("DIV R0 R0 R1")
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l.append("DIV 0 0 1")
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "COP":
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case "COP":
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l.append(optionalFlag+"LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "AFC":
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case "AFC":
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l.append(optionalFlag+"AFC R0 "+s[2+incr])
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l.append(optionalFlag + "AFC 0 " + s[2 + incr])
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l.append("STORE "+s[1+incr]+" R0")
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l.append("STORE " + s[1 + incr] + " 0")
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case "JMP":
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case "JMP":
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pass
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l.append(" ".join(s))
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case "JMF":
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case "JMF":
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pass
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l.append(" ".join(s))
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case "INF":
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case "INF":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("INF R2 R0 R1")
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l.append("INF 2 0 1")
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case "SUP":
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case "SUP":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("SUP R2 R1 R0")
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l.append("SUP 2 1 0")
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case "EQ":
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case "EQ":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("EQ R2 R1 R0")
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l.append("EQ 2 1 0")
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case "PRI":
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case "PRI":
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l.append("PRI "+s[2+incr])
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l.append(optionalFlag + "PRI " + s[2 + incr])
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case "AND":
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case "AND":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("AND R2 R0 R1")
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l.append("AND 2 0 1")
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case "OR":
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case "OR":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD R1 "+s[3+incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("OR R2 R0 R1")
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l.append("OR 2 0 1")
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case "NOT":
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case "NOT":
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l.append("LOAD R0 "+s[2+incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("NOT R2 R0")
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l.append("NOT 2 0")
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""" R2 contiendra la valeur qui dit s'il faut sauter ou non """
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""" R2 will contain the information whether to jump or not"""
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return l
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return l
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@ -107,6 +116,7 @@ fileInput.close()
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ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
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ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
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ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
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ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
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ASMLinesFinal = [] # will contain the output, register-based, code
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ASMLinesFinal = [] # will contain the output, register-based, code
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for i, l in enumerate(ASMLines):
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for i, l in enumerate(ASMLines):
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items = l.split(" ")
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items = l.split(" ")
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if items[0] in ["JMP", "JMF"]:
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if items[0] in ["JMP", "JMF"]:
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@ -119,11 +129,11 @@ for i, l in enumerate(ASMLines):
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ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo]
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ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo]
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ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"])
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ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"])
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labelCount += 1
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labelCount += 1
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print(ASMLinesLabel)
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print("labels : ", ASMLinesLabel)
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for i, l in enumerate(ASMLinesLabel):
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for i, l in enumerate(ASMLinesLabel):
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ASMLinesRegister.extend(convertToRegister(l.split()))
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ASMLinesRegister.extend(convertToRegister(l.split()))
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print(ASMLinesRegister)
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print("regs : ", ASMLinesRegister)
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labels = {}
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labels = {}
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for i, l in enumerate(ASMLinesRegister):
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for i, l in enumerate(ASMLinesRegister):
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@ -136,12 +146,18 @@ for i, l in enumerate(ASMLinesRegister):
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label = re.match(r"\d_LABEL", l.split()[-1])
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label = re.match(r"\d_LABEL", l.split()[-1])
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if label:
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if label:
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ASMLinesFinal.append(" ".join(l.split()[:-1] + [str(labels[label[0]])]))
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ASMLinesFinal.append(" ".join(l.split()[:-1] + [str(labels[label[0]])]))
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else :
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else:
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ASMLinesFinal.append(l)
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ASMLinesFinal.append(l)
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print(ASMLinesFinal)
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output(ASMLinesFinal, 2)
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print(ASMLinesRegister)
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lines = []
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output(ASMLinesFinal)
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for i, l in enumerate(ASMLinesFinal):
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# - trucs en registre
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arr = l.split()
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# - décaler les Jumps
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while len(arr) < 4:
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# - COP -> OPCode
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arr.append(0)
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lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
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ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\")"
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print("converted to VHDL-friendly format : " + ASMLinesConverted)
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output(ASMLinesConverted, 3, True)
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