From 8a7685b049787fe8c9526ed0636b47cda3d38ecd Mon Sep 17 00:00:00 2001 From: Lacroix Raphael Date: Tue, 30 May 2023 08:46:35 +0200 Subject: [PATCH 1/3] xilinx generqted files --- VHDL/ALU/ALU.cache/wt/gui_handlers.wdf | 28 ++++++++------- .../ALU.cache/wt/java_command_handlers.wdf | 6 ++-- VHDL/ALU/ALU.cache/wt/webtalk_pa.xml | 32 ++++++++++-------- .../sim_1/behav/xsim/Test_total_behav.wdb | Bin 24275 -> 25317 bytes .../ALU/ALU.sim/sim_1/behav/xsim/simulate.log | 2 ++ .../webtalk/.xsim_webtallk.info | 2 +- .../Test_total_behav/webtalk/xsim_webtalk.tcl | 6 ++-- .../xsim.dir/Test_total_behav/xsimkernel.log | 3 ++ VHDL/ALU/Test_Alu_behav.wcfg | 12 +++---- 9 files changed, 50 insertions(+), 41 deletions(-) diff --git a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf index e28902b..80ffaa4 100644 --- a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf +++ b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf @@ -3,11 +3,12 @@ version:1 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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 -eof:900808538 +eof:1901464571 diff --git a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml index c5d8014..7389f3a 100644 --- a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml +++ b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -25,9 +25,9 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -39,11 +39,12 @@ This means code written to parse this file will need to be revisited each subseq - - + + + @@ -55,12 +56,12 @@ This means code written to parse this file will need to be revisited each subseq - + - - - + + + @@ -92,11 +93,11 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -104,18 +105,19 @@ This means code written to parse this file will need to be revisited each subseq + - + - + @@ -123,13 +125,13 @@ This means code written to parse this file will need to be revisited each subseq - + - + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb index df20a833fee7626f7f84bd39a5ca195062988038..b6ba277c6db2f784948f7f08eb3893dd477d492b 100644 GIT binary patch delta 1219 zcmcb-m+|RQ#tjvW%nnZcldBnZC*SAeV7eT)c@tx%E7Rk+&4TW7%#4?TR6nB-BLf4& zym}x31>52w(g(0hmnA@?AAqGn26Mr5h9yFz&SBT7k_3@H2-jK91l6hqr7IZUUfj!j z$Uva&;bFHwogH#gR%#Ajl7^g%12!^nx3ESuv;|7As()miziy#xRqT;{duRbZ0o-K&96_0$eXhyyM8D1y3Th7uh;#;o2V>ucbb0OsLx{dAJ_qMNm z`>^S>+28uCk5gYX{k4_dyMjZnLU!6RrCksHM9l1Zz+}13*R{m)_ZlD9g2sDKt}DmC zmH5J2q0qp<#6c|aXX^p>mS~A*KtElw=4&<(a1A_uZoT88<%yb_!JCdu(NR2IpI|wK zXWRUyMH?@V^nBtU=FM{HDO85KkwOxMLZcnbUT(kV^oA>rb`>t_*8vNz+ z)`|Py+}~3?@A;(HF=rniJ%8P8U(DZMKc786V3JVcShPPl=>F?JH(zgC*{Bt=&TXoV z>(i_&<$I;(75`qR$7GD+{(AiW`LLf!+H|jQ8psEyL9ya`G2!z`wvFkooKq44Sycnt zycfuvS|}3t$R={*8M%ellTxcqy3~#v^Qc~WYa*|Ay7tzlYb!*jT`27Pz3fTt_d4Fc zezTpqtry^ty=6t^=BJhLN{Ahzpq)LI_cW_Mc1bN z{8htawSJoa^T+1b_pVy}d#0cR10#z7kwhIw4a2`#qVquBapY@O5NJ(gF*SX8Xsh@K z7GE2`>9$_|PcA+FBH`B%u9SG&_jA3!Q-h%Uj|)3x`m1GhW<~$sR<`+B@r#R_y(`aN z&EGe7zO(iJjeDkQ6@GckzppLpp-oulU7@vW{~Z)8*>Y%#+a=>8B1!Akd$T6lvDB{# su6dXxyyx`(hIQYg)t|5bdb%oh_p5CCFL*MH6lVIf7qMVmnZ#cV0Bis0bN~PV delta 81 zcmaEQl=1Rj#tjvW6AL&dH!x~UED+qhlQGG4v%WhI^JWA06^u;t>NhL8OMy5`kU88S P5pL#5jDAQeRxknpu+tjU diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log index e69de29..2cc3412 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info index fce4d4a..60f0a1f 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ 1685389741 1685390103 -17 +18 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl index b938c76..065616b 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 00:45:27 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Tue May 30 00:50:26 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "16" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" @@ -28,5 +28,5 @@ webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "118556_KB" -context "xsim\\usage" -webtalk_transmit -clientid 2993264675 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_transmit -clientid 2174300005 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log index 7b9e937..2424516 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log @@ -2,3 +2,6 @@ Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb Design successfully loaded Design Loading Memory Usage: 32720 KB (Peak: 32772 KB) Design Loading CPU Usage: 60 ms +Simulation completed +Simulation Memory Usage: 118556 KB (Peak: 179992 KB) +Simulation CPU Usage: 60 ms diff --git a/VHDL/ALU/Test_Alu_behav.wcfg b/VHDL/ALU/Test_Alu_behav.wcfg index 8496043..62614dd 100644 --- a/VHDL/ALU/Test_Alu_behav.wcfg +++ b/VHDL/ALU/Test_Alu_behav.wcfg @@ -11,17 +11,17 @@ - - + + - - + + - - + + Clk From 576b41da4d5e3dfed85022e5648dba0fc0217885 Mon Sep 17 00:00:00 2001 From: Lacroix Raphael Date: Tue, 30 May 2023 13:38:05 +0200 Subject: [PATCH 2/3] fixed data path and aleas --- VHDL/ALU/ALU.cache/wt/gui_handlers.wdf | 97 +++-- .../ALU.cache/wt/java_command_handlers.wdf | 25 +- VHDL/ALU/ALU.cache/wt/project.wpc | 2 +- VHDL/ALU/ALU.cache/wt/synthesis.wdf | 8 +- VHDL/ALU/ALU.cache/wt/webtalk_pa.xml | 124 +++--- VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml | 5 + VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst | 2 +- VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp | Bin 21058 -> 3010 bytes VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl | 32 +- VHDL/ALU/ALU.runs/synth_1/Pipeline.vds | 192 ++++----- .../synth_1/Pipeline_utilization_synth.pb | Bin 276 -> 276 bytes .../synth_1/Pipeline_utilization_synth.rpt | 102 ++--- VHDL/ALU/ALU.runs/synth_1/gen_run.xml | 17 +- VHDL/ALU/ALU.runs/synth_1/project.wdf | 37 +- VHDL/ALU/ALU.runs/synth_1/runme.log | 182 ++++---- VHDL/ALU/ALU.runs/synth_1/runme.sh | 2 +- VHDL/ALU/ALU.runs/synth_1/vivado.jou | 10 +- VHDL/ALU/ALU.runs/synth_1/vivado.pb | Bin 81946 -> 80929 bytes .../ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl | 11 + .../sim_1/behav/xsim/Pipeline_behav.wdb | Bin 0 -> 26125 bytes .../sim_1/behav/xsim/Pipeline_vhdl.prj | 16 + .../ALU.sim/sim_1/behav/xsim/Test_total.tcl | 2 +- .../sim_1/behav/xsim/Test_total_behav.wdb | Bin 25317 -> 34063 bytes .../sim_1/behav/xsim/Test_total_vhdl.prj | 3 +- VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log | 119 ++++++ VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh | 2 +- .../ALU.sim/sim_1/behav/xsim/elaborate.log | 1 - .../ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh | 2 +- .../ALU/ALU.sim/sim_1/behav/xsim/simulate.log | 2 - VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh | 4 +- VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou | 14 +- VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log | 17 +- .../behav/xsim/webtalk_334386.backup.jou | 12 - .../behav/xsim/webtalk_334386.backup.log | 13 - .../behav/xsim/webtalk_509586.backup.jou | 12 + .../behav/xsim/webtalk_509586.backup.log | 14 + .../sim_1/behav/xsim/webtalk_5794.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_5794.backup.log | 13 + .../behav/xsim/webtalk_831173.backup.jou | 12 - .../behav/xsim/webtalk_831173.backup.log | 13 - VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb | Bin 1217 -> 921 bytes .../Pipeline_behav/Compile_Options.txt | 1 + .../Pipeline_behav/TempBreakPointFile.txt | 1 + .../Pipeline_behav/obj/xsim_0.lnx64.o | Bin 0 -> 48040 bytes .../xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c | 122 ++++++ .../Pipeline_behav/obj/xsim_1.lnx64.o | Bin 0 -> 5640 bytes .../webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 +++ .../webtalk/usage_statistics_ext_xsim.wdm | 38 ++ .../webtalk/usage_statistics_ext_xsim.xml | 44 ++ .../Pipeline_behav/webtalk/xsim_webtalk.tcl | 32 ++ .../xsim/xsim.dir/Pipeline_behav/xsim.dbg | Bin 0 -> 18108 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.mem | Bin 0 -> 5000 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.reloc | Bin 0 -> 2192 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.rlx | 12 + .../xsim/xsim.dir/Pipeline_behav/xsim.rtti | Bin 0 -> 592 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.svtype | Bin 0 -> 16 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.type | Bin 0 -> 7424 bytes .../xsim/xsim.dir/Pipeline_behav/xsim.xdbg | Bin 0 -> 79640 bytes .../xsim.dir/Pipeline_behav/xsimSettings.ini | 41 ++ .../xsim.dir/Pipeline_behav/xsimcrash.log | 0 .../behav/xsim/xsim.dir/Pipeline_behav/xsimk | Bin 0 -> 58112 bytes .../xsim.dir/Pipeline_behav/xsimkernel.log | 7 + .../Test_total_behav/obj/xsim_0.lnx64.o | Bin 44416 -> 50512 bytes .../xsim.dir/Test_total_behav/obj/xsim_1.c | 31 +- .../Test_total_behav/obj/xsim_1.lnx64.o | Bin 5512 -> 5712 bytes .../webtalk/.xsim_webtallk.info | 2 +- .../Test_total_behav/webtalk/xsim_webtalk.tcl | 22 +- .../xsim/xsim.dir/Test_total_behav/xsim.dbg | Bin 16892 -> 18436 bytes .../xsim/xsim.dir/Test_total_behav/xsim.mem | Bin 4892 -> 4966 bytes .../xsim/xsim.dir/Test_total_behav/xsim.reloc | Bin 1978 -> 2137 bytes .../xsim/xsim.dir/Test_total_behav/xsim.rlx | 2 +- .../xsim/xsim.dir/Test_total_behav/xsim.rtti | Bin 711 -> 711 bytes .../xsim/xsim.dir/Test_total_behav/xsim.xdbg | Bin 79456 -> 79656 bytes .../Test_total_behav/xsimSettings.ini | 2 +- .../xsim/xsim.dir/Test_total_behav/xsimk | Bin 53944 -> 58288 bytes .../xsim.dir/Test_total_behav/xsimkernel.log | 9 +- .../xsim.dir/xil_defaultlib/aleacontroler.vdb | Bin 0 -> 5211 bytes .../xsim/xsim.dir/xil_defaultlib/alu.vdb | Bin 9789 -> 9789 bytes .../xsim.dir/xil_defaultlib/datamemory.vdb | Bin 4136 -> 4253 bytes .../xil_defaultlib/instructionmemory.vdb | Bin 8800 -> 5645 bytes .../behav/xsim/xsim.dir/xil_defaultlib/ip.vdb | Bin 3608 -> 3608 bytes .../xsim/xsim.dir/xil_defaultlib/pipeline.vdb | Bin 30040 -> 30143 bytes .../xsim.dir/xil_defaultlib/registers.vdb | Bin 5762 -> 5862 bytes .../xsim.dir/xil_defaultlib/stage_di_ex.vdb | Bin 3387 -> 3387 bytes .../xsim.dir/xil_defaultlib/stage_ex_mem.vdb | Bin 2905 -> 2905 bytes .../xsim.dir/xil_defaultlib/stage_li_di.vdb | Bin 3387 -> 3387 bytes .../xsim.dir/xil_defaultlib/stage_mem_re.vdb | Bin 2905 -> 2905 bytes .../xsim.dir/xil_defaultlib/test_total.vdb | Bin 2029 -> 2484 bytes .../xil_defaultlib/xil_defaultlib.rlx | 23 +- VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd | 64 +++ .../ALU.srcs/sources_1/new/AleaControler.vhd | 62 +-- VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd | 4 +- .../sources_1/new/InstructionMemory.vhd | 13 +- VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd | 13 +- VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd | 60 ++- VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd | 4 +- VHDL/ALU/ALU.xpr | 19 +- VHDL/ALU/Test_Alu_behav.wcfg | 395 ++++++++++-------- 101 files changed, 1435 insertions(+), 787 deletions(-) create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_vhdl.prj delete mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou delete mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log delete mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou delete mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/.xsim_webtallk.info create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.dbg create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.mem create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.reloc create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rlx create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rtti create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.svtype create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.type create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.xdbg create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimSettings.ini create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimcrash.log create mode 100755 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimk create mode 100644 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100644 --- a/VHDL/ALU/ALU.cache/wt/synthesis.wdf +++ b/VHDL/ALU/ALU.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3239334d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436394d42:00:00 -eof:2352502396 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3238314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436314d42:00:00 +eof:428720552 diff --git a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml index 7389f3a..b8b518b 100644 --- a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml +++ b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,53 +17,65 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - - - - - - + + + + + + + + + + + + - - - - + + + + + + - + - + - + + + + + - + - + - - + + - + + @@ -73,11 +85,11 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -87,51 +99,61 @@ This means code written to parse this file will need to be revisited each subseq - - - - - + + + + + + - + + - - - + + + + + + - + - + - + + + + - + + - - - - - - + + + + + + + - - - - - - + + + + + + @@ -140,9 +162,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst b/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst index f28b9a6..60b7b62 100644 --- a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst +++ b/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp 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-in_memory -part xc7a35tcpg236-1 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt} [current_project] -set_property parent.project_path {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr} [current_project] +set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project] +set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] -set_property ip_output_repo {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip} [current_project] +set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_vhdl -library xil_defaultlib { - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd} - {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd} + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd + /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd } # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -50,8 +50,8 @@ read_vhdl -library xil_defaultlib { foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}} -set_property used_in_implementation false [get_files {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}}] +read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc +set_property used_in_implementation false [get_files /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] set_param ips.enableIPCacheLiteLoad 0 close [open __synthesis_is_running__ w] diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds b/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds index acca65e..0e8305f 100644 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds +++ b/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds @@ -2,12 +2,12 @@ # Vivado v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 00:39:32 2023 -# Process ID: 608313 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 +# Start of session at: Tue May 30 09:12:59 2023 +# Process ID: 10840 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou #----------------------------------------------------------- source Pipeline.tcl -notrace Command: synth_design -top Pipeline -part xc7a35tcpg236-1 @@ -15,44 +15,46 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 608386 +INFO: Helper process launched with PID 10853 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] -INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] -INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] -INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] -INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] -INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] -INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] -WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] -WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] +INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] +INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] +INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] +INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] +INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] +INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] +INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] +INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] +INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] +INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] +INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] +INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] +INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] +INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] +INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] +INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] +INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] +INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] +INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] +WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] +WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] +INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569 --------------------------------------------------------------------------------- Report Check Netlist: @@ -61,46 +63,46 @@ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ -WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] +WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) @@ -219,9 +221,9 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] +WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -327,8 +329,8 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] +WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] +WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. @@ -431,7 +433,7 @@ WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused an WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -443,13 +445,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 +Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -461,7 +463,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -485,7 +487,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- Report Check Netlist: @@ -498,7 +500,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -510,73 +512,55 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: -+------+--------------+----------+ -| |BlackBox name |Instances | -+------+--------------+----------+ -|1 |ControlUnit | 1| -+------+--------------+----------+ ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ Report Cell Usage: -+------+-------------------+------+ -| |Cell |Count | -+------+-------------------+------+ -|1 |ControlUnit_bbox_0 | 1| -|2 |BUFG | 1| -|3 |LUT1 | 2| -|4 |LUT2 | 14| -|5 |LUT3 | 2| -|6 |LUT4 | 2| -|7 |LUT5 | 4| -|8 |LUT6 | 15| -|9 |FDRE | 34| -|10 |FDSE | 13| -|11 |IBUF | 1| -+------+-------------------+------+ ++-+-----+------+ +| |Cell |Count | ++-+-----+------+ ++-+-----+------+ Report Instance Areas: -+------+-------------+------------------+------+ -| |Instance |Module |Cells | -+------+-------------+------------------+------+ -|1 |top | | 89| -|2 | MemInst |InstructionMemory | 17| -|3 | Stage1 |Stage_Li_Di | 11| -|4 | Stage2 |Stage_Di_Ex | 11| -|5 | inst_point |IP | 47| -+------+-------------+------------------+------+ ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 0| ++------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487 -Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498 +Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336 +Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: @@ -585,9 +569,9 @@ No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322 WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491 -INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023... +report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306 +INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb index 338d3903dbd9a96980b6e4f2b6f337e9192b54b5..a29faa5e62148053506e54b1ed307e0802e76f96 100644 GIT binary patch delta 96 zcmbQjG=*t`xeEisTwaC-CHJSi3_$Q!2t@7`W@uRC)+z#G_ez4uyFgORZK)K9y;dGX d{sod(oQ^7h*b}QY_<$l7K&I1COR&hsWB}om6oUW& delta 96 zcmbQjG=*t`xr>d{TwaC-CHJSiWl7I%-wH7>JaF7A%+RpNtyN_14NkjWNd_Re3nazd tmP&!xYvmaj8tnf9$tzAr6|$NN?I%`i@Bu|EfRau}Eg2X*942l|1^})49ee-) diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt index 53c488b..d935c8b 100644 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt +++ b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt @@ -1,12 +1,12 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Tue May 30 00:40:39 2023 -| Host : srv-tp04 running 64-bit Ubuntu 20.04.6 LTS +| Date : Tue May 30 09:13:39 2023 +| Host : insa-11267 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb | Design : Pipeline | Device : 7a35tcpg236-1 -| Design State : Synthesized +| Design State : Fully Placed ----------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -15,14 +15,15 @@ Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists 1. Slice Logic -------------- @@ -30,16 +31,15 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 28 | 0 | 20800 | 0.13 | -| LUT as Logic | 28 | 0 | 20800 | 0.13 | +| Slice LUTs | 0 | 0 | 20800 | 0.00 | +| LUT as Logic | 0 | 0 | 20800 | 0.00 | | LUT as Memory | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 47 | 0 | 41600 | 0.11 | -| Register as Flip Flop | 47 | 0 | 41600 | 0.11 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | | Register as Latch | 0 | 0 | 41600 | 0.00 | | F7 Muxes | 0 | 0 | 16300 | 0.00 | | F8 Muxes | 0 | 0 | 8150 | 0.00 | +-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type @@ -56,12 +56,31 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 13 | Yes | Set | - | -| 34 | Yes | Reset | - | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | +-------+--------------+-------------+--------------+ -2. Memory +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 0 | 0 | 8150 | 0.00 | +| SLICEL | 0 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 0 | 0 | 20800 | 0.00 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory --------- +----------------+------+-------+-----------+-------+ @@ -74,7 +93,7 @@ Table of Contents * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 -3. DSP +4. DSP ------ +-----------+------+-------+-----------+-------+ @@ -84,13 +103,13 @@ Table of Contents +-----------+------+-------+-----------+-------+ -4. IO and GT Specific +5. IO and GT Specific --------------------- +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 1 | 0 | 106 | 0.94 | +| Bonded IOB | 0 | 0 | 106 | 0.00 | | Bonded IPADs | 0 | 0 | 10 | 0.00 | | Bonded OPADs | 0 | 0 | 4 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | @@ -109,13 +128,13 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ -5. Clocking +6. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFGCTRL | 0 | 0 | 32 | 0.00 | | BUFIO | 0 | 0 | 20 | 0.00 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 | @@ -125,7 +144,7 @@ Table of Contents +------------+------+-------+-----------+-------+ -6. Specific Feature +7. Specific Feature ------------------- +-------------+------+-------+-----------+-------+ @@ -143,38 +162,25 @@ Table of Contents +-------------+------+-------+-----------+-------+ -7. Primitives +8. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 34 | Flop & Latch | -| LUT6 | 15 | LUT | -| LUT2 | 14 | LUT | -| FDSE | 13 | Flop & Latch | -| LUT5 | 4 | LUT | -| LUT4 | 2 | LUT | -| LUT3 | 2 | LUT | -| LUT1 | 2 | LUT | -| IBUF | 1 | IO | -| BUFG | 1 | Clock | -+----------+------+---------------------+ -8. Black Boxes +9. Black Boxes -------------- -+-------------+------+ -| Ref Name | Used | -+-------------+------+ -| ControlUnit | 1 | -+-------------+------+ - - -9. Instantiated Netlists ------------------------- - ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + +----------+------+ | Ref Name | Used | +----------+------+ diff --git a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml index 5fe2340..43a1ea5 100644 --- a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml +++ b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - + + + + - - - - @@ -17,6 +14,12 @@ + + + + + + diff --git a/VHDL/ALU/ALU.runs/synth_1/project.wdf b/VHDL/ALU/ALU.runs/synth_1/project.wdf index 03ad16a..44c1bc3 100644 --- a/VHDL/ALU/ALU.runs/synth_1/project.wdf +++ b/VHDL/ALU/ALU.runs/synth_1/project.wdf @@ -1,5 +1,5 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 @@ -13,7 +13,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3830:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3836:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 @@ -28,35 +28,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7072696d6172795f636c6f636b73:31:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7072696d6172795f636c6f636b73:31:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f67656e6572617465645f636c6f636b73:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f67656e6572617465645f636c6f636b73:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f666f727761726465645f636c6f636b73:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f666f727761726465645f636c6f636b73:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f65787465726e616c5f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f65787465726e616c5f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f696e7075745f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f696e7075745f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6f75747075745f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6f75747075745f64656c617973:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f636f6d62696e6174696f6e616c5f7061746873:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f636f6d62696e6174696f6e616c5f7061746873:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6173796e635f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6173796e635f636c6f636b5f67726f757073:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f66616c73655f7061746873:30:00:00 -74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f66616c73655f7061746873:30:00:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636865636b73:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:706f73745f77697a617264:00:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726d6174:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6661696c5f6f6e:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72657475726e5f737472696e67:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d65737361676573:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726365:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d776169766564:64656661756c74:5b6e6f745f7370656369666965645d:00 -7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617070656e64:64656661756c74:5b6e6f745f7370656369666965645d:00 -eof:2501282044 +eof:3805747332 diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.log b/VHDL/ALU/ALU.runs/synth_1/runme.log index 93ab5ce..3e75e98 100644 --- a/VHDL/ALU/ALU.runs/synth_1/runme.log +++ b/VHDL/ALU/ALU.runs/synth_1/runme.log @@ -14,44 +14,46 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 608386 +INFO: Helper process launched with PID 10853 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] -INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] -INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] -INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] -INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] -INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] -INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] -WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] -WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] +INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] +INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] +INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] +INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] +INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] +INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] +INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] +INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] +INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] +INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] +INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] +INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] +INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] +INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] +INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] +INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] +INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] +INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] +INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] +WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] +WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] +INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569 --------------------------------------------------------------------------------- Report Check Netlist: @@ -60,46 +62,46 @@ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ -WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] +WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) @@ -218,9 +220,9 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] +WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -326,8 +328,8 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] +WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] +WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. @@ -430,7 +432,7 @@ WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused an WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -442,13 +444,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 +Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -460,7 +462,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433 +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -484,7 +486,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- Report Check Netlist: @@ -497,7 +499,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -509,73 +511,55 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: -+------+--------------+----------+ -| |BlackBox name |Instances | -+------+--------------+----------+ -|1 |ControlUnit | 1| -+------+--------------+----------+ ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ Report Cell Usage: -+------+-------------------+------+ -| |Cell |Count | -+------+-------------------+------+ -|1 |ControlUnit_bbox_0 | 1| -|2 |BUFG | 1| -|3 |LUT1 | 2| -|4 |LUT2 | 14| -|5 |LUT3 | 2| -|6 |LUT4 | 2| -|7 |LUT5 | 4| -|8 |LUT6 | 15| -|9 |FDRE | 34| -|10 |FDSE | 13| -|11 |IBUF | 1| -+------+-------------------+------+ ++-+-----+------+ +| |Cell |Count | ++-+-----+------+ ++-+-----+------+ Report Instance Areas: -+------+-------------+------------------+------+ -| |Instance |Module |Cells | -+------+-------------+------------------+------+ -|1 |top | | 89| -|2 | MemInst |InstructionMemory | 17| -|3 | Stage1 |Stage_Li_Di | 11| -|4 | Stage2 |Stage_Di_Ex | 11| -|5 | inst_point |IP | 47| -+------+-------------+------------------+------+ ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 0| ++------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487 -Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498 +Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336 +Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: @@ -584,9 +568,9 @@ No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322 WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491 -INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023... +report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306 +INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.sh b/VHDL/ALU/ALU.runs/synth_1/runme.sh index 3a75b33..ae5d7fd 100755 --- a/VHDL/ALU/ALU.runs/synth_1/runme.sh +++ b/VHDL/ALU/ALU.runs/synth_1/runme.sh @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1' +HD_PWD='/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.jou b/VHDL/ALU/ALU.runs/synth_1/vivado.jou index b72c97e..6074572 100644 --- a/VHDL/ALU/ALU.runs/synth_1/vivado.jou +++ b/VHDL/ALU/ALU.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 00:39:32 2023 -# Process ID: 608313 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 +# Start of session at: Tue May 30 09:12:59 2023 +# Process ID: 10840 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou #----------------------------------------------------------- source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.pb b/VHDL/ALU/ALU.runs/synth_1/vivado.pb index d2a131a550a6c6d09a545268b5744f1669020583..d51d0f6ac2ff16cfd72d79bfecedd60b7e1d620e 100644 GIT binary patch delta 3544 zcmb_edrVVj6wkSo*F|1!0f9nqK~yM~dwYA^ULHcl=M-dfZful!wa_w#hPQ z#LZ35lF#UTP7}>Ua81@_(+o0M+>(Xi+)L4o#K+t+vp<%&IivgTZ9yqj7KJq7dz|z8 zoqN9X+Oa-#-`|?iF~!07Hsd^UQRWO2-{k#iGv>1N>Tv4=;Uq^tUUaf)0!TZ$dJXi8?r3-NAx(reqO z8hKV*KXU)i$g0%O?Z%Z!lkwL{8T3Z6fk{MFw+3$|zUM#7N-o9kCnXKlx zNjag-FEzB(SWf_Z2s`pblo(5*D2NuP?7WkJg3W3X$p8Zh2AY7pJ!k^jWi-h~&l0{c z#BaiN@k^REy|!#6ZIrj`&ottEDHf-7zUF<}1WSReF+w`7bK1t^RTJM9l-J?md(R}o+k~35D8B85tf#uh9|S3l0%ZPYLPC|N;h^{6lC1GP>+X8-X*gb>WF7tdBFQ> zp_Qk#Fiqza?!1D;3l<0OQ0kyYa@gsEgo93jk?kIs)z9dE3vj^zu*dP@?0FA}X_7Mm zyWiG&ewbSU`fCB;-vQf$1@jj^7&r};eV*M5ZWj9^Bc!A2UN30ED;=rBEyAj_h)0Ec1ks0j4vFo_ssmT zXI|Rx0bhL@*b^|fwxPDU#$Am)omp6NBLzhNn@Qst$IC&DbI8;zA_YAWbR zY$8OG)+9)NXm~Xgy)+ab2l7W2aO5!qO(WkUKe*8zHDOEkYQ1^s;0j(52~34FvX55X ziJ==^#>I&N-8Nh6?VJK7fJH9V_Y>$FLVXiPu1$kml!e5Hf`M=>aC8H0q&(frr$^N9#`+=L94D@R;P}hUS*4hUeT|TUlduYrUK7;bHoH!K^{R1Rq#S;~GD#?;q!5 z;qlR%-2E{32d(KuV}pW+jua(D$r?Rq$!ZA-LPSv@ha||>5BiG2h{HYy_9(d|fjrzo z1cy>aMLQ0a8ujM`@J|BUMNZj4#;0!38a;0MI{2XIbSR|gWV-|A zVp!o~uSSN~8Ms8piwz{E5N0rRR%rhyF~T=vP#U@k7witvVpT^B@+O@&lvyLfKWA8R zNK6P*#sk_jeN%>({8b1i)d_|tSBv1B=2N9&o|;K3CS-y>l;GH64U W#Nh7W?WD07R%_&ZK_uskq3A!Be-)oNsy}lJEZ2b1H7Bbo+w{r9vDD-Id0^gzZK=>? zDiYg^@9;b7cu{on9uM2Y?hQp^?1QXVaC%)nJT_FT=UiU5kAwuME#U;OM-tv{=__LcliYxUyq?FRf)>FcV+P`L(w=Wt?G z`GkgR#t+I*Y5l{pLSw~@X8E_;idPwM=c=#g;YL@#qV)~PIG5RvXI7i>x*@3b+?HE6 z)aRhB8Bf=oke`Bhy!NKn>XLnpREF`fIx~J;=}-~zs*)E?m%T3?b>ha3D_ZL_!auB90VLaMej}_Kj5bm~CVOvXXvZWwe zTfd{C@3!96T7we4epbhbauSAPvAd$7iG91`hp?)wsk*33@U-dUq2%EtZ(?+T zF|?P~uC_51fp{!68IO*|A}M_8o1#jZ(67TI?Twf)=)r??&RmS8jQmgM745C{=;5Bj zHO`GV=gqmTWUb5i+k)D-0L*Ee@7C>T>N}_aBkk|7Ti*OSmgTf z(!M>D;V^qJGMPFMiqaC2iv`&MHuGhnw@7oQ9}`{!j(U_t3!svAHflYkz9U&KH%S%) zj!ZqB+1Nb>WVivW`am%#*PXGyxv%vEtVr zmUB?bSb=jd?x05wM4pG|ehiO-@vjAXSAcn&bn0M}j+b+~7DVy~2UwTN5h*B~XK_up zkYNYbL6#|oQNZzjD>jnN_1m=6>5e7uy zUzQi3WxZcs1#<5KGfTGHp!fbn=t4kCHZfB}ZnZ&4)^DfvBUKbR z;Q;RbD6{@1IHa3jsqc?Pag5zulRei0eL(tbz>-%SP)*iv0L$m$q=U`U!4?CKeyavH z9tWr;GwskJJ(i?d=|i@)L(d}J_B1E=r}H*qYEVE@4@a(cKpozgE-yfnwhkDm4c>bI z^)l-ed7BwZ@P@mL+;UR%1zmaj!Z%fsbRZm!%1&rsyG*VEIBV*eY^?A60CsZvem4>MkZ`mPYDkcWo+94IljnKZVEjqjUN+bOlFlQxF--@>xUeE}AUWt%A>4w3F!c2!h z7K$F0uXxQ#mR{VFk^O8q8r~m{rIPHP_#`_SPSCrbY+$PN4LZ)#RvHVZqLCy{SC~zY z>Um!W=Xv~rg#M6z8Xl<9F;6f&e&{!~O~m&nqTy6{H=Q?@vIl}=Y%)9%kL^y%OuRS8 zMCQ7{Tq;xXUbH^EGiwmx86EtE-a(!v^yTMqlUQ8&H-DHyf8RGVFc>56}`MVc>BcG66^p(a 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..3907a605843c64a7ca7c009abb60ee84b364d8cc GIT binary patch literal 26125 zcmeI43v^Z0na2;vs{?4n_me2EfRLMn0KuZ<<{b!0NCHHpUM|U%Tu5@mO)dtHDBj)QfaqE1I@R~?qh5{gt-TUHeW=KnwE+hOx1_mqwZ zj^Mxyxvi7*B8KlU z>m%i|zNJ{;)SBBW3sZ|q%dqfR`92#T!`gBfDZL$M8Z?HsvAU)pR8~=3n(rXf4Yd51 z5Jt@!<&3ID$Uw+Mn2Rt6p$wq}VcaN(opXUqOS3*%Q>kdGF9uZ}teI66EOUp0Ea&9O zlPlO&5Fy1LbZB;AeoaM{3-)q0y5k|pxlkK9ffm*yq#}bIl$O^N78iQ;kkw&2C_;iA z%!o9F!tr=`S!c_%3R~oDz}6`z5tuiW2?$zodoit4MHZexEA$h#(w|L0bSr<_Sad6J zBUj9g{v%2MO7!(&rdvhdC;F$N#hK`sTrz_p=p*u8M+#fzKrEZq>BN%$83_;BJ0b95cf%+=ZP;NQ<94&dz zNZu$(L%DS>hlVNK_zr0LT2RtZZa(*rY>7Vy-3OsY(ok-lE1_?ZyjP$(-X=*yx$Rs7 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z&F!B&l-@D&?_CysxwGiX)-`JiRt)X(79zw3~m;1MV`1>J!ZfM_oU8wim_8CP@ z{iX9x|K#R{ua(yAoiab~e{Oxh^_!FX-SYX&yU*VIbmxa}9{l@PwruflJh1DXo5uE- zH#L1g(u@bcDx2`;7tdW?b>M+LTVE*6c<}xKA7rmu>%IOrGv3U;=e4<=Zf*8Vua@mM z%*`47RR3$fxOPdm+umLFz`J*T^X;{*FI#qJ!H$nF-Ms2ge>m{FcA2J0^MqqOT;J+i z^WEKN-HWSnpK(KC!Y_Tz`}Y0p#b?gh(|p9`BY!(^*e#!I`gmW*k#%Fc`u;v*Z$VaF zyCGk1{PTIYTytLUyC)o8G4rYI;hk?iHGKAlcY>?$xi5Rb;pNZY(d(*xyW6gwKYiQf zV{ZDe{o{{+_d>hK(=RT{-IVt7nUj|;8{T5_pyqQPE53Hy^bXIjUsJbq|Ag*4mVLGU b>MNf6uNi~)9rLY%TWau`8BHFU+&28bZ+!If diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj index 7b9f8b6..bfcc4c8 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj @@ -1,6 +1,7 @@ # compile vhdl design source files vhdl xil_defaultlib \ "../../../../ALU.srcs/sources_1/new/ALU.vhd" \ +"../../../../ALU.srcs/sources_1/new/AleaControler.vhd" \ "../../../../ALU.srcs/sources_1/new/IP.vhd" \ "../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \ "../../../../ALU.srcs/sources_1/new/Memory.vhd" \ @@ -10,7 +11,7 @@ vhdl xil_defaultlib \ "../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \ "../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \ "../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \ -"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ +"../../../../ALU.srcs/sim_1/new/test_total.vhd" \ # Do not sort compile order nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log index a0c4a5f..018949d 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log @@ -217,3 +217,122 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Pro INFO: [VRFC 10-307] analyzing entity Test_total INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity IP +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Li_Di +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity IP +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +ERROR: [VRFC 10-825] illegal identifier : __En [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:38] +ERROR: [VRFC 10-1504] unit instructionmemory ignored due to previous errors [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35] +INFO: [VRFC 10-240] VHDL file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd ignored due to errors +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity DataMemory diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh index 97b5f55..f6b7d78 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Tue May 30 00:45:29 CEST 2023 +# Generated by Vivado on Tue May 30 13:26:07 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log index 26a61eb..93de205 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log @@ -3,6 +3,5 @@ Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log Using 8 slave threads. Starting static elaboration -WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh index ad71e04..d9fe5f4 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Tue May 30 00:45:30 CEST 2023 +# Generated by Vivado on Tue May 30 13:26:09 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log index 2cc3412..e69de29 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log @@ -1,2 +0,0 @@ -Vivado Simulator 2018.2 -Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh index 9bb1cfd..5640af2 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Tue May 30 00:45:32 CEST 2023 +# Generated by Vivado on Tue May 30 13:26:10 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. @@ -23,4 +23,4 @@ then exit $RETVAL fi } -ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log +ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou index ad71808..00a9a20 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:55:04 2023 -# Process ID: 509586 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +# Start of session at: Tue May 30 08:48:34 2023 +# Process ID: 5876 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou #----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log index 57760b0..1837e58 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log @@ -2,13 +2,12 @@ # Webtalk v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:55:04 2023 -# Process ID: 509586 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +# Start of session at: Tue May 30 08:48:34 2023 +# Process ID: 5876 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou #----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace -couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory -INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023... +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:35 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou deleted file mode 100644 index 1b48663..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 19:26:30 2023 -# Process ID: 334386 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log deleted file mode 100644 index f578386..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 19:26:30 2023 -# Process ID: 334386 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:26:31 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou new file mode 100644 index 0000000..ad71808 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon May 29 21:55:04 2023 +# Process ID: 509586 +# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log new file mode 100644 index 0000000..57760b0 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon May 29 21:55:04 2023 +# Process ID: 509586 +# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst -notrace +couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory +INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou new file mode 100644 index 0000000..7a74134 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue May 30 08:48:10 2023 +# Process ID: 5794 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log new file mode 100644 index 0000000..a9563c6 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue May 30 08:48:10 2023 +# Process ID: 5794 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:11 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou deleted file mode 100644 index ad264ba..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Sun May 14 22:27:00 2023 -# Process ID: 831173 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log deleted file mode 100644 index 5c88519..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Sun May 14 22:27:00 2023 -# Process ID: 831173 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:01 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb index e8e73cf8fe3f43fc776d4c0f435824de4aa2eba1..3020a605746522398d5b8ad178fe1fecb6ca2ca2 100644 GIT binary patch delta 11 TcmX@eIg@?E1*XYAm`?%#9tH(O delta 304 zcmZvXu};H45Ja&fIl^h&Lc}WKcJ%K z2lxeA8u%nkK?TJ~qc_FOy!78!-@d}-YZ&iuv9Qo+Bo> zIZ}yqD}WrjMG~#|GNrZ$En_nWi&HGrMm#7CIcsW9=v2RisrI!y`Zek)h)Gta0cpD) zYnIr`k+-0|+(RpQ!A>Aejht9>2QIzn05rhqc?WHy9X@zqd3AO=mM7!O9}U?SEZKNl z0N-Si;89L+1~n24=T(^m|Lj{2f=Z09c4Rd_pVx*MQ!x_5q^FHQuk$= diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt new file mode 100644 index 0000000..6314351 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Pipeline_behav" "xil_defaultlib.Pipeline" -log "elaborate.log" diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..c6458fd5ea999ae4b3cf72ab58c9075460f9dd14 GIT binary patch literal 48040 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a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c new file mode 100644 index 0000000..892e97c --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c @@ -0,0 +1,122 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern void execute_76(char*, char *); +extern void execute_77(char*, char *); +extern void execute_78(char*, char *); +extern void execute_79(char*, char *); +extern void execute_80(char*, char *); +extern void execute_81(char*, char *); +extern void execute_82(char*, char *); +extern void execute_87(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_58(char*, char *); +extern void execute_60(char*, char *); +extern void execute_62(char*, char *); +extern void execute_63(char*, char *); +extern void execute_64(char*, char *); +extern void execute_66(char*, char *); +extern void execute_68(char*, char *); +extern void execute_69(char*, char *); +extern void execute_71(char*, char *); +extern void execute_73(char*, char *); +extern void execute_75(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_86(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[26] = {(funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_87, (funcp)execute_51, (funcp)execute_52, (funcp)execute_58, (funcp)execute_60, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_66, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 26; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/Pipeline_behav/xsim.reloc", (void **)funcTab, 26); + iki_vhdl_file_variable_register(dp + 24592); + iki_vhdl_file_variable_register(dp + 24648); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/Pipeline_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/Pipeline_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/Pipeline_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/Pipeline_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/Pipeline_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..dbb268f8aa6330de0f327233e98ddd26d59ee133 GIT binary patch literal 5640 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XSIM Usage Report


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software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedTue May 30 08:48:33 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration2random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
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os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram67.000 GBtotal_processors1

+ + +
vivado_usage

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xsim
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command_line_options
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usage
iteration=0runtime=1 ussimulation_memory=118556_KBsimulation_time=0.01_sec
trace_waveform=true
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+ + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..539a45a --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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XSIM Usage Report


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ziRL`cD;MLVWOHdeVNP-^69r`zbtR8;K^aGi9A4(Lo}3OYYj}Pa*JbpS47#ceOTA24 ztf@N6yxLatNO9d~&EZ(hkcnter#!O3OF>5y@(^pqL;Rg=Cf#~dm|2eC)n*aa+ delta 613 zcmYk2&r2Io5XX1cm|woFZ#S;HDWwJpRH?d+HE!A(5>NF|DLoW=38j>vV0sV~a?nC< z>7fw$UOZKA=Ah8Br35@QRw(4wLyt;N1^Wl|R_@y6s3$_ze{&O z(GtyIp8a<;q9yfQ#VQS>9FO26nk5AkE72I{*|*S$l@c-@2<)O4bCd72;PylHlJQSO zhd4^y;!(d6OVq;);dsl*452M-bOzdJ3ES%m2F(GR-r-5o^5nHW;th7BDO{ymufAMg zt3G!NI36t9`P>!BPybH~$jOYjdj)1^P?00*>^;1eqd1a}F{l?Qheh2=7kIxv=fUxF z|3ugd*wh`&83G+WOVc>jEpqT%f5?AQG#u>f0(B#cM;zPys>aqeYBYt(l$Fl2!lmj6 z`I>>Mi%QDUCIj%#$FXHv*iL;U8;e60Him@u?4s^BUdJZWeWuGHdIJYcPngz2^d?T3 q3R7s!5Y0g233E)hLv$2HrZuMR5Y6J1X{GO95I=N6)d%=#uKWd*h?GYF diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info index 60f0a1f..219c3be 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ 1685389741 1685390103 -18 +104 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl index 065616b..6c5c8cc 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ -webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ +webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 00:50:26 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:40 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "103" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "900.000 MHz" -context "user_environment" -webtalk_add_data -client project -key total_processors -value "2" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2757.340 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "118556_KB" -context "xsim\\usage" -webtalk_transmit -clientid 2174300005 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "122660_KB" -context "xsim\\usage" +webtalk_transmit -clientid 653659988 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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zKX8jrG>lJ#7@XLEgHN28KM~^iM3ab5-hB{0emTJSh%(WnN5)Q0j(6jmpn6ZgvCu0Z z??xyBzge&uiiR^3A(l{Vz{yaYI71QQ*J05lX1Ezgr9$|nhs{tl^}OmmH^VJX1b$;; zBZ#K%SMRwIAEX+X8WVlP|HH2hp3Cuuf+O E0JIVlo&W#< diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb index afa0fab805bb4a3902b5c00b410f60c11a8178c0..586ab08d5d9c0f3c52f5fa8e0cc7642dddeea8de 100644 GIT binary patch delta 52 zcmca9c2i7LC`X=|lYwCY0}wbosgh^rP@hveQFI=o!^SO#nVEr{$yF@pLG)%HR$ev$ DeRU67 delta 52 zcmca9c2i7LC`X=|lYwCY0}wbosgh^rxc0kbqUb!vrj1(;GcyA@ldD+HgXqmZth{Uh Dxw{g> diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb index 4a478b3bc85013db7abc00a735ee32c904da390c..ed7918a1bf26306112478bed4a3cfb6e30f838ff 100644 GIT binary patch delta 52 zcmdljwOdM5C`X=|lYwCY0}wbosgh^rP@hveQFIQY?Z!>AEX+X8WVlP|HH2hp3Cuuf+O E0JIVlo&W#< diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb index 08522d2ad6a56da6c89cd8941b97acb3a245811e..985dcffe9780b98648fd9d76e19001ffb3b044bc 100644 GIT binary patch delta 52 zcmca9c2i7LC`X=|lYwCY0}wbosgh^rP@hveQFI=o!^SO#nVEr{$yF@pLG)%HR$ev$ DeRU67 delta 52 zcmca9c2i7LC`X=|lYwCY0}wbosgh^rxc0kbqUb!vrj1(;GcyA@ldD+HgXqmZth{Uh Dxw{g> diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb index 2f523d1b13c6dbeffa4cf11926380be6d15b1cc2..4b2fd1823d775d5d4baa9ca2dc50bd011120f465 100644 GIT binary patch delta 896 zcmZ`&Jx^3Y6rGR9?!H)TTsIg|gVkz?zy={~K+Tm%A{I*lzhFZ_Vdw}6fjmA!tjWaK zDIW=;pa295K9pFgl|7xY^#|B_&iH0|g!r;E`|dsGo;!2zeZPwbH_D|~?KW0wP2rJW zv+cGpbF^B1t7UIz&X}1a*I{4kyqmT?_l-;`b=Co*#MyslF+qPOT za?k?rp*y#CwQ+y!P)XV{(a->REvhoblW0<(xUHxwc>qfH{}aeLQ}u)NC?%PC!_@cb zeVFmeXC#MjA>%8Ij1JdF8pDm|i|mtS+tu{g9?3aH!5F0^c%cJNXT~G*8Dj!8K3*-vn8{K6f!gp$XZzh-AfB#$K>~ YtX7cp)e1%r^78TL4bIEeBFfM1FCaUiQ~&?~ delta 532 zcmdlY{FYxtC`X=|lYwCY0}wbosgh^rXj7OdGM%w$KrZ$DiTFhRIY?DiwjTjjx zpJO&qWOUfV3Q}9iz;Hkl$Y2EP+zb?R*aVVboUFp)1k$*QC4+J2WMNi4eRH5vBdAg) zza%EVO+b!=4w9(DZje?6hX#)u(ZEpl&utQK}SX&!= z+Z!RI!!EEh!ESN@xxj3)C!0 rst, + Clk => clock + ); + + Clock_process : process + begin + clock <= not(clock); + wait for 100ns; + end process; + + rst <= '0' after 50ns; + +end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd index 2bfe6a4..22d8155 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd @@ -25,43 +25,49 @@ use IEEE.STD_LOGIC_UNSIGNED.all; -- we freeze IP on the current instruction -- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish -entity ControlUnit is +entity AleaControler is Port ( -- get the current op and variables from the 3 pipelines stages that can interract - Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0); - A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0); + Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0); + A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0); B_DI : in STD_LOGIC_VECTOR (7 downto 0); C_DI : in STD_LOGIC_VECTOR (7 downto 0); CNTRL : out STD_LOGIC); -end ControlUnit; +end AleaControler; -architecture Behavioral of ControlUnit is - signal alea_DI_EX or alea_DI_MEM: STD_LOGIC; +architecture Behavioral of AleaControler is + signal alea_DI_EX, alea_DI_MEM: STD_LOGIC; signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC; begin - CNTRL <= alea_DI_EX or alea_DI_MEM; -- either a problem between the 1st and 2nd or 1st and 3rd + CNTRL <= -- either a problem between the 1st and 2nd or 1st and 3rd + '1' when + -- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read) + ( + -- check Op1 & Op2 + ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_EX /= x"08" and Op_EX /= x"ff")) and + + -- check Registers are the same + ((A_Ex = B_DI) or (A_EX = C_DI)) + ) or + + -- read after write : Op1 other than STORE/NOP, op3 other than AFC/NOP, R(write) = R(read) + ( + -- check Op1 & Op2 + ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Mem /= x"08" and Op_Mem /= x"ff")) and + + -- check Registers are the same + ((A_Mem = B_DI) or (A_Mem = C_DI)) + ) or + + -- read after write : Op1 other than STORE/NOP, op4 other than AFC/NOP, R(write) = R(read) + ( + -- check Op1 & Op2 + ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Re /= x"08" and Op_Re /= x"ff")) and - alea_DI_EX <= '1' when - -- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read) - ( - -- check Op1 & Op2 - (OP_DI != x"08" or OP_DI != x"ff") and (Op_EX != x"06" Op_EX != x"ff") and - - -- check Registers are the same - (A_Ex = B_DI) or (A_EX = C_DI) - ) - else '0'; - - alea_DI_Mem <= '1' when - -- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read) - ( - -- check Op1 & Op2 - (OP_DI != x"08" or OP_DI != x"ff") and (Op_Mem != x"06" Op_Mem!= x"ff") and - - -- check Registers are the same - (A_Mem = B_DI) or (A_Mem = C_DI) - ) - else '0'; + -- check Registers are the same + ((A_Re = B_DI) or (A_Re = C_DI)) + ) + else '0'; end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd index 8b5bb43..d4cade3 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd @@ -35,7 +35,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; entity IP is Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; -- rst when 0 + RST : in STD_LOGIC; -- rst when 1 LOAD : in STD_LOGIC; EN : in STD_LOGIC; -- enable when 0 Din : in STD_LOGIC_VECTOR (7 downto 0); @@ -49,7 +49,7 @@ begin begin wait until rising_edge(CLK); - if (RST = '0') then + if (RST = '1') then aux <= x"00"; elsif (LOAD = '1') then aux <= Din; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd index 4b9a49b..eed9e61 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd @@ -40,14 +40,9 @@ end InstructionMemory; architecture Behavioral of InstructionMemory is type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); - signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); - +-- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000")); + signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); begin - - process - begin - wait until clk'event and clk = '1'; - Inst_out <= Mem(to_integer(unsigned(Addr))); - end process; - + Inst_out <= Mem(to_integer(unsigned(Addr))); end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd index 5e0f95f..7ae32ec 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd @@ -43,21 +43,18 @@ end DataMemory; architecture Behavioral of DataMemory is type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); - signal Mem : Mem_array; + signal Mem : Mem_array := (others => x"00"); begin process begin wait until clk'event and clk = '1'; - if Rst = '0' then -- Reset - mem <= (others => x"00"); - else if Rw = '1' then --reading - Data_out <= Mem(to_integer(unsigned(Addr))); - else -- writting + if Rst = '1' then -- Reset + mem <= (others => x"00"); + else if Rw = '0' then --writing Mem(to_integer(unsigned(Addr))) <= Data_in; end if; end if; end process; - - + Data_out <= Mem(to_integer(unsigned(Addr))); --reading end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index 9709371..b4233f7 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -32,22 +32,21 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Pipeline is - Port ( Clk : in STD_LOGIC); + Port (RST : in STD_LOGIC; Clk : in STD_LOGIC); end Pipeline; architecture Behavioral of Pipeline is component IP is port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; -- rst when 0 + RST : in STD_LOGIC; -- rst when 1 LOAD : in STD_LOGIC; - EN : in STD_LOGIC; -- enable when 1 + EN : in STD_LOGIC; -- enable when 0 Din : in STD_LOGIC_VECTOR (7 downto 0); Dout : out STD_LOGIC_VECTOR (7 downto 0)); end component; signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal Rst : STD_LOGIC; -- to modify component InstructionMemory Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); @@ -55,7 +54,7 @@ architecture Behavioral of Pipeline is Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); end component; - signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '0'); + signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '1'); component Stage_Li_Di Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); @@ -70,8 +69,6 @@ architecture Behavioral of Pipeline is ); end component; - signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - component Registers Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); Addr_B : in STD_LOGIC_VECTOR (3 downto 0); @@ -85,8 +82,8 @@ architecture Behavioral of Pipeline is ); end component; - signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); + signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); component Stage_Di_Ex Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); @@ -101,7 +98,7 @@ architecture Behavioral of Pipeline is ); end component; - signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); component ALU Port ( A : in STD_LOGIC_VECTOR (7 downto 0); @@ -115,7 +112,7 @@ architecture Behavioral of Pipeline is ); end component; - signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; component Stage_Ex_Mem @@ -129,9 +126,9 @@ architecture Behavioral of Pipeline is ); end component; - signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal Mem_RW : STD_LOGIC; - signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); component DataMemory Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); @@ -153,24 +150,24 @@ architecture Behavioral of Pipeline is Out_Op : out STD_LOGIC_VECTOR (7 downto 0) ); end component; - component ControlUnit is - Port ( Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0); - A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0); + component AleaControler is + Port ( Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0); + A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0); B_DI : in STD_LOGIC_VECTOR (7 downto 0); C_DI : in STD_LOGIC_VECTOR (7 downto 0); CNTRL : out STD_LOGIC - ); + ); end component; - signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal Re_W : STD_LOGIC; -- to control jumping and where to jump - signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); signal jump : STD_LOGIC; signal nop_Cntrl : STD_LOGIC; - signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); begin -- instructionPointer @@ -178,7 +175,7 @@ inst_point : IP port map ( CLK=> clk, Dout=> IP_out, Din => addr_to_jump, - RST => '1', + RST => rst, EN => nop_Cntrl, LOAD => jump); @@ -272,7 +269,7 @@ Stage4 : Stage_Mem_Re PORT MAP ( -- DIV x"04" -- COP x"05" -- AFC x"06" - -- LOAD x"07" + -- LOAD x"07"OP_DI -- STORE x"08" -- INF x"09" -- SUP x"0A" @@ -289,7 +286,8 @@ Stage4 : Stage_Mem_Re PORT MAP ( -- Mux post registers Di_FinalB <= Di_B when - Di_OP = x"06" -- AFC + Di_OP = x"06" or -- AFC + Di_OP = x"07" -- LOAD else Di_RegB; -- Mux post ALU @@ -312,23 +310,23 @@ Mem_FinalB <= Mem_B when or Mem_Op = x"03" -- SUB or Mem_Op = x"02" -- MUL or Mem_Op = x"04" -- DIV - else Mem_FinalB ; --LOAD & STORE + else Mem_Data_out ; --LOAD & STORE -- Mux pre data memory Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD else Mem_A; --STORE -- LC pre data memory -Mem_RW <= '1' when Mem_Op = x"07" --LOAD - else '0'; --STORE +Mem_RW <= '0' when Mem_Op = x"08" --STORE + else '1'; --STORE -- LC post Pip_Mem_Re -Re_W <= '0' when Re_Op = x"08" --STORE +Re_W <= '0' when Re_Op = x"08" or Re_Op = x"ff" --STORE else '1'; -CU : ControlUnit port map ( - Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, - A_EX => Di_A, A_Mem => Ex_A, +CU : AleaControler port map ( + Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, Op_Re => Mem_Op, + A_EX => Di_A, A_Mem => Ex_A, A_Re => Mem_A, B_DI => Li(15 downto 8), C_DI => Li(7 downto 0), CNTRL => nop_Cntrl); @@ -336,4 +334,4 @@ CU : ControlUnit port map ( -- in case of alea : replace li(31 downto 24) by NOP OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); - end Behavioral; \ No newline at end of file + end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd index f132e6e..c137e3f 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd @@ -46,13 +46,13 @@ end Registers; architecture Behavioral of Registers is type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0); - signal Regs : Reg_array; + signal Regs : Reg_array := (others => x"00"); begin process begin wait until clk'event and clk = '1'; - if Rst = '0' then -- Reset + if Rst = '1' then -- Reset Regs <= (others => x"00"); elsif W = '1' then -- Writing Regs(to_integer(unsigned(Addr_W))) <= Data; diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr index ffe552f..4b10f19 100644 --- a/VHDL/ALU/ALU.xpr +++ b/VHDL/ALU/ALU.xpr @@ -3,7 +3,7 @@ - +

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a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ 1685389741 1685390103 -104 +147 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl index 6c5c8cc..fe1417b 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:40 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Tue May 30 16:24:18 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "103" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "146" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "2757.340 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2576.095 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122660_KB" -context "xsim\\usage" -webtalk_transmit -clientid 653659988 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key iteration -value "5" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "122664_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2613593652 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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-/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685437044,vhdl,,,,test_total,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685444515,vhdl,,,,aleacontroler,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685451235,vhdl,,,,test_total,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685454749,vhdl,,,,alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685451016,vhdl,,,,aleacontroler,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685439807,vhdl,,,,instructionmemory,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685456575,vhdl,,,,instructionmemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685443285,vhdl,,,,pipeline,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685455519,vhdl,,,,pipeline,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, diff --git a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd index b5debf1..32ba8ab 100644 --- a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd +++ b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd @@ -39,17 +39,15 @@ architecture Behavioral of test_total is component Pipeline - Port ( rst : in STD_LOGIC; Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC); end component; constant clock_period : time := 10 ns; signal clock : Std_logic := '0'; - signal rst : Std_logic := '1'; begin -- instantiate Pl : Pipeline PORT MAP ( - Rst => rst, Clk => clock ); @@ -59,6 +57,4 @@ begin wait for 100ns; end process; - rst <= '0' after 50ns; - end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd index 1ef8568..6ce7ac6 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd @@ -41,7 +41,9 @@ entity ALU is N : out STD_LOGIC; O : out STD_LOGIC; Z : out STD_LOGIC; - C : out STD_LOGIC); + C : out STD_LOGIC; + JumpFlag : inout STD_LOGIC -- 0 false 1 true + ); end ALU; -- Instruction code @@ -60,7 +62,7 @@ end ALU; architecture Behavioral of ALU is signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000"; - + signal flag : STD_LOGIC := '0'; begin process(A, B, Ctrl_Alu) begin @@ -68,20 +70,22 @@ begin O <= '0'; Z <= '0'; C <= '0'; + flag <= JumpFlag; case Ctrl_Alu is when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV - when x"09" => if A < B then res <= x"0001"; else res <= x"0000"; end if; - when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if; - when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if; - when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if; - when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; else res <= x"0000"; end if; - when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; else res <= x"0000"; end if; - when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; else res <= x"0000"; end if; + when x"09" => if A < B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0A" => if A > B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0B" => if A = B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0C" => if A > 0 then res <= x"0000"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when others => res <= x"0000"; end case; end process; + JumpFlag <= flag; S <= res(7 downto 0); end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd index 22d8155..4cb3f72 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd @@ -68,6 +68,10 @@ begin -- check Registers are the same ((A_Re = B_DI) or (A_Re = C_DI)) - ) + ) + or + ( + Op_EX = x"10" or Op_Mem = x"10" or Op_Re = x"10" + ) else '0'; end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd index eed9e61..7f4f048 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd @@ -41,7 +41,12 @@ end InstructionMemory; architecture Behavioral of InstructionMemory is type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); -- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000")); - signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- test JMP signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08030000"),(x"07000300"),(x"08010000"),(x"0F0D0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08020000"),(x"06000900"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); +-- test JMF signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"100F0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); +-- test if else signal Mem : Mem_array := ((x"06000200"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10021000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F140000"),(x"06000C00"),(x"08020000"),(x"07000200"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); +-- test boucle while +signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10001B00"),(x"06001400"),(x"08030000"),(x"07000000"),(x"07010300"),(x"09020001"),(x"08040200"),(x"10041B00"),(x"06000200"),(x"08010000"),(x"07000000"),(x"07010100"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F0B0000"),(x"FF000000"),others => (x"ff000000")); -- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); begin Inst_out <= Mem(to_integer(unsigned(Addr))); diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index b4233f7..e2e2c39 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Pipeline is - Port (RST : in STD_LOGIC; Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC); end Pipeline; architecture Behavioral of Pipeline is @@ -47,6 +47,7 @@ architecture Behavioral of Pipeline is end component; signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal rst : STD_LOGIC := '0'; component InstructionMemory Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); @@ -108,12 +109,13 @@ architecture Behavioral of Pipeline is N : out STD_LOGIC; O : out STD_LOGIC; Z : out STD_LOGIC; - C : out STD_LOGIC + C : out STD_LOGIC; + JumpFlag : inout STD_LOGIC ); end component; signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; + signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag, Jump_Flag : STD_LOGIC; component Stage_Ex_Mem Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); @@ -163,11 +165,12 @@ architecture Behavioral of Pipeline is signal Re_W : STD_LOGIC; -- to control jumping and where to jump - signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal jump : STD_LOGIC; + signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal jump : STD_LOGIC := '0'; signal nop_Cntrl : STD_LOGIC; signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); + signal Di_Op_Final : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); begin -- instructionPointer @@ -215,7 +218,7 @@ Stage2 : Stage_Di_Ex PORT MAP ( In_A => Di_A, In_B => Di_FinalB, In_C => Di_C2, - In_Op => Di_Op, + In_Op => Di_Op_Final, Clk => Clk, Out_A => Ex_A, Out_B => Ex_B, @@ -231,7 +234,8 @@ Ual : ALU PORT MAP ( N => S_NFlag, O => S_OFlag, Z => S_ZFlag, - C => S_CFlag); + C => S_CFlag, + JumpFlag => Jump_Flag); -- Stage Ex/Mem Stage3 : Stage_Ex_Mem PORT MAP ( @@ -332,6 +336,22 @@ CU : AleaControler port map ( CNTRL => nop_Cntrl); -- in case of alea : replace li(31 downto 24) by NOP - OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24); + OP_LI_DI <= X"ff" when (nop_Cntrl='1' or + (Di_Op = x"10" and Jump_Flag = '1')) -- to prevent JMF + else Li(31 downto 24); + +-- jump JMP + addr_to_jump <= DI_A when (DI_OP = x"0F") -- JMP + else Di_B when (Di_Op = x"10" and Jump_Flag = '0') -- JMF + else (others => '0'); + jump <= '1' when DI_OP = x"0F" -- JMP + or (Di_Op = x"10" and Jump_Flag = '0') -- JMF + else '0'; + +-- case of JMF not triggering + Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1') + else Di_Op; + + end Behavioral; diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr index 4b10f19..a429411 100644 --- a/VHDL/ALU/ALU.xpr +++ b/VHDL/ALU/ALU.xpr @@ -33,7 +33,7 @@