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Raphaël LACROIX 2023-05-12 16:03:47 +02:00
parent 019a8c506e
commit c369d180b0
1 changed files with 87 additions and 35 deletions
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122
post-process.py
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@ -1,3 +1,5 @@
import re
opToBinOP = { opToBinOP = {
"ADD": 1, "ADD": 1,
"MUL": 2, "MUL": 2,
@ -16,80 +18,130 @@ opToBinOP = {
"NOT": 15 "NOT": 15
} }
def output(s):
fileOutput = open('asm2', 'w')
fileOutput.write("\n".join(s))
fileOutput.close()
def convertToRegister(s): def convertToRegister(s):
# TODO check if there is a /\d_label/ in s[0] and if so adds it back at the start of the output
l = [] l = []
if not re.match(r"\d_LABEL .*", s[0]) :
optionalFlag = ""
incr = 0
else:
optionalFlag = s[0] + " "
incr = 1
match s[0]: match s[0]:
case "ADD": case "ADD":
l.append("LOAD R0 "+s[2]) l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3]) l.append("LOAD R1 "+s[3+incr])
l.append("ADD R0 R0 R1") l.append("ADD R0 R0 R1")
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "MUL": case "MUL":
l.append("LOAD R0 "+s[2]) l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3]) l.append("LOAD R1 "+s[3+incr])
l.append("MUL R0 R0 R1") l.append("MUL R0 R0 R1")
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "SUB": case "SUB":
l.append("LOAD R0 "+s[2]) l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3]) l.append("LOAD R1 "+s[3+incr])
l.append("SUB R0 R0 R1") l.append("SUB R0 R0 R1")
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "DIV_INT": case "DIV_INT":
l.append("LOAD R0 "+s[2]) l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3]) l.append("LOAD R1 "+s[3+incr])
l.append("DIV R0 R0 R1") l.append("DIV R0 R0 R1")
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "COP": case "COP":
l.append("LOAD R0 "+s[2]) l.append(optionalFlag+"LOAD R0 "+s[2+incr])
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "AFC": case "AFC":
l.append("AFC R0 "+s[2]) l.append(optionalFlag+"AFC R0 "+s[2+incr])
l.append("STORE "+s[1]+" R0") l.append("STORE "+s[1+incr]+" R0")
case "JMP": case "JMP":
pass pass
case "JMF": case "JMF":
pass pass
case "INF": case "INF":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+inc]) l.append("LOAD R1 "+s[3+incr])
l.append("INF R2 R0 R1") l.append("INF R2 R0 R1")
case "SUP": case "SUP":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+inc]) l.append("LOAD R1 "+s[3+incr])
l.append("SUP R2 R1 R0") l.append("SUP R2 R1 R0")
case "EQ": case "EQ":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+inc]) l.append("LOAD R1 "+s[3+incr])
l.append("EQ R2 R1 R0") l.append("EQ R2 R1 R0")
case "PRI": case "PRI":
l.append("PRI "+s[2+inc]) l.append("PRI "+s[2+incr])
case "AND": case "AND":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+inc]) l.append("LOAD R1 "+s[3+incr])
l.append("AND R2 R0 R1") l.append("AND R2 R0 R1")
case "OR": case "OR":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("LOAD R1 "+s[3+inc]) l.append("LOAD R1 "+s[3+incr])
l.append("OR R2 R0 R1") l.append("OR R2 R0 R1")
case "NOT": case "NOT":
l.append("LOAD R0 "+s[2+inc]) l.append("LOAD R0 "+s[2+incr])
l.append("NOT R2 R0") l.append("NOT R2 R0")
''' R2 contiendra la valeur qui dit s'il faut sauter ou non''' """ R2 contiendra la valeur qui dit s'il faut sauter ou non """
return l return l
totalLine = 0 # TODO Check the number of line is never reached
labelCount = 0 # used to create a new label each time
fileInput = open("asm", "r") fileInput = open("asm", "r")
ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines())) ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines()))
print(ASMLines) fileInput.close()
finalCode = []
ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
ASMLinesFinal = [] # will contain the output, register-based, code
for i, l in enumerate(ASMLines): for i, l in enumerate(ASMLines):
items = l.split(" ") items = l.split(" ")
finalCode.extend(convertToRegister(items)) if items[0] in ["JMP", "JMF"]:
# idée pour les jumps : quand on voit un jump à la ligne tant on peut ajouter un label là-bas lineToJumpTo = int(items[
1 if items[0] == "JMP" else 2
])
if re.match(r"\d_LABEL .*", ASMLinesLabel[lineToJumpTo]):
ASMLinesLabel[i] = " ".join(ASMLines[i].split()[:-1] + [ASMLinesLabel[lineToJumpTo].split()[0]])
else:
ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo]
ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"])
labelCount += 1
print(ASMLinesLabel)
for i, l in enumerate(ASMLinesLabel):
ASMLinesRegister.extend(convertToRegister(l.split()))
print(ASMLinesRegister)
labels = {}
for i, l in enumerate(ASMLinesRegister):
if re.match(r"\d_LABEL .*", l):
labels[l.split()[0]] = i
ASMLinesRegister[i] = " ".join(ASMLinesRegister[i].split()[1:])
print(ASMLinesRegister)
for i, l in enumerate(ASMLinesRegister):
label = re.match(r"\d_LABEL", l.split()[-1])
if label:
ASMLinesFinal.append(" ".join(l.split()[:-1] + [str(labels[label[0]])]))
else :
ASMLinesFinal.append(l)
print(ASMLinesRegister)
output(ASMLinesFinal)
# - trucs en registre # - trucs en registre
# - décaler les Jumps # - décaler les Jumps
# - COP -> OPCode # - COP -> OPCode