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fixed missing store in post process

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This commit is contained in:
Raphaël LACROIX 2023-05-31 22:01:23 +02:00
parent eb384e3018
commit 52ea586362
1 changed files with 25 additions and 6 deletions
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29
post-process.py
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@ -75,44 +75,59 @@ def convertToRegister(s):
case "JMP":
l.append(" ".join(s))
case "JMF":
if len(s) == 3:
l.append(" ".join(s))
else :
l.append(s[0]+ " 0 " + s[1])
case "INF":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("INF 2 0 1")
l.append("STORE " + s[1 + incr] + " 2")
case "SUP":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("SUP 2 1 0")
l.append("STORE " + s[1 + incr] + " 2")
case "EQ":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("EQ 2 1 0")
l.append("STORE " + s[1 + incr] + " 2")
case "PRI":
l.append(optionalFlag + "PRI " + s[2 + incr])
case "AND":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("AND 2 0 1")
l.append("STORE " + s[1 + incr] + " 2")
case "OR":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("LOAD 1 " + s[3 + incr])
l.append("OR 2 0 1")
l.append("STORE " + s[1 + incr] + " 2")
case "NOT":
l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
l.append("NOT 2 0")
l.append("STORE " + s[1 + incr] + " 2")
case default:
l.append(" ".join(s))
""" R2 will contain the information whether to jump or not"""
return l
totalLine = 0 # TODO Check the number of line is never reached
totalLine = 0
labelCount = 0 # used to create a new label each time
fileInput = open("asm", "r")
ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines()))
fileInput.close()
# added to prevent problems when cross compiling some code representing a jump to after the last line
ASMLines.append("NOP")
ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
ASMLinesFinal = [] # will contain the output, register-based, code
@ -120,9 +135,7 @@ ASMLinesFinal = [] # will contain the output, register-based, code
for i, l in enumerate(ASMLines):
items = l.split(" ")
if items[0] in ["JMP", "JMF"]:
lineToJumpTo = int(items[
1 if items[0] == "JMP" else 2
])
lineToJumpTo = int(items[-1])
if re.match(r"\d_LABEL .*", ASMLinesLabel[lineToJumpTo]):
ASMLinesLabel[i] = " ".join(ASMLines[i].split()[:-1] + [ASMLinesLabel[lineToJumpTo].split()[0]])
else:
@ -158,6 +171,12 @@ for i, l in enumerate(ASMLinesFinal):
while len(arr) < 4:
arr.append(0)
lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\")"
ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\"))"
print("converted to VHDL-friendly format : " + ASMLinesConverted)
output(ASMLinesConverted, 3, True)
""" Used to generate the beautiful table in the report
for i in range(10):
print(f"{ASMLines[i]} & {ASMLinesFinal[i]} & {ASMLinesConverted.split(',')[i]} \\\\")
"""