fixed missing store in post process
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parent
eb384e3018
commit
52ea586362
1 changed files with 25 additions and 6 deletions
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@ -75,44 +75,59 @@ def convertToRegister(s):
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case "JMP":
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case "JMP":
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l.append(" ".join(s))
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l.append(" ".join(s))
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case "JMF":
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case "JMF":
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l.append(" ".join(s))
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if len(s) == 3:
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l.append(" ".join(s))
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else :
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l.append(s[0]+ " 0 " + s[1])
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case "INF":
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case "INF":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("INF 2 0 1")
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l.append("INF 2 0 1")
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l.append("STORE " + s[1 + incr] + " 2")
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case "SUP":
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case "SUP":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("SUP 2 1 0")
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l.append("SUP 2 1 0")
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l.append("STORE " + s[1 + incr] + " 2")
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case "EQ":
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case "EQ":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("EQ 2 1 0")
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l.append("EQ 2 1 0")
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l.append("STORE " + s[1 + incr] + " 2")
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case "PRI":
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case "PRI":
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l.append(optionalFlag + "PRI " + s[2 + incr])
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l.append(optionalFlag + "PRI " + s[2 + incr])
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case "AND":
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case "AND":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("AND 2 0 1")
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l.append("AND 2 0 1")
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l.append("STORE " + s[1 + incr] + " 2")
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case "OR":
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case "OR":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("LOAD 1 " + s[3 + incr])
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l.append("OR 2 0 1")
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l.append("OR 2 0 1")
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l.append("STORE " + s[1 + incr] + " 2")
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case "NOT":
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case "NOT":
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
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l.append("NOT 2 0")
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l.append("NOT 2 0")
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l.append("STORE " + s[1 + incr] + " 2")
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case default:
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l.append(" ".join(s))
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""" R2 will contain the information whether to jump or not"""
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""" R2 will contain the information whether to jump or not"""
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return l
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return l
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totalLine = 0 # TODO Check the number of line is never reached
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totalLine = 0
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labelCount = 0 # used to create a new label each time
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labelCount = 0 # used to create a new label each time
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fileInput = open("asm", "r")
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fileInput = open("asm", "r")
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ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines()))
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ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines()))
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fileInput.close()
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fileInput.close()
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# added to prevent problems when cross compiling some code representing a jump to after the last line
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ASMLines.append("NOP")
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ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
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ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted
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ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
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ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels
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ASMLinesFinal = [] # will contain the output, register-based, code
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ASMLinesFinal = [] # will contain the output, register-based, code
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@ -120,9 +135,7 @@ ASMLinesFinal = [] # will contain the output, register-based, code
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for i, l in enumerate(ASMLines):
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for i, l in enumerate(ASMLines):
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items = l.split(" ")
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items = l.split(" ")
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if items[0] in ["JMP", "JMF"]:
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if items[0] in ["JMP", "JMF"]:
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lineToJumpTo = int(items[
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lineToJumpTo = int(items[-1])
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1 if items[0] == "JMP" else 2
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])
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if re.match(r"\d_LABEL .*", ASMLinesLabel[lineToJumpTo]):
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if re.match(r"\d_LABEL .*", ASMLinesLabel[lineToJumpTo]):
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ASMLinesLabel[i] = " ".join(ASMLines[i].split()[:-1] + [ASMLinesLabel[lineToJumpTo].split()[0]])
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ASMLinesLabel[i] = " ".join(ASMLines[i].split()[:-1] + [ASMLinesLabel[lineToJumpTo].split()[0]])
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else:
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else:
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@ -158,6 +171,12 @@ for i, l in enumerate(ASMLinesFinal):
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while len(arr) < 4:
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while len(arr) < 4:
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arr.append(0)
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arr.append(0)
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lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
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lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
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ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\")"
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ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\"))"
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print("converted to VHDL-friendly format : " + ASMLinesConverted)
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print("converted to VHDL-friendly format : " + ASMLinesConverted)
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output(ASMLinesConverted, 3, True)
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output(ASMLinesConverted, 3, True)
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""" Used to generate the beautiful table in the report
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for i in range(10):
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print(f"{ASMLines[i]} & {ASMLinesFinal[i]} & {ASMLinesConverted.split(',')[i]} \\\\")
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"""
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