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Added vhdl/inter make options

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Raphaël LACROIX 2023-05-31 21:59:52 +02:00
parent 0642e1bab6
commit 4529d87b04
1 changed files with 8 additions and 3 deletions
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11
Makefile
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@ -7,10 +7,9 @@ CFLAGS=-Wall -g
OBJ=yacc.tab.o lex.yy.o table.o operations.o blocs.o asmTable.o OBJ=yacc.tab.o lex.yy.o table.o operations.o blocs.o asmTable.o
all: $(BIN) asm: $(BIN)
@touch testFile # to prevent an error in case of deletion @touch testFile # to prevent an error in case of deletion
./out < testFile ./out < testFile
build: $(BIN) build: $(BIN)
@ -29,3 +28,9 @@ $(BIN): $(OBJ)
clean: clean:
rm $(OBJ) yacc.tab.c yacc.tab.h lex.yy.c rm $(OBJ) yacc.tab.c yacc.tab.h lex.yy.c
vhdl: clean asm
python3 post-process.py
inter: clean asm
python3 graph_interpreter.py