diff --git a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf index eb381bd..562c893 100644 --- a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf +++ b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf @@ -1,41 +1,50 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:3336:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f636c6f7365:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3137:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3834:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3235:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3331:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6e6f:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:323335:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:3430:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636c6f636b6372656174696f6e70616e656c5f636c6f636b5f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636c6f636b6372656174696f6e70616e656c5f656e7465725f706f7369746976655f6e756d626572:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3333:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d62696e6174696f6e616c636f6e73747261696e74737461626c6570616e656c5f7461626c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f6578697374696e675f6f725f6372656174655f6e65775f636f6e73747261696e7473:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f66696c655f7461626c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f6578697374696e675f6f725f6372656174655f6e65775f636f6e73747261696e7473:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f66696c655f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746572756e7265706f72746469616c6f675f7265706f72745f6e616d65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:313438:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f656e746974795f6e616d65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65646974637265617465636c6f636b7461626c6570616e656c5f656469745f6372656174655f636c6f636b5f7461626c65:3133:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6578707265706f72747472656570616e656c5f656469745f7265706f72745f6f7074696f6e73:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6578707265706f72747472656570616e656c5f6578705f7265706f72745f747265655f7461626c65:39:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:343533:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:363036:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f6d65737361676573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:313935:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:333736:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:313033:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:313334:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:313338:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:313532:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3430:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f6c696e655f636f6d6d656e7473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:696e7075746f75747075747461626c6570616e656c5f7461626c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f6770616e656c5f636f7079:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f6770616e656c5f66696e64:31:00:00 @@ -44,79 +53,122 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:3138:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:3136:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3730:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3736:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f696f5f706c616e6e696e67:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:3235:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3437:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3531:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73657474696e6773:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f74696d696e67:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f756e73656c6563745f74797065:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:3136:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3235:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c6f6164:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:313732:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f6572726f725f6d65737361676573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6176696761626c6574696d696e677265706f72747461625f74696d696e675f7265706f72745f6e617669676174696f6e5f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e756d6a6f627363686f6f7365725f6e756d6265725f6f665f6a6f6273:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f63616e63656c:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f6f70656e5f6469726563746f7279:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3138:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e74617267657477697a6172645f636f6e6e6563745f746f:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f636f6e6669675f6d656d6f7279:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3236:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f66696c657365745f77696e646f77:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f696e7374616e74696174696f6e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f726563656e745f746172676574:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f7461726765745f77697a617264:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f6772616d5f66706761:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f72745f636c6f636b5f6e6574776f726b73:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f7461726765745f756366:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:313333:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:313735:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f706f73745f73796e7468657369735f66756e6374696f6e616c:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f73657474696e6773:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f73657474696e6773:39:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3335:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3431:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636b6167657472656570616e656c5f7061636b6167655f747265655f70616e656c:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706c616e61686561647461625f73686f775f666c6f775f6e6176696761746f72:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7072696d617279636c6f636b7370616e656c5f7265636f6d6d656e6465645f636f6e73747261696e74735f7461626c65:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7072696d617279636c6f636b7370616e656c5f7265636f6d6d656e6465645f636f6e73747261696e74735f7461626c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f726563656e746c795f6f70656e65645f746172676574:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f726566726573685f646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f636865636b5f656e645f6f665f73746172747570:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:3136:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e67736761646765745f656469745f70726f6a6563745f73657474696e6773:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f73656c6563745f7465737462656e63685f746f705f6d6f64756c65:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f7461626265645f70616e65:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f6c696e655f636f6d6d656e74:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f7461626265645f70616e65:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f636c6f73655f64657369676e:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f637573746f6d5f636f6d6d616e6473:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f6c696e655f636f6d6d656e74:3233:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:363238:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:373935:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72746c6f7074696f6e7370616e656c5f73656c6563745f746f705f6d6f64756c655f6f665f796f75725f64657369676e:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7265706f72746e617669676174696f6e686f6c6465725f726572756e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f6572726f725f616e645f637269746963616c5f7761726e696e675f6d65737361676573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:3436:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c656374746f706d6f64756c656469616c6f675f73656c6563745f746f705f6d6f64756c65:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e67736469616c6f675f70726f6a6563745f74726565:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3435:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3734:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7369676e616c7472656570616e656c5f7369676e616c5f747265655f7461626c65:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3535:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3830:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:3231:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3136:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3339:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f636865636b5f74696d696e675f7265706f7274:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3236:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f796573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f636c6561725f616c6c5f6f75747075745f696e5f74636c5f636f6e736f6c65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3530:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f636865636b5f74696d696e675f7265706f7274:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f6d6574686f646f6c6f67795f7265706f7274:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f74696d696e675f73756d6d6172795f7265706f7274:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f766965775f74696d696e675f636f6e73747261696e7473:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:323633:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f74696d696e675f73756d6d6172795f7265706f7274:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f676f746f5f636f6e73747261696e74735f73756d6d6172795f70616765:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f766965775f74696d696e675f636f6e73747261696e7473:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:323832:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f72657365745f746f5f64656661756c7473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f73686f775f7369676e616c5f696e6469636573:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6164645f6d61726b6572:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f6c6173745f74696d65:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f74696d655f30:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6e6578745f6d61726b6572:33:00:00 -eof:1736165994 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:786463656469746f72766965775f6170706c795f616c6c5f6368616e6765735f746f5f7864635f636f6e73747261696e7473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:786463766965776572747265657461626c6570616e656c5f7864635f7669657765725f747265655f7461626c65:34:00:00 +eof:67023714 diff --git a/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf b/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf index a1dbbdf..61b4ec9 100644 --- a/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf +++ b/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf @@ -1,23 +1,36 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3230:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646366676d656d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3234:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:656469747061737465:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e63686f70656e746172676574:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3136:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3235:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3132:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3139:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f727474696d696e6773756d6d617279:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3437:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3232:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746172676574636f6e73747266696c65:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f77736f75726365:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3534:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:35:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:313331:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:313733:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:3135:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965776c61796f7574636d64:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:34:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:77617665666f726d73617665636f6e66696775726174696f6e:3131:00:00 -eof:158833456 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:77617665666f726d73617665636f6e66696775726174696f6e:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:786463637265617465636c6f636b:31:00:00 +eof:2756648638 diff --git a/VHDL/ALU/ALU.cache/wt/project.wpc b/VHDL/ALU/ALU.cache/wt/project.wpc index 7e694a7..edfdec4 100644 --- a/VHDL/ALU/ALU.cache/wt/project.wpc +++ b/VHDL/ALU/ALU.cache/wt/project.wpc @@ -1,3 +1,4 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:21 +57656254616c6b5472616e736d697373696f6e417474656d70746564:12 +6d6f64655f636f756e7465727c4755494d6f6465:24 eof: diff --git a/VHDL/ALU/ALU.cache/wt/synthesis.wdf b/VHDL/ALU/ALU.cache/wt/synthesis.wdf index 3ebe16b..cc6c5df 100644 --- a/VHDL/ALU/ALU.cache/wt/synthesis.wdf +++ b/VHDL/ALU/ALU.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3238314d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436314d42:00:00 -eof:428720552 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323373:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313635312e3231394d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3439312e3339384d42:00:00 +eof:2592849427 diff --git a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml index b8b518b..5f94549 100644 --- a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml +++ b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,66 +17,88 @@ This means code written to parse this file will need to be revisited each subseq - + + + - + + + + + - - - + + + + + + + + - + - - + + - + - + + - + + + - + + - - - - - + + + + + + + + + + - - - - - + + + + + + - + - + - - + + - + + @@ -85,86 +107,129 @@ This means code written to parse this file will need to be revisited each subseq - - + + + - - + + - + - - - + + + + + - - + + + + + + + + + + + + - - + + + + + + - + - + + + + + + + - + - + - - + + + - - + + + + + + + + - - - - + + + + + + - + - + + + + - - + + + - - - - - - - + + + + + + + + + + - - - + + + + + + + - + - +
diff --git a/VHDL/ALU/ALU.hw/ALU.lpr b/VHDL/ALU/ALU.hw/ALU.lpr index 4577eea..68b7fe8 100644 --- a/VHDL/ALU/ALU.hw/ALU.lpr +++ b/VHDL/ALU/ALU.hw/ALU.lpr @@ -3,4 +3,6 @@ - + + + diff --git a/VHDL/ALU/ALU.hw/hw_1/hw.xml b/VHDL/ALU/ALU.hw/hw_1/hw.xml new file mode 100644 index 0000000..f20d5c2 --- /dev/null +++ b/VHDL/ALU/ALU.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..806781c --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..330f416 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..4c95ac6 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml new file mode 100644 index 0000000..a2d5bc4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml new file mode 100644 index 0000000..715a1f3 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml new file mode 100644 index 0000000..715a1f3 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml new file mode 100644 index 0000000..715a1f3 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..b34d040 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.Vivado_Implementation.queue.rst b/VHDL/ALU/ALU.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..bc98f66 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.init_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..bc98f66 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.opt_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..bc98f66 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.place_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..bc98f66 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.route_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..4284699 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.vivado.end.rst b/VHDL/ALU/ALU.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..bc98f66 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.end.rst b/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit b/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit new file mode 100644 index 0000000..c07098d Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl b/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl new file mode 100644 index 0000000..3eef97e --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl @@ -0,0 +1,171 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcpg236-1 + set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project] + set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project] + set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp + read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc + link_design -top Pipeline -part xc7a35tcpg236-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force Pipeline_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force Pipeline_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file Pipeline_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Pipeline_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force Pipeline_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Pipeline_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force Pipeline_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force Pipeline.mmi } + write_bitstream -force Pipeline.bit + catch {write_debug_probes -quiet -force Pipeline} + catch {file copy -force Pipeline.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi b/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi new file mode 100644 index 0000000..35f7c37 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi @@ -0,0 +1,472 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed May 31 17:57:08 2023 +# Process ID: 144223 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1 +# Command line: vivado -log Pipeline.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source Pipeline.tcl -notrace +Command: link_design -top Pipeline -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1e379f571 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e379f571 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 224c05fcb + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 237fe1223 + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 237fe1223 + +Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +Ending Logic Optimization Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx +Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd + +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Phase 1 Placer Initialization | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15cb247ff + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Phase 3 Detail Placement | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Ending Placer Task | Checksum: 8268151a + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt +report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537 +INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs +Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437 +Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 16523de4e + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 11b0f7581 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 97 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 +Phase 4 Rip-up And Reroute | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 +Phase 6 Post Hold Fix | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.153313 % + Global Horizontal Routing Utilization = 0.172046 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16fad2baa + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx +Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx +Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 6 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx +Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs +Command: write_bitstream -force Pipeline.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 6 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. +WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7. +WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./Pipeline.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368 +INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023... diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt new file mode 100644 index 0000000..d54e949 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:14 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx +| Design : Pipeline +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +--------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx new file mode 100644 index 0000000..41eaae5 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt new file mode 100644 index 0000000..abfe0fc --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt @@ -0,0 +1,145 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:14 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt +| Design : Pipeline +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +-------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 342 | 0 | | | Clk_IBUF_BUFG_inst/O | Clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | None | IOB_X0Y128 | X0Y2 | 1 | 0 | | | Clk_IBUF_inst/O | Clk_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 342 | 1200 | 136 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 342 | 0 | 0 | 0 | Clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+ +| | X0 | X1 | ++----+------+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 342 | 0 | ++----+------+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 342 | 0 | 342 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells Clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y128 [get_ports Clk] + +# Clock net "Clk_IBUF_BUFG" driven by instance "Clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_Clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} +#endgroup diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt new file mode 100644 index 0000000..436bb01 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt @@ -0,0 +1,101 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:57:59 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt +| Design : Pipeline +| Device : xc7a35t +------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 36 | +| Unused register locations in slices containing registers | 12 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 12 | 2 | +| 16+ | 34 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 132 | 23 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 24 | 4 | +| Yes | No | No | 528 | 111 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------+-----------------------+---------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+-----------------------+---------------------+------------------+----------------+ +| Clk_IBUF_BUFG | | Stage1/Di_Op_Final1 | 2 | 12 | +| Clk_IBUF_BUFG | | Stage1/OP_LI_DI1 | 2 | 12 | +| Clk_IBUF_BUFG | Stage3/Mem[6]_8 | | 1 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[6]_9 | | 5 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[10]_8 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[11]_4 | | 5 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[12]_0 | | 5 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[13]_11 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[7]_5 | | 5 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[8]_1 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[9]_12 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs_reg[0][7] | | 2 | 16 | +| Clk_IBUF_BUFG | Stage1/aux_reg[7] | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[1]_14 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[2]_10 | | 5 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[8]_2 | | 1 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[9]_9 | | 3 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[4]_2 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[5]_13 | | 3 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[5]_0 | | 1 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem_reg[1][0] | | 2 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem_reg[2][0] | | 1 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[14]_7 | | 6 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[3]_7 | | 3 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem_reg[13][0] | | 1 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem_reg[14][0] | | 2 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[7]_6 | | 2 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[11]_5 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[12]_1 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[15]_3 | | 7 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[10]_10 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[15]_4 | | 2 | 16 | +| Clk_IBUF_BUFG | Stage4/Regs[3]_6 | | 4 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[0]_11 | | 2 | 16 | +| Clk_IBUF_BUFG | Stage3/Mem[4]_3 | | 3 | 16 | +| Clk_IBUF_BUFG | | | 23 | 132 | ++----------------+-----------------------+---------------------+------------------+----------------+ + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb new file mode 100644 index 0000000..6c5ff57 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt new file mode 100644 index 0000000..62607dd --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt @@ -0,0 +1,72 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:57:56 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx +| Design : Pipeline +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 5 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 | +| NSTD-1 | Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Warning | Unconstrained Logical Port | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +LUTLP-2#1 Warning +Combinatorial Loop Allowed +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. +Related violations: + +LUTLP-2#2 Warning +Combinatorial Loop Allowed +3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7. +Related violations: + +NSTD-1#1 Warning +Unspecified I/O Standard +1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +Related violations: + +UCIO-1#1 Warning +Unconstrained Logical Port +1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +Related violations: + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx new file mode 100644 index 0000000..9c362c1 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb new file mode 100644 index 0000000..6c5ff57 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt new file mode 100644 index 0000000..0285501 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt @@ -0,0 +1,72 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:11 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx +| Design : Pipeline +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 5 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 | +| NSTD-1 | Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Warning | Unconstrained Logical Port | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +LUTLP-2#1 Warning +Combinatorial Loop Allowed +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. +Related violations: + +LUTLP-2#2 Warning +Combinatorial Loop Allowed +3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7. +Related violations: + +NSTD-1#1 Warning +Unspecified I/O Standard +1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +Related violations: + +UCIO-1#1 Warning +Unconstrained Logical Port +1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +Related violations: + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx new file mode 100644 index 0000000..f0b91c6 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt new file mode 100644 index 0000000..5d86e7e --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt @@ -0,0 +1,280 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:57:59 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_io -file Pipeline_io_placed.rpt +| Design : Pipeline +| Device : xc7a35t +| Speed File : -1 +| Package : cpg236 +| Package Version : FINAL 2014-02-19 +| Package Pin Delay Version : VERS. 2.0 2014-02-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 13 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| C15 | Clk | High Range | IO_L11P_T1_SRCC_16 | INPUT | LVCMOS18* | 16 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E19 | reg_val[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U14 | reg_val[6] | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U15 | reg_val[5] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U16 | reg_val[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | reg_val[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| V14 | reg_val[7] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | reg_addr[1] | High Range | IO_L19P_T3_A10_D26_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V17 | reg_addr[0] | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V19 | reg_val[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| W16 | reg_addr[2] | High Range | IO_L20P_T3_A08_D24_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W17 | reg_addr[3] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W18 | reg_val[4] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb new file mode 100644 index 0000000..793f977 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt new file mode 100644 index 0000000..b080d6b --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt @@ -0,0 +1,1751 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:13 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx +| Design : Pipeline +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 343 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 342 | +| TIMING-23 | Warning | Combinational loop found | 1 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[0][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[10][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[11][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[12][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[13][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[14][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[15][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#60 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#61 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#62 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#63 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#64 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[1][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#65 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#66 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#67 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#68 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#69 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#70 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#71 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#72 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[2][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#73 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#74 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#75 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#76 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#77 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#78 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#79 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#80 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[3][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#81 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#82 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#83 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#84 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#85 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#86 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#87 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#88 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[4][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#89 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#90 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#91 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#92 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#93 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#94 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#95 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#96 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[5][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#97 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#98 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#99 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#100 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#101 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#102 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#103 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#104 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[6][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#105 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#106 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#107 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#108 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#109 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#110 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#111 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#112 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[7][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#113 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#114 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#115 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#116 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#117 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#118 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#119 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#120 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[8][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#121 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#122 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#123 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#124 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#125 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#126 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#127 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#128 Warning +Non-clocked sequential cell +The clock pin DataMem/Mem_reg[9][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#129 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_A_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#130 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_A_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#131 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_A_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#132 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_A_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#133 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_B_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#134 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_B_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#135 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_B_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#136 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_B_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#137 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_B_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#138 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_C_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#139 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#140 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#141 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#142 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#143 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#144 Warning +Non-clocked sequential cell +The clock pin Stage1/Out_Op_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#145 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_A_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#146 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_A_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#147 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_A_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#148 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_A_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#149 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#150 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#151 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#152 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#153 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#154 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#155 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#156 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_B_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#157 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#158 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#159 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#160 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#161 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#162 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#163 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#164 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_C_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#165 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#166 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#167 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#168 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#169 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#170 Warning +Non-clocked sequential cell +The clock pin Stage2/Out_Op_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#171 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_A_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#172 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_A_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#173 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_A_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#174 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_A_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#175 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#176 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#177 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#178 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#179 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#180 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#181 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#182 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_B_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#183 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#184 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#185 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#186 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#187 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#188 Warning +Non-clocked sequential cell +The clock pin Stage3/Out_Op_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#189 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_A_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#190 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_A_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#191 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_A_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#192 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_A_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#193 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#194 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#195 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#196 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#197 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#198 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#199 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#200 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_B_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#201 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#202 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#203 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#204 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#205 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#206 Warning +Non-clocked sequential cell +The clock pin Stage4/Out_Op_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#207 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#208 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#209 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#210 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#211 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#212 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#213 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#214 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[0][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#215 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#216 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#217 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#218 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#219 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#220 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#221 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#222 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[10][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#223 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#224 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#225 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#226 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#227 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#228 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#229 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#230 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[11][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#231 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#232 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#233 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#234 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#235 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#236 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#237 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#238 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[12][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#239 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#240 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#241 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#242 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#243 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#244 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#245 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#246 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[13][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#247 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#248 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#249 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#250 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#251 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#252 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#253 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#254 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[14][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#255 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#256 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#257 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#258 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#259 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#260 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#261 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#262 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[15][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#263 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#264 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#265 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#266 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#267 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#268 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#269 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#270 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[1][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#271 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#272 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#273 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#274 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#275 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#276 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#277 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#278 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[2][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#279 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#280 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#281 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#282 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#283 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#284 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#285 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#286 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[3][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#287 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#288 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#289 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#290 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#291 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#292 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#293 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#294 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[4][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#295 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#296 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#297 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#298 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#299 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#300 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#301 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#302 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[5][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#303 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#304 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#305 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#306 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#307 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#308 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#309 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#310 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[6][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#311 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#312 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#313 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#314 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#315 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#316 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#317 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#318 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[7][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#319 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#320 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#321 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#322 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#323 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#324 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#325 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#326 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[8][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#327 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#328 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#329 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#330 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#331 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#332 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#333 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#334 Warning +Non-clocked sequential cell +The clock pin StageRegisters/Regs_reg[9][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#335 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#336 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#337 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#338 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#339 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#340 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#341 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#342 Warning +Non-clocked sequential cell +The clock pin inst_point/aux_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-23#1 Warning +Combinational loop found +A timing loop has been detected on a combinational path. A timing arc has been disabled between Stage2/Out_Op[5]_i_3/I1 and Stage2/Out_Op[5]_i_3/O to disable the timing loop +Related violations: + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx new file mode 100644 index 0000000..697143f Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp new file mode 100644 index 0000000..3a2fd63 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp new file mode 100644 index 0000000..1957ed2 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt new file mode 100644 index 0000000..057b164 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt @@ -0,0 +1,153 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:13 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx +| Design : Pipeline +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 3.334 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 3.253 | +| Device Static (W) | 0.081 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 68.3 | +| Junction Temperature (C) | 41.7 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 1.294 | 831 | --- | --- | +| LUT as Logic | 1.166 | 371 | 20800 | 1.78 | +| CARRY4 | 0.105 | 33 | 8150 | 0.40 | +| Register | 0.018 | 342 | 41600 | 0.82 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| F7/F8 Muxes | <0.001 | 19 | 32600 | 0.06 | +| Others | 0.000 | 13 | --- | --- | +| Signals | 1.154 | 691 | --- | --- | +| I/O | 0.804 | 13 | 106 | 12.26 | +| Static Power | 0.081 | | | | +| Total | 3.334 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 2.486 | 2.468 | 0.018 | +| Vccaux | 1.800 | 0.042 | 0.029 | 0.013 | +| Vcco33 | 3.300 | 0.223 | 0.222 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------------+-----------+ +| Name | Power (W) | ++------------------+-----------+ +| Pipeline | 3.253 | +| DataMem | 0.035 | +| Stage1 | 0.205 | +| Stage2 | 1.072 | +| Stage3 | 0.208 | +| Stage4 | 0.140 | +| StageRegisters | 0.099 | +| Ual | 0.165 | +| inst_point | 0.416 | ++------------------+-----------+ + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx new file mode 100644 index 0000000..1af5673 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb new file mode 100644 index 0000000..5a6b2ef Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb new file mode 100644 index 0000000..4c5b016 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt new file mode 100644 index 0000000..2d1d87b --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 914 : + # of nets not needing routing.......... : 221 : + # of internally routed nets........ : 221 : + # of routable nets..................... : 693 : + # of fully routed nets............. : 693 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp new file mode 100644 index 0000000..ff740c4 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt new file mode 100644 index 0000000..a9292b0 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:58:13 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation +| Design : Pipeline +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 342 register/latch pins with no clock driven by root clock pin: Clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 618 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 8 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 2 combinational loops in the design. (HIGH) + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx new file mode 100644 index 0000000..d313c26 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb new file mode 100644 index 0000000..3e7476f Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt new file mode 100644 index 0000000..392c7d5 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt @@ -0,0 +1,209 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 +| Date : Wed May 31 17:57:59 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb +| Design : Pipeline +| Device : 7a35tcpg236-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 371 | 0 | 20800 | 1.78 | +| LUT as Logic | 371 | 0 | 20800 | 1.78 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 342 | 0 | 41600 | 0.82 | +| Register as Flip Flop | 342 | 0 | 41600 | 0.82 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 19 | 0 | 16300 | 0.12 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 12 | Yes | Set | - | +| 330 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 158 | 0 | 8150 | 1.94 | +| SLICEL | 103 | 0 | | | +| SLICEM | 55 | 0 | | | +| LUT as Logic | 371 | 0 | 20800 | 1.78 | +| using O5 output only | 0 | | | | +| using O6 output only | 319 | | | | +| using O5 and O6 | 52 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 48 | 0 | 20800 | 0.23 | +| fully used LUT-FF pairs | 5 | | | | +| LUT-FF pairs with one unused LUT output | 42 | | | | +| LUT-FF pairs with one unused Flip Flop | 37 | | | | +| Unique Control Sets | 36 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 13 | 12 | 106 | 12.26 | +| IOB Master Pads | 6 | | | | +| IOB Slave Pads | 6 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 330 | Flop & Latch | +| LUT6 | 209 | LUT | +| LUT3 | 67 | LUT | +| LUT5 | 55 | LUT | +| LUT2 | 51 | LUT | +| LUT4 | 41 | LUT | +| CARRY4 | 33 | CarryLogic | +| MUXF7 | 19 | MuxFx | +| FDSE | 12 | Flop & Latch | +| OBUF | 8 | IO | +| IBUF | 5 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/VHDL/ALU/ALU.runs/impl_1/gen_run.xml b/VHDL/ALU/ALU.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..8005842 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/gen_run.xml @@ -0,0 +1,171 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/impl_1/htr.txt b/VHDL/ALU/ALU.runs/impl_1/htr.txt new file mode 100644 index 0000000..4c3500d --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +vivado -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/impl_1/init_design.pb b/VHDL/ALU/ALU.runs/impl_1/init_design.pb new file mode 100644 index 0000000..8ca3bfc Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/init_design.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/opt_design.pb b/VHDL/ALU/ALU.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..c2d41e5 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/opt_design.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/place_design.pb b/VHDL/ALU/ALU.runs/impl_1/place_design.pb new file mode 100644 index 0000000..a57c02b Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/place_design.pb differ diff --git a/VHDL/ALU/ALU.runs/synth_1/project.wdf b/VHDL/ALU/ALU.runs/impl_1/project.wdf similarity index 97% rename from VHDL/ALU/ALU.runs/synth_1/project.wdf rename to VHDL/ALU/ALU.runs/impl_1/project.wdf index 44c1bc3..279e5aa 100644 --- a/VHDL/ALU/ALU.runs/synth_1/project.wdf +++ b/VHDL/ALU/ALU.runs/impl_1/project.wdf @@ -13,7 +13,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3836:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313734:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 @@ -28,4 +28,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00 -eof:3805747332 +eof:1726599244 diff --git a/VHDL/ALU/ALU.runs/impl_1/route_design.pb b/VHDL/ALU/ALU.runs/impl_1/route_design.pb new file mode 100644 index 0000000..fa0cf95 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/route_design.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/rundef.js b/VHDL/ALU/ALU.runs/impl_1/rundef.js new file mode 100644 index 0000000..7dc8d03 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/rundef.js @@ -0,0 +1,44 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;"; +} else { + PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.bat b/VHDL/ALU/ALU.runs/impl_1/runme.bat new file mode 100644 index 0000000..8eb74b1 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.log b/VHDL/ALU/ALU.runs/impl_1/runme.log new file mode 100644 index 0000000..a508221 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/runme.log @@ -0,0 +1,471 @@ + +*** Running vivado + with args -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source Pipeline.tcl -notrace +Command: link_design -top Pipeline -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1e379f571 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e379f571 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 224c05fcb + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 237fe1223 + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 237fe1223 + +Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +Ending Logic Optimization Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 141d47eb5 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx +Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd + +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +Phase 1 Placer Initialization | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: e4604ef0 + +Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15cb247ff + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Phase 3 Detail Placement | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 112e53995 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 +Ending Placer Task | Checksum: 8268151a + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt +report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537 +INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs +Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437 +Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 77742d47 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 16523de4e + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 11b0f7581 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 97 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 +Phase 4 Rip-up And Reroute | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 +Phase 6 Post Hold Fix | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.153313 % + Global Horizontal Routing Utilization = 0.172046 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 14cade65a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16fad2baa + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427 +INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx +Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 6 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx +Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 6 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx +Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs +Command: write_bitstream -force Pipeline.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 6 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. +WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7. +WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./Pipeline.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368 +INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023... diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.sh b/VHDL/ALU/ALU.runs/impl_1/runme.sh new file mode 100755 index 0000000..877ede8 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin +else + PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace + + diff --git a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..ce67df4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,867 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedWed May 31 17:58:23 2023os_platformLIN64
product_versionVivado v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration12random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-9500 CPU @ 3.00GHzcpu_speed3000.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_handlers
abstractcombinedpanel_add_element=36abstractcombinedpanel_remove_selected_elements=13abstractfileview_close=1abstractfileview_reload=1
addsrcwizard_specify_hdl_netlist_block_design=1addsrcwizard_specify_or_create_constraint_files=4addsrcwizard_specify_simulation_specific_hdl_files=3basedialog_apply=2
basedialog_cancel=31basedialog_no=2basedialog_ok=234basedialog_yes=40
clockcreationpanel_clock_name=1clockcreationpanel_enter_positive_number=5cmdmsgdialog_messages=6cmdmsgdialog_ok=33
cmdmsgdialog_open_messages_view=1combinationalconstraintstablepanel_table=1commandsinput_type_tcl_command_here=4constraintschooserpanel_add_existing_or_create_new_constraints=5
constraintschooserpanel_add_files=4constraintschooserpanel_create_file=4constraintschooserpanel_file_table=2createconstraintsfilepanel_file_name=3
createrunreportdialog_report_name=1createsrcfiledialog_file_name=15createsrcfiledialog_file_type=1definemodulesdialog_define_modules_and_specify_io_ports=148
definemodulesdialog_entity_name=3editcreateclocktablepanel_edit_create_clock_table=13expreporttreepanel_edit_report_options=1expreporttreepanel_exp_report_tree_table=9
expruntreepanel_exp_run_tree_table=2filesetpanel_file_set_panel_tree=606filesetpanel_messages=1flownavigatortreepanel_flow_navigator_tree=374
gettingstartedview_create_new_project=1gettingstartedview_open_project=3graphicalview_zoom_fit=6graphicalview_zoom_in=135
graphicalview_zoom_out=149hcodeeditor_close=2hcodeeditor_search_text_combo_box=40hinputhandler_toggle_line_comments=1
hpopuptitle_close=1inputoutputtablepanel_table=1logmonitor_monitor=1logpanel_copy=1
logpanel_find=1logpanel_pause_output=2logpanel_toggle_column_selection_mode=2mainmenumgr_checkpoint=18
mainmenumgr_edit=16mainmenumgr_export=7mainmenumgr_file=76mainmenumgr_flow=10
mainmenumgr_io_planning=1mainmenumgr_ip=12mainmenumgr_open_recent_project=25mainmenumgr_project=51
mainmenumgr_reports=12mainmenumgr_settings=2mainmenumgr_simulation_waveform=15mainmenumgr_text_editor=10
mainmenumgr_timing=1mainmenumgr_tools=16mainmenumgr_unselect_type=1mainmenumgr_view=8
mainmenumgr_window=16maintoolbarmgr_run=7mainwinmenumgr_layout=12mainwinmenumgr_load=1
messagewithoptiondialog_dont_show_this_dialog_again=1msgtreepanel_message_severity=1msgtreepanel_message_view_tree=172msgview_clear_messages_resulting_from_user_executed=9
msgview_critical_warnings=2msgview_error_messages=2msgview_information_messages=3msgview_warning_messages=1
navigabletimingreporttab_timing_report_navigation_tree=5numjobschooser_number_of_jobs=2openfileaction_cancel=2openfileaction_open_directory=4
opentargetwizard_connect_to=3packagetreepanel_package_tree_panel=5pacommandnames_add_config_memory=3pacommandnames_add_sources=21
pacommandnames_auto_connect_target=2pacommandnames_auto_update_hier=26pacommandnames_fileset_window=3pacommandnames_goto_instantiation=1
pacommandnames_log_window=10pacommandnames_open_project=1pacommandnames_open_recent_target=3pacommandnames_open_target_wizard=4
pacommandnames_program_fpga=4pacommandnames_report_clock_networks=1pacommandnames_reports_window=5pacommandnames_run_bitgen=1
pacommandnames_run_synthesis=3pacommandnames_set_as_top=6pacommandnames_set_target_ucf=3pacommandnames_simulation_relaunch=5
pacommandnames_simulation_reset=1pacommandnames_simulation_run=1pacommandnames_simulation_run_behavioral=174pacommandnames_simulation_run_post_synthesis_functional=1
pacommandnames_simulation_settings=9pacommandnames_src_replace_file=5paviews_code=41paviews_device=3
paviews_project_summary=2planaheadtab_show_flow_navigator=4primaryclockspanel_recommended_constraints_table=6programdebugtab_open_recently_opened_target=13
programdebugtab_open_target=2programdebugtab_refresh_device=1programfpgadialog_check_end_of_startup=1programfpgadialog_program=12
programfpgadialog_specify_bitstream_file=2progressdialog_background=16progressdialog_cancel=1projectsettingsgadget_edit_project_settings=2
projectsettingssimulationpanel_select_testbench_top_module=2projectsettingssimulationpanel_tabbed_pane=7projecttab_close_design=4projecttab_reload=7
rdicommands_custom_commands=4rdicommands_delete=5rdicommands_line_comment=23rdicommands_save_file=10
rdiviews_waveform_viewer=787removesourcesdialog_also_delete=1reportnavigationholder_rerun=2rtloptionspanel_select_top_module_of_your_design=2
rungadget_show_error_and_critical_warning_messages=1saveprojectutils_cancel=1saveprojectutils_save=46selecttopmoduledialog_select_top_module=8
settingsdialog_project_tree=1signaltreepanel_signal_tree_table=13simulationobjectspanel_simulation_objects_tree_table=55simulationscopespanel_simulate_scope_table=80
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=4srcchooserpanel_add_or_create_source_file=21srcchooserpanel_create_file=15srcchoosertable_src_chooser_table=2
srcmenu_ip_hierarchy=26srcmenu_refresh_hierarchy=2stalerundialog_yes=2statemonitor_reset_run=3
syntheticagettingstartedview_recent_projects=8syntheticastatemonitor_cancel=8taskbanner_close=6tclconsoleview_clear_all_output_in_tcl_console=3
tclconsoleview_tcl_console_code_editor=50timingconstraintswizard_create_check_timing_report=6timingconstraintswizard_create_methodology_report=2timingconstraintswizard_create_timing_summary_report=6
timingconstraintswizard_goto_constraints_summary_page=4timingconstraintswizard_view_timing_constraints=6touchpointsurveydialog_no=1waveformnametree_waveform_name_tree=275
waveformoptionsview_reset_to_defaults=1waveformoptionsview_show_signal_indices=4waveformview_add_marker=4waveformview_goto_last_time=4
waveformview_goto_time_0=3waveformview_next_marker=3xdceditorview_apply_all_changes_to_xdc_constraints=2xdcviewertreetablepanel_xdc_viewer_tree_table=4
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
java_command_handlers
addcfgmem=1addsources=24autoconnecttarget=2closeproject=2
editdelete=5editpaste=5editundo=1launchopentarget=4
launchprogramfpga=15newproject=1openhardwaremanager=24openproject=4
openrecenttarget=14programdevice=18reporttimingsummary=1runbitgen=47
runimplementation=6runsynthesis=22savefileproxyhandler=4settargetconstrfile=3
settopnode=1showsource=1showview=53simulationrelaunch=5
simulationrun=172timingconstraintswizard=7toggleviewnavigator=4toolssettings=15
updatesourcefiles=5viewlayoutcmd=1viewtaskimplementation=4viewtasksynthesis=1
waveformsaveconfiguration=13xdccreateclock=1
+ + + +
other_data
guimode=24
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=174simulator_language=Mixedsrcsetcount=11synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDLtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1carry4=33fdre=330fdse=12
gnd=8ibuf=5lut2=51lut3=67
lut4=41lut5=55lut6=209muxf7=19
obuf=8vcc=5
+
+ + + + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1carry4=33fdre=330fdse=12
gnd=8ibuf=5lut2=51lut3=67
lut4=41lut5=55lut6=209muxf7=19
obuf=8vcc=5
+

+ + + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + + + +
results
cfgbvs-1=1lutlp-2=2nstd-1=1ucio-1=1
+
+ + + + +
usage
nstd-1=Warningucio-1=Warning
+

+ + + + + +
report_methodology
+ + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
+
+ + + + +
results
timing-17=342timing-23=1
+
+ + + + +
usage
nstd-1=Warningucio-1=Warning
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.081472die=xc7a35tcpg236-1
dsp_output_toggle=12.500000dynamic=3.252769effective_thetaja=5.0enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=0.804337input_toggle=12.500000junction_temp=41.7 (C)logic=1.293960
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=3.334241output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=cpg236pct_clock_constrained=0.860000
pct_inputs_defined=0platform=lin64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=1.154472simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=7.5 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=5.0user_junc_temp=41.7 (C)user_thetajb=7.5 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.028741vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.013356vccaux_total_current=0.042097
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000299vccbram_total_current=0.000299
vccbram_voltage=1.000000vccint_dynamic_current=2.468432vccint_static_current=0.017832vccint_total_current=2.486264
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=0.222001vcco33_static_current=0.001000vcco33_total_current=0.223001
vcco33_voltage=3.300000version=2018.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=90dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=1lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1carry4_functional_category=CarryLogiccarry4_used=33
fdre_functional_category=Flop & Latchfdre_used=330fdse_functional_category=Flop & Latchfdse_used=12
ibuf_functional_category=IOibuf_used=5lut2_functional_category=LUTlut2_used=51
lut3_functional_category=LUTlut3_used=67lut4_functional_category=LUTlut4_used=41
lut5_functional_category=LUTlut5_used=55lut6_functional_category=LUTlut6_used=209
muxf7_functional_category=MuxFxmuxf7_used=19obuf_functional_category=IOobuf_used=8
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=19f7_muxes_util_percentage=0.12
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=371lut_as_logic_util_percentage=1.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=342register_as_flip_flop_util_percentage=0.82
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=371slice_luts_util_percentage=1.78
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=342slice_registers_util_percentage=0.82
fully_used_lut_ff_pairs_fixed=0.82fully_used_lut_ff_pairs_used=5lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=371lut_as_logic_util_percentage=1.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=37
lut_ff_pairs_with_one_unused_lut_output_fixed=37lut_ff_pairs_with_one_unused_lut_output_used=42lut_flip_flop_pairs_available=20800lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=48lut_flip_flop_pairs_util_percentage=0.23slice_available=8150slice_fixed=0
slice_used=158slice_util_percentage=1.94slicel_fixed=0slicel_used=103
slicem_fixed=0slicem_used=55unique_control_sets_used=36using_o5_and_o6_fixed=36
using_o5_and_o6_used=52using_o5_output_only_fixed=52using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=319
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=336796bogomips=6000bram18=0bram36=0
bufg=0bufr=0ctrls=36dsp=0
effort=2estimated_expansions=475116ff=342global_clocks=1
high_fanout_nets=0iob=13lut=371movable_instances=844
nets=925pins=4840pll=0router_runtime=0.000000
router_timing_driven=1threads=6timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a35tcpg236-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=Pipeline-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:23shls_ip=0memory_gain=491.398MBmemory_peak=1651.219MB
+

+ + + +
xsim
+ + + + +
command_line_options
-sim_mode=default::behavioral-sim_type=default::
+

+ + diff --git a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..65eff10 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,790 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + +
+
+ + + + +
+
+ + +
+
+
+
+ + + + + + + + + +
+
+ + +
+
+ + +
+
+
+
+ + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + +
+
+
+ diff --git a/VHDL/ALU/ALU.runs/impl_1/vivado.jou b/VHDL/ALU/ALU.runs/impl_1/vivado.jou new file mode 100644 index 0000000..52cab70 --- /dev/null +++ b/VHDL/ALU/ALU.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed May 31 17:57:08 2023 +# Process ID: 144223 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1 +# Command line: vivado -log Pipeline.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/impl_1/vivado.pb b/VHDL/ALU/ALU.runs/impl_1/vivado.pb new file mode 100644 index 0000000..d3f674c Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/vivado.pb differ diff --git a/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb b/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..63ae9a4 Binary files /dev/null and b/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb differ diff --git a/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc b/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc new file mode 100644 index 0000000..252a926 --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc @@ -0,0 +1,31 @@ +set_property SRC_FILE_INFO {cfile:/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc rfile:../../../ALU.srcs/constrs_1/new/test_cpu.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports CLK] +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports CLK] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets {Stage2/Jump_Flag}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[0]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[1]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[2]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[3]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {reg_val[0]}] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {reg_val[1]}] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {reg_val[2]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {reg_val[3]}] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {reg_val[4]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {reg_val[5]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {reg_val[6]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {reg_val[7]}] diff --git a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst b/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst index 60b7b62..7836eeb 100644 --- a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst +++ b/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp b/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp index 2f2fd84..a133e7e 100644 Binary files a/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp and b/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp differ diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl b/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl index f78754c..0ca503b 100644 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl +++ b/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl @@ -17,6 +17,7 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } +set_param xicom.use_bs_reader 1 create_project -in_memory -part xc7a35tcpg236-1 set_param project.singleFileAddWarning.threshold 0 @@ -50,8 +51,8 @@ read_vhdl -library xil_defaultlib { foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc -set_property used_in_implementation false [get_files /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc +set_property used_in_implementation false [get_files /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] set_param ips.enableIPCacheLiteLoad 0 close [open __synthesis_is_running__ w] diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds b/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds index 0e8305f..796a1fd 100644 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds +++ b/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds @@ -2,8 +2,8 @@ # Vivado v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 09:12:59 2023 -# Process ID: 10840 +# Start of session at: Wed May 31 17:56:19 2023 +# Process ID: 144089 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds @@ -15,46 +15,46 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 10853 +INFO: Helper process launched with PID 144101 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.828 ; free physical = 7354 ; free virtual = 19137 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] +INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:182] INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] +INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:192] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] +INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:198] INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] +INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:210] +INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] +INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] +INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:224] INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] +INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:236] +INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] +WARNING: [Synth 8-614] signal 'JumpFlagIn' is read in the process but is not in the sensitivity list [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:68] +INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] +INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:249] INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] +INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:268] INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] +INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:339] INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] -WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] +WARNING: [Synth 8-3331] design InstructionMemory has unconnected port Clk --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7345 ; free virtual = 19128 --------------------------------------------------------------------------------- Report Check Netlist: @@ -63,46 +63,54 @@ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ -WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'Stage2/Jump_Flag'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Pipeline_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Pipeline_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000 ; free physical = 7109 ; free virtual = 18892 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) @@ -221,9 +229,8 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7161 ; free virtual = 18945 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -240,11 +247,10 @@ Detailed RTL Component Info : 2 Input 8 Bit Adders := 2 3 Input 8 Bit Adders := 1 +---Registers : - 32 Bit Registers := 1 - 8 Bit Registers := 288 + 8 Bit Registers := 287 +---Muxes : 257 Input 32 Bit Muxes := 1 - 2 Input 8 Bit Muxes := 8 + 2 Input 8 Bit Muxes := 13 2 Input 1 Bit Muxes := 279 12 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- @@ -257,8 +263,8 @@ Hierarchical RTL Component report Module Pipeline Detailed RTL Component Info : +---Muxes : - 2 Input 8 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 7 + 2 Input 1 Bit Muxes := 1 Module IP Detailed RTL Component Info : +---Adders : @@ -270,8 +276,6 @@ Detailed RTL Component Info : 2 Input 1 Bit Muxes := 1 Module InstructionMemory Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 1 +---Muxes : 257 Input 32 Bit Muxes := 1 Module Stage_Li_Di @@ -283,7 +287,7 @@ Detailed RTL Component Info : +---Registers : 8 Bit Registers := 16 +---Muxes : - 2 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 3 2 Input 1 Bit Muxes := 16 Module Stage_Di_Ex Detailed RTL Component Info : @@ -297,7 +301,7 @@ Detailed RTL Component Info : 2 Input 8 Bit Adders := 1 +---Muxes : 2 Input 8 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 4 + 2 Input 1 Bit Muxes := 5 12 Input 1 Bit Muxes := 3 Module Stage_Ex_Mem Detailed RTL Component Info : @@ -306,7 +310,7 @@ Detailed RTL Component Info : Module DataMemory Detailed RTL Component Info : +---Registers : - 8 Bit Registers := 257 + 8 Bit Registers := 256 +---Muxes : 2 Input 1 Bit Muxes := 256 Module Stage_Mem_Re @@ -331,109 +335,125 @@ Start Cross Boundary and Area Optimization Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. -INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[5]' (FD) to 'Stage1/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[7]' (FD) to 'Stage1/Out_Op_reg[6]' +INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[6]' (FD) to 'Stage2/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[7]' (FD) to 'Stage2/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[6]' (FD) to 'Stage3/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[7]' (FD) to 'Stage3/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[6]' (FD) to 'Stage4/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[7]' (FD) to 'Stage4/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[46][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[47][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[44][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[45][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[42][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[43][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[40][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[41][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[38][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[39][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[36][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[37][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[34][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[35][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[32][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[33][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[62][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[63][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[60][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[61][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[58][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[59][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[56][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[57][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[54][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[55][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[52][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[53][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[50][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[51][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[48][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[49][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[30][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[31][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[28][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[29][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[26][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[27][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[24][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[25][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[22][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[23][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[20][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[21][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[18][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[19][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[16][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[17][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[238][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[239][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[236][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[237][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[234][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[235][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[232][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[233][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[230][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[231][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[228][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[229][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[226][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[227][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[224][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[225][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[254][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[255][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[252][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[253][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[250][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[251][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[248][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[249][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[246][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[247][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[244][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[245][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[242][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[243][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[240][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[241][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[206][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[207][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[204][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[205][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[202][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[203][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[200][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[201][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[198][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[199][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[196][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[197][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[153][7] ) +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][0]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][1]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][2]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][3]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][4]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][5]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][6]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[153][7]) is unused and will be removed from module Pipeline. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7123 ; free virtual = 18911 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -445,13 +465,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18798 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -463,7 +483,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -487,7 +507,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report Check Netlist: @@ -500,7 +520,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -512,25 +532,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -543,35 +563,57 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+-+-----+------+ -| |Cell |Count | -+-+-----+------+ -+-+-----+------+ ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 33| +|3 |LUT2 | 51| +|4 |LUT3 | 67| +|5 |LUT4 | 41| +|6 |LUT5 | 55| +|7 |LUT6 | 209| +|8 |MUXF7 | 19| +|9 |FDRE | 330| +|10 |FDSE | 12| +|11 |IBUF | 5| +|12 |OBUF | 8| ++------+-------+------+ Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 0| -+------+---------+-------+------+ ++------+-----------------+-------------+------+ +| |Instance |Module |Cells | ++------+-----------------+-------------+------+ +|1 |top | | 831| +|2 | DataMem |DataMemory | 168| +|3 | Stage1 |Stage_Li_Di | 35| +|4 | Stage2 |Stage_Di_Ex | 213| +|5 | Stage3 |Stage_Ex_Mem | 63| +|6 | Stage4 |Stage_Mem_Re | 37| +|7 | StageRegisters |Registers | 230| +|8 | Ual |ALU | 35| +|9 | inst_point |IP | 36| ++------+-----------------+-------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336 -Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340 +Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1651.219 ; gain = 139.453 ; free physical = 7056 ; free virtual = 18845 +Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7056 ; free virtual = 18845 INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. +270 Infos, 15 Warnings, 3 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322 +synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 1659.227 ; gain = 499.406 ; free physical = 7043 ; free virtual = 18832 WARNING: [Constraints 18-5210] No constraint will be written out. INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306 -INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023... +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1683.238 ; gain = 0.000 ; free physical = 7046 ; free virtual = 18834 +INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:57:07 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb index a29faa5..3e7476f 100644 Binary files a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb and b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb differ diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt index d935c8b..f247b36 100644 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt +++ b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt @@ -1,12 +1,12 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Tue May 30 09:13:39 2023 -| Host : insa-11267 running 64-bit Ubuntu 20.04.6 LTS +| Date : Wed May 31 17:57:07 2023 +| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb | Design : Pipeline | Device : 7a35tcpg236-1 -| Design State : Fully Placed +| Design State : Synthesized ----------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -15,15 +15,14 @@ Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists 1. Slice Logic -------------- @@ -31,15 +30,16 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 0 | 0 | 20800 | 0.00 | -| LUT as Logic | 0 | 0 | 20800 | 0.00 | +| Slice LUTs* | 371 | 0 | 20800 | 1.78 | +| LUT as Logic | 371 | 0 | 20800 | 1.78 | | LUT as Memory | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 0 | 0 | 41600 | 0.00 | -| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Slice Registers | 342 | 0 | 41600 | 0.82 | +| Register as Flip Flop | 342 | 0 | 41600 | 0.82 | | Register as Latch | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F7 Muxes | 19 | 0 | 16300 | 0.12 | | F8 Muxes | 0 | 0 | 8150 | 0.00 | +-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type @@ -56,31 +56,12 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 0 | Yes | Reset | - | +| 12 | Yes | Set | - | +| 330 | Yes | Reset | - | +-------+--------------+-------------+--------------+ -2. Slice Logic Distribution ---------------------------- - -+--------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------+------+-------+-----------+-------+ -| Slice | 0 | 0 | 8150 | 0.00 | -| SLICEL | 0 | 0 | | | -| SLICEM | 0 | 0 | | | -| LUT as Logic | 0 | 0 | 20800 | 0.00 | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | -| Unique Control Sets | 0 | | | | -+--------------------------+------+-------+-----------+-------+ -* Note: Review the Control Sets Report for more information regarding control sets. - - -3. Memory +2. Memory --------- +----------------+------+-------+-----------+-------+ @@ -93,7 +74,7 @@ Table of Contents * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 -4. DSP +3. DSP ------ +-----------+------+-------+-----------+-------+ @@ -103,13 +84,13 @@ Table of Contents +-----------+------+-------+-----------+-------+ -5. IO and GT Specific +4. IO and GT Specific --------------------- +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 106 | 0.00 | +| Bonded IOB | 13 | 0 | 106 | 12.26 | | Bonded IPADs | 0 | 0 | 10 | 0.00 | | Bonded OPADs | 0 | 0 | 4 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | @@ -128,13 +109,13 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ -6. Clocking +5. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFGCTRL | 1 | 0 | 32 | 3.13 | | BUFIO | 0 | 0 | 20 | 0.00 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 | @@ -144,7 +125,7 @@ Table of Contents +------------+------+-------+-----------+-------+ -7. Specific Feature +6. Specific Feature ------------------- +-------------+------+-------+-----------+-------+ @@ -162,15 +143,28 @@ Table of Contents +-------------+------+-------+-----------+-------+ -8. Primitives +7. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ +| FDRE | 330 | Flop & Latch | +| LUT6 | 209 | LUT | +| LUT3 | 67 | LUT | +| LUT5 | 55 | LUT | +| LUT2 | 51 | LUT | +| LUT4 | 41 | LUT | +| CARRY4 | 33 | CarryLogic | +| MUXF7 | 19 | MuxFx | +| FDSE | 12 | Flop & Latch | +| OBUF | 8 | IO | +| IBUF | 5 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ -9. Black Boxes +8. Black Boxes -------------- +----------+------+ @@ -178,8 +172,8 @@ Table of Contents +----------+------+ -10. Instantiated Netlists -------------------------- +9. Instantiated Netlists +------------------------ +----------+------+ | Ref Name | Used | diff --git a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml index 43a1ea5..2247bbd 100644 --- a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml +++ b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml @@ -1,11 +1,14 @@ - - - - + + + + + + + @@ -82,14 +85,14 @@ - + - diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.log b/VHDL/ALU/ALU.runs/synth_1/runme.log index 3e75e98..f824df8 100644 --- a/VHDL/ALU/ALU.runs/synth_1/runme.log +++ b/VHDL/ALU/ALU.runs/synth_1/runme.log @@ -14,46 +14,46 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 10853 +INFO: Helper process launched with PID 144101 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.699 ; free physical = 57815 ; free virtual = 69577 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.828 ; free physical = 7354 ; free virtual = 19137 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] +INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] +INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:182] INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187] +INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:192] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193] +INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:198] INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217] +INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:210] +INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] +INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] +INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:224] INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240] +INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:236] +INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] +WARNING: [Synth 8-614] signal 'JumpFlagIn' is read in the process but is not in the sensitivity list [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:68] +INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] +INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:249] INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] +INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] +INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:268] INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329] +INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:339] INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50] -WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38] +INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] +WARNING: [Synth 8-3331] design InstructionMemory has unconnected port Clk --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57806 ; free virtual = 69569 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7345 ; free virtual = 19128 --------------------------------------------------------------------------------- Report Check Netlist: @@ -62,46 +62,54 @@ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ -WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177] -WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205] -WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1313.898 ; gain = 142.324 ; free physical = 57814 ; free virtual = 69577 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc] +Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'Stage2/Jump_Flag'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Pipeline_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Pipeline_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57555 ; free virtual = 69319 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000 ; free physical = 7109 ; free virtual = 18892 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcpg236-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57631 ; free virtual = 69396 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) @@ -220,9 +228,8 @@ INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57618 ; free virtual = 69383 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7161 ; free virtual = 18945 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -239,11 +246,10 @@ Detailed RTL Component Info : 2 Input 8 Bit Adders := 2 3 Input 8 Bit Adders := 1 +---Registers : - 32 Bit Registers := 1 - 8 Bit Registers := 288 + 8 Bit Registers := 287 +---Muxes : 257 Input 32 Bit Muxes := 1 - 2 Input 8 Bit Muxes := 8 + 2 Input 8 Bit Muxes := 13 2 Input 1 Bit Muxes := 279 12 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- @@ -256,8 +262,8 @@ Hierarchical RTL Component report Module Pipeline Detailed RTL Component Info : +---Muxes : - 2 Input 8 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 7 + 2 Input 1 Bit Muxes := 1 Module IP Detailed RTL Component Info : +---Adders : @@ -269,8 +275,6 @@ Detailed RTL Component Info : 2 Input 1 Bit Muxes := 1 Module InstructionMemory Detailed RTL Component Info : -+---Registers : - 32 Bit Registers := 1 +---Muxes : 257 Input 32 Bit Muxes := 1 Module Stage_Li_Di @@ -282,7 +286,7 @@ Detailed RTL Component Info : +---Registers : 8 Bit Registers := 16 +---Muxes : - 2 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 3 2 Input 1 Bit Muxes := 16 Module Stage_Di_Ex Detailed RTL Component Info : @@ -296,7 +300,7 @@ Detailed RTL Component Info : 2 Input 8 Bit Adders := 1 +---Muxes : 2 Input 8 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 4 + 2 Input 1 Bit Muxes := 5 12 Input 1 Bit Muxes := 3 Module Stage_Ex_Mem Detailed RTL Component Info : @@ -305,7 +309,7 @@ Detailed RTL Component Info : Module DataMemory Detailed RTL Component Info : +---Registers : - 8 Bit Registers := 257 + 8 Bit Registers := 256 +---Muxes : 2 Input 1 Bit Muxes := 256 Module Stage_Mem_Re @@ -330,109 +334,125 @@ Start Cross Boundary and Area Optimization Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][7]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline. -INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[5]' (FD) to 'Stage1/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[7]' (FD) to 'Stage1/Out_Op_reg[6]' +INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[6]' (FD) to 'Stage2/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[7]' (FD) to 'Stage2/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[6]' (FD) to 'Stage3/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[7]' (FD) to 'Stage3/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[6]' (FD) to 'Stage4/Out_Op_reg[7]' +INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[7]' (FD) to 'Stage4/Out_Op_reg[5]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[46][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[47][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[44][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[45][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[42][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[43][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[40][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[41][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[38][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[39][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[36][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[37][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[34][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[35][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[32][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[33][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[62][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[63][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[60][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[61][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[58][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[59][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[56][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[57][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[54][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[55][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[52][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[53][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[50][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[51][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[48][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[49][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[30][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[31][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[28][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[29][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[26][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[27][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[24][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[25][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[22][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[23][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[20][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[21][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[18][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[19][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[16][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[17][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[238][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[239][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[236][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[237][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[234][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[235][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[232][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[233][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[230][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[231][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[228][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[229][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[226][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[227][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[224][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[225][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[254][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[255][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[252][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[253][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[250][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[251][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[248][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[249][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[246][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[247][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[244][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[245][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[242][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[243][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[240][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[241][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[206][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[207][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[204][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[205][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[202][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[203][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[200][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[201][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[198][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[199][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[196][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[197][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[153][7] ) +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][0]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][1]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][2]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][3]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][4]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][5]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][6]) is unused and will be removed from module Pipeline. +WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[153][7]) is unused and will be removed from module Pipeline. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57609 ; free virtual = 69379 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7123 ; free virtual = 18911 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -444,13 +464,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18798 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -462,7 +482,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:31 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57516 ; free virtual = 69285 +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -486,7 +506,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report Check Netlist: @@ -499,7 +519,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -511,25 +531,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -542,35 +562,57 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+-+-----+------+ -| |Cell |Count | -+-+-----+------+ -+-+-----+------+ ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 33| +|3 |LUT2 | 51| +|4 |LUT3 | 67| +|5 |LUT4 | 41| +|6 |LUT5 | 55| +|7 |LUT6 | 209| +|8 |MUXF7 | 19| +|9 |FDRE | 330| +|10 |FDSE | 12| +|11 |IBUF | 5| +|12 |OBUF | 8| ++------+-------+------+ Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 0| -+------+---------+-------+------+ ++------+-----------------+-------------+------+ +| |Instance |Module |Cells | ++------+-----------------+-------------+------+ +|1 |top | | 831| +|2 | DataMem |DataMemory | 168| +|3 | Stage1 |Stage_Li_Di | 35| +|4 | Stage2 |Stage_Di_Ex | 213| +|5 | Stage3 |Stage_Ex_Mem | 63| +|6 | Stage4 |Stage_Mem_Re | 37| +|7 | StageRegisters |Registers | 230| +|8 | Ual |ALU | 35| +|9 | inst_point |IP | 36| ++------+-----------------+-------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57515 ; free virtual = 69285 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2331 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1673.281 ; gain = 142.324 ; free physical = 57567 ; free virtual = 69336 -Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 501.707 ; free physical = 57570 ; free virtual = 69340 +Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1651.219 ; gain = 139.453 ; free physical = 7056 ; free virtual = 18845 +Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7056 ; free virtual = 18845 INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. +270 Infos, 15 Warnings, 3 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 1673.281 ; gain = 513.461 ; free physical = 57552 ; free virtual = 69322 +synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 1659.227 ; gain = 499.406 ; free physical = 7043 ; free virtual = 18832 WARNING: [Constraints 18-5210] No constraint will be written out. INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1673.281 ; gain = 0.000 ; free physical = 57537 ; free virtual = 69306 -INFO: [Common 17-206] Exiting Vivado at Tue May 30 09:13:40 2023... +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1683.238 ; gain = 0.000 ; free physical = 7046 ; free virtual = 18834 +INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:57:07 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.jou b/VHDL/ALU/ALU.runs/synth_1/vivado.jou index 6074572..8c57bba 100644 --- a/VHDL/ALU/ALU.runs/synth_1/vivado.jou +++ b/VHDL/ALU/ALU.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 09:12:59 2023 -# Process ID: 10840 +# Start of session at: Wed May 31 17:56:19 2023 +# Process ID: 144089 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 # Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.pb b/VHDL/ALU/ALU.runs/synth_1/vivado.pb index d51d0f6..e50866e 100644 Binary files a/VHDL/ALU/ALU.runs/synth_1/vivado.pb and b/VHDL/ALU/ALU.runs/synth_1/vivado.pb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb index 69e344e..c62301b 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log index 8b4909e..abd0c43 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log @@ -390,3 +390,39 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Pro INFO: [VRFC 10-307] analyzing entity InstructionMemory INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity InstructionMemory +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_total +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Registers +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AleaControler +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh index e677e93..5525f79 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Tue May 30 16:24:18 CEST 2023 +# Generated by Vivado on Wed May 31 18:24:50 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log index 93de205..e0fb715 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log @@ -4,4 +4,25 @@ Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab Using 8 slave threads. Starting static elaboration Completed static elaboration -INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.std_logic_arith +Compiling package ieee.std_logic_unsigned +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default] +Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default] +Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default] +Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default] +Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default] +Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default] +Compiling architecture behavioral of entity xil_defaultlib.AleaControler [aleacontroler_default] +Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default] +Compiling architecture behavioral of entity xil_defaultlib.test_total +Built simulation snapshot Test_total_behav diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh index 62a1c82..06902b4 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Tue May 30 16:24:19 CEST 2023 +# Generated by Vivado on Wed May 31 18:24:52 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log index e69de29..2cc3412 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh index 3243763..bc7c372 100755 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : Xilinx Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Tue May 30 16:24:20 CEST 2023 +# Generated by Vivado on Wed May 31 18:24:54 CEST 2023 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou index 00a9a20..4f85255 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:34 2023 -# Process ID: 5876 +# Start of session at: Wed May 31 16:13:36 2023 +# Process ID: 12761 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou #----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log index 1837e58..0df3749 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log @@ -2,12 +2,12 @@ # Webtalk v2018.2 (64-bit) # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:34 2023 -# Process ID: 5876 +# Start of session at: Wed May 31 16:13:36 2023 +# Process ID: 12761 # Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log # Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou #----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:35 2023... +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed May 31 16:13:37 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou new file mode 100644 index 0000000..e8fe47e --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed May 31 16:08:55 2023 +# Process ID: 2956 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log new file mode 100644 index 0000000..4572683 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed May 31 16:08:55 2023 +# Process ID: 2956 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed May 31 16:08:56 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou deleted file mode 100644 index 7eeb0ee..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Fri May 12 18:00:54 2023 -# Process ID: 31637 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log deleted file mode 100644 index 266b444..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Fri May 12 18:00:54 2023 -# Process ID: 31637 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:00:55 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou deleted file mode 100644 index 680239c..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Fri May 12 18:03:10 2023 -# Process ID: 32017 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log deleted file mode 100644 index ac35d6b..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Fri May 12 18:03:10 2023 -# Process ID: 32017 -# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:03:11 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou new file mode 100644 index 0000000..00a9a20 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue May 30 08:48:34 2023 +# Process ID: 5876 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log new file mode 100644 index 0000000..1837e58 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue May 30 08:48:34 2023 +# Process ID: 5876 +# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:35 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb index 3020a60..10c3cab 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o index 5b1f105..a697b16 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c index c0f17e4..903aeed 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c @@ -43,18 +43,18 @@ #define alloca _alloca #endif typedef void (*funcp)(char *, char *); -extern void execute_93(char*, char *); -extern void execute_80(char*, char *); +extern void execute_94(char*, char *); extern void execute_81(char*, char *); extern void execute_82(char*, char *); extern void execute_83(char*, char *); extern void execute_84(char*, char *); extern void execute_85(char*, char *); extern void execute_86(char*, char *); -extern void execute_89(char*, char *); +extern void execute_87(char*, char *); extern void execute_90(char*, char *); extern void execute_91(char*, char *); extern void execute_92(char*, char *); +extern void execute_93(char*, char *); extern void execute_53(char*, char *); extern void execute_54(char*, char *); extern void execute_60(char*, char *); @@ -62,25 +62,26 @@ extern void execute_62(char*, char *); extern void execute_64(char*, char *); extern void execute_65(char*, char *); extern void execute_66(char*, char *); -extern void execute_68(char*, char *); -extern void execute_70(char*, char *); +extern void execute_67(char*, char *); +extern void execute_69(char*, char *); extern void execute_71(char*, char *); extern void execute_72(char*, char *); -extern void execute_74(char*, char *); -extern void execute_76(char*, char *); +extern void execute_73(char*, char *); +extern void execute_75(char*, char *); extern void execute_77(char*, char *); -extern void execute_79(char*, char *); -extern void execute_88(char*, char *); +extern void execute_78(char*, char *); +extern void execute_80(char*, char *); +extern void execute_89(char*, char *); extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[30] = {(funcp)execute_93, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_68, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_74, (funcp)execute_76, (funcp)execute_77, (funcp)execute_79, (funcp)execute_88, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 30; +funcp funcTab[31] = {(funcp)execute_94, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_69, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_75, (funcp)execute_77, (funcp)execute_78, (funcp)execute_80, (funcp)execute_89, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 31; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 30); - iki_vhdl_file_variable_register(dp + 24448); - iki_vhdl_file_variable_register(dp + 24504); + iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 31); + iki_vhdl_file_variable_register(dp + 24832); + iki_vhdl_file_variable_register(dp + 24888); /*Populate the transaction function pointer field in the whole net structure */ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o index f7bfae3..9aa9332 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info index a8a0d21..99c4d45 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ -1685389741 -1685390103 -147 +1685542134 +1685542416 +171 1 aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..0d26e76 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedWed May 31 16:13:36 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration153random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-9500 CPU @ 3.00GHzcpu_speed3000.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=4runtime=100 ussimulation_memory=122672_KBsimulation_time=0.02_sec
trace_waveform=true
+

+ + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..76e4ff4 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl index fe1417b..cec9ee2 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl @@ -1,6 +1,6 @@ webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 16:24:18 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Wed May 31 18:34:59 2023" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" @@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "146" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "170" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "2576.095 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3000.000 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "50 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "5" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122664_KB" -context "xsim\\usage" -webtalk_transmit -clientid 2613593652 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key runtime -value "100 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "122672_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1544091380 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg index fca23f8..14752d5 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem index bd35d3a..695ee5d 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc index ea4bf54..aefc4c8 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx index 06987bd..d1425c9 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 4961576604248800900 , + crc : 2677193059207045368 , ccp_crc : 0 , cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" , buildDate : "Jun 14 2018" , diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti index ebeb0fd..4574d4f 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type index b868556..b22217f 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg index 02652b1..dc21d13 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk index 01b13ee..3c185ca 100755 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log index f6f65fc..15d0cbf 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log @@ -1,4 +1,7 @@ -Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 42291 +Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 53223 Design successfully loaded -Design Loading Memory Usage: 32728 KB (Peak: 32780 KB) -Design Loading CPU Usage: 20 ms +Design Loading Memory Usage: 32736 KB (Peak: 32788 KB) +Design Loading CPU Usage: 30 ms +Simulation completed +Simulation Memory Usage: 122672 KB (Peak: 180008 KB) +Simulation CPU Usage: 30 ms diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb index 6f9dc20..8327d80 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb index dbb642b..a86cd06 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb index 7438a48..822ff0a 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb index 6356d14..16492cc 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb index 11fe39e..7dc3221 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index 1535890..0f13ad9 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,14 +2,14 @@ 2018.2 Jun 14 2018 20:07:38 -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685451235,vhdl,,,,test_total,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685454749,vhdl,,,,alu,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685451016,vhdl,,,,aleacontroler,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685465261,vhdl,,,,test_total,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685542123,vhdl,,,,alu,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685543740,vhdl,,,,aleacontroler,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685456575,vhdl,,,,instructionmemory,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685455519,vhdl,,,,pipeline,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685435532,vhdl,,,,registers,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685545934,vhdl,,,,pipeline,,,,,,,, +/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685467153,vhdl,,,,registers,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,, diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log index e69de29..b6abecb 100644 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb index b155e40..c765b72 100644 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb and b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc b/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc new file mode 100644 index 0000000..c9f590c --- /dev/null +++ b/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc @@ -0,0 +1,26 @@ +set_property PACKAGE_PIN R2 [get_ports CLK] + set_property IOSTANDARD LVCMOS33 [get_ports CLK] +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK] + +#set_property -dicset_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports CLK] +#set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports CLK] +#create_clock -period 10.000 -name -sysclk_pin -waveform {0.000 5.000} [get_ports CLK] + +set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets {Stage2/Jump_Flag}] + +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[0]}] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[1]}] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[2]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[3]}] + +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {reg_val[0]}] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {reg_val[1]}] +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {reg_val[2]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {reg_val[3]}] +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {reg_val[4]}] +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {reg_val[5]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {reg_val[6]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {reg_val[7]}] + +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] diff --git a/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc b/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc new file mode 100644 index 0000000..da05bd1 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc @@ -0,0 +1 @@ +#create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk] diff --git a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd index 32ba8ab..407233b 100644 --- a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd +++ b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd @@ -39,16 +39,21 @@ architecture Behavioral of test_total is component Pipeline - Port (Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC; + reg_addr : in STD_LOGIC_VECTOR(3 downto 0); + reg_val : out STD_LOGIC_VECTOR(7 downto 0)); end component; constant clock_period : time := 10 ns; signal clock : Std_logic := '0'; + signal a : STD_LOGIC_VECTOR(7 downto 0); begin -- instantiate Pl : Pipeline PORT MAP ( - Clk => clock + Clk => clock, + reg_addr => x"0", + reg_val => a ); Clock_process : process diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd index 6ce7ac6..8e96a44 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd @@ -42,7 +42,8 @@ entity ALU is O : out STD_LOGIC; Z : out STD_LOGIC; C : out STD_LOGIC; - JumpFlag : inout STD_LOGIC -- 0 false 1 true + JumpFlagOut : out STD_LOGIC; -- 0 false 1 true + JumpFlagIn : in STD_LOGIC ); end ALU; @@ -70,7 +71,7 @@ begin O <= '0'; Z <= '0'; C <= '0'; - flag <= JumpFlag; + flag <= JumpFlagIn; case Ctrl_Alu is when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL @@ -79,13 +80,13 @@ begin when x"09" => if A < B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when x"0A" => if A > B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when x"0B" => if A = B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0C" => if A > 0 then res <= x"0000"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; + when x"0C" => if A > 0 then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; when others => res <= x"0000"; end case; end process; - JumpFlag <= flag; + JumpFlagOut <= flag; S <= res(7 downto 0); end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd index 4cb3f72..c6e728e 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd @@ -43,35 +43,35 @@ architecture Behavioral of AleaControler is begin CNTRL <= -- either a problem between the 1st and 2nd or 1st and 3rd '1' when - -- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read) + -- read after write : Op1 other than STORE/NOP/JMP/JMF, op2 other than AFC/NOP/JMP/JMF, R(write) = R(read) ( -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_EX /= x"08" and Op_EX /= x"ff")) and + ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_EX /= x"08" and Op_EX /= x"ff" and Op_EX /= x"0f" and Op_EX /= x"10")) and -- check Registers are the same ((A_Ex = B_DI) or (A_EX = C_DI)) ) or - -- read after write : Op1 other than STORE/NOP, op3 other than AFC/NOP, R(write) = R(read) + -- read after write : Op1 other than STORE/NOP/JMP/JMF, op3 other than AFC/NOP/JMP/JMF, R(write) = R(read) ( -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Mem /= x"08" and Op_Mem /= x"ff")) and + ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_Mem /= x"08" and Op_Mem /= x"ff" and Op_Mem /= x"0f" and Op_Mem /= x"10")) and -- check Registers are the same ((A_Mem = B_DI) or (A_Mem = C_DI)) ) or - -- read after write : Op1 other than STORE/NOP, op4 other than AFC/NOP, R(write) = R(read) + -- read after write : Op1 other than STORE/NOP/JMP/JMF, op4 other than AFC/NOP/JMP/JMF, R(write) = R(read) ( -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff") and (Op_Re /= x"08" and Op_Re /= x"ff")) and + ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_Re /= x"08" and Op_Re /= x"ff" and Op_Re /= x"0f" and Op_Re /= x"10")) and -- check Registers are the same ((A_Re = B_DI) or (A_Re = C_DI)) ) or ( - Op_EX = x"10" or Op_Mem = x"10" or Op_Re = x"10" + Op_EX = x"10" -- or Op_Mem = x"10" or Op_Re = x"10" ) else '0'; end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index e2e2c39..ed83102 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -32,7 +32,9 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Pipeline is - Port (Clk : in STD_LOGIC); + Port (Clk : in STD_LOGIC := '0'; + reg_addr : in STD_LOGIC_VECTOR(3 downto 0) := "0000"; + reg_val : out STD_LOGIC_VECTOR(7 downto 0)); end Pipeline; architecture Behavioral of Pipeline is @@ -72,15 +74,17 @@ architecture Behavioral of Pipeline is component Registers Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); - Addr_B : in STD_LOGIC_VECTOR (3 downto 0); - Addr_W : in STD_LOGIC_VECTOR (3 downto 0); - W : in STD_LOGIC; - Data : in STD_LOGIC_VECTOR (7 downto 0); - Rst : in STD_LOGIC; - Clk : in STD_LOGIC; - QA : out STD_LOGIC_VECTOR (7 downto 0); - QB : out STD_LOGIC_VECTOR (7 downto 0) - ); + Addr_B : in STD_LOGIC_VECTOR (3 downto 0); + Addr_W : in STD_LOGIC_VECTOR (3 downto 0); + Addr_C : in STD_LOGIC_VECTOR (3 downto 0); -- display on FPGA + W : in STD_LOGIC; + Data : in STD_LOGIC_VECTOR (7 downto 0); + Rst : in STD_LOGIC; + Clk : in STD_LOGIC; + QA : out STD_LOGIC_VECTOR (7 downto 0); + QB : out STD_LOGIC_VECTOR (7 downto 0); + QC : out STD_LOGIC_VECTOR (7 downto 0) + ); end component; signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); @@ -110,7 +114,8 @@ architecture Behavioral of Pipeline is O : out STD_LOGIC; Z : out STD_LOGIC; C : out STD_LOGIC; - JumpFlag : inout STD_LOGIC + JumpFlagOut : out STD_LOGIC; -- 0 false 1 true + JumpFlagIn : in STD_LOGIC ); end component; @@ -206,12 +211,14 @@ StageRegisters : Registers PORT MAP ( Addr_A => Di_B(3 downto 0), -- because the registers are on 4 bits Addr_B => Di_C(3 downto 0), Addr_W => Re_A(3 downto 0), + Addr_C => reg_addr, W => Re_W, Data => Re_B, Rst => Rst, Clk => Clk, QA => Di_RegB, - QB => Di_C2); + QB => Di_C2, + QC => reg_val); -- Stage DI/EX Stage2 : Stage_Di_Ex PORT MAP ( @@ -235,7 +242,8 @@ Ual : ALU PORT MAP ( O => S_OFlag, Z => S_ZFlag, C => S_CFlag, - JumpFlag => Jump_Flag); + JumpFlagOut => Jump_Flag, + JumpFlagIn => Jump_Flag); -- Stage Ex/Mem Stage3 : Stage_Ex_Mem PORT MAP ( @@ -273,7 +281,7 @@ Stage4 : Stage_Mem_Re PORT MAP ( -- DIV x"04" -- COP x"05" -- AFC x"06" - -- LOAD x"07"OP_DI + -- LOAD x"07" -- STORE x"08" -- INF x"09" -- SUP x"0A" @@ -351,7 +359,6 @@ CU : AleaControler port map ( -- case of JMF not triggering Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1') else Di_Op; - - + end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd index c137e3f..6b04c78 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd @@ -36,12 +36,14 @@ entity Registers is Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); Addr_B : in STD_LOGIC_VECTOR (3 downto 0); Addr_W : in STD_LOGIC_VECTOR (3 downto 0); + Addr_C : in STD_LOGIC_VECTOR (3 downto 0); -- display on FPGA W : in STD_LOGIC; Data : in STD_LOGIC_VECTOR (7 downto 0); Rst : in STD_LOGIC; Clk : in STD_LOGIC; QA : out STD_LOGIC_VECTOR (7 downto 0); - QB : out STD_LOGIC_VECTOR (7 downto 0)); + QB : out STD_LOGIC_VECTOR (7 downto 0); + QC : out STD_LOGIC_VECTOR (7 downto 0)); end Registers; architecture Behavioral of Registers is @@ -68,4 +70,10 @@ begin when W = '0' or Addr_W /= Addr_B else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q + QC <= Regs(to_integer(unsigned(Addr_C))) + when W = '0' or Addr_W /= Addr_C + --else Regs(to_integer(unsigned(Addr_W))) + else + x"11" ; -- to bypass D --> Q + end Behavioral; diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr index a429411..a09f0c2 100644 --- a/VHDL/ALU/ALU.xpr +++ b/VHDL/ALU/ALU.xpr @@ -33,7 +33,7 @@