diff --git a/LinkedList.h b/LinkedList.h deleted file mode 100644 index e69de29..0000000 diff --git a/Makefile b/Makefile deleted file mode 100644 index a97ea4e..0000000 --- a/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -GRM=yacc.y -LEX=lex.l -BIN=out - -CC=gcc -CFLAGS=-Wall -g - -OBJ=yacc.tab.o lex.yy.o table.o operations.o blocs.o asmTable.o - -asm: $(BIN) - @touch testFile # to prevent an error in case of deletion - ./out < testFile - -build: $(BIN) - -%.o: %.c - $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ - -yacc.tab.c: $(GRM) - bison -d -t -v $< - -lex.yy.c: $(LEX) - flex $< - -$(BIN): $(OBJ) - $(CC) $(CFLAGS) $(CPPFLAGS) $^ -o $@ - -clean: - rm $(OBJ) yacc.tab.c yacc.tab.h lex.yy.c - -vhdl: clean asm - python3 post-process.py - -inter: clean asm - python3 graph_interpreter.py - diff --git a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf deleted file mode 100644 index 562c893..0000000 --- a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf +++ /dev/null @@ -1,174 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- - diff --git a/VHDL/ALU/ALU.cache/wt/xsim.wdf b/VHDL/ALU/ALU.cache/wt/xsim.wdf deleted file mode 100644 index 50afb2c..0000000 --- a/VHDL/ALU/ALU.cache/wt/xsim.wdf +++ /dev/null @@ -1,4 +0,0 @@ -version:1 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 -eof:241934075 diff --git a/VHDL/ALU/ALU.hw/ALU.lpr b/VHDL/ALU/ALU.hw/ALU.lpr deleted file mode 100644 index 68b7fe8..0000000 --- a/VHDL/ALU/ALU.hw/ALU.lpr +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.hw/hw_1/hw.xml b/VHDL/ALU/ALU.hw/hw_1/hw.xml deleted file mode 100644 index f20d5c2..0000000 --- a/VHDL/ALU/ALU.hw/hw_1/hw.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/VHDL/ALU/ALU.ip_user_files/README.txt b/VHDL/ALU/ALU.ip_user_files/README.txt deleted file mode 100644 index 023052c..0000000 --- a/VHDL/ALU/ALU.ip_user_files/README.txt +++ /dev/null @@ -1 +0,0 @@ -The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index 7f1dfcd..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml deleted file mode 100644 index 08c8941..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml deleted file mode 100644 index 806781c..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml deleted file mode 100644 index b9bdcb4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml deleted file mode 100644 index 330f416..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml deleted file mode 100644 index 4c95ac6..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml deleted file mode 100644 index 7f1dfcd..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml deleted file mode 100644 index 7f1dfcd..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml deleted file mode 100644 index a2d5bc4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml deleted file mode 100644 index b9bdcb4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml deleted file mode 100644 index 715a1f3..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml deleted file mode 100644 index 715a1f3..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml deleted file mode 100644 index 715a1f3..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml deleted file mode 100644 index 7f1dfcd..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml deleted file mode 100644 index b34d040..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml deleted file mode 100644 index 7f1dfcd..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml deleted file mode 100644 index b9bdcb4..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml deleted file mode 100644 index 08c8941..0000000 --- a/VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.Vivado_Implementation.queue.rst b/VHDL/ALU/ALU.runs/impl_1/.Vivado_Implementation.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst deleted file mode 100644 index bc98f66..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.init_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.init_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst deleted file mode 100644 index bc98f66..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.opt_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.opt_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst deleted file mode 100644 index bc98f66..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.place_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.place_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst deleted file mode 100644 index bc98f66..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.route_design.end.rst b/VHDL/ALU/ALU.runs/impl_1/.route_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst deleted file mode 100644 index 4284699..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.vivado.end.rst b/VHDL/ALU/ALU.runs/impl_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst b/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst deleted file mode 100644 index bc98f66..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.end.rst b/VHDL/ALU/ALU.runs/impl_1/.write_bitstream.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js deleted file mode 100755 index 8284d2d..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.js +++ /dev/null @@ -1,244 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh b/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh deleted file mode 100755 index e1a8f5d..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit b/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit deleted file mode 100644 index c07098d..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline.bit and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl b/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl deleted file mode 100644 index 3eef97e..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl +++ /dev/null @@ -1,171 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - set_param xicom.use_bs_reader 1 - create_project -in_memory -part xc7a35tcpg236-1 - set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project] - set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project] - set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp - read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc - link_design -top Pipeline -part xc7a35tcpg236-1 - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force Pipeline_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force Pipeline_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file Pipeline_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Pipeline_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force Pipeline_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Pipeline_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force Pipeline_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - -start_step write_bitstream -set ACTIVE_STEP write_bitstream -set rc [catch { - create_msg_db write_bitstream.pb - catch { write_mem_info -force Pipeline.mmi } - write_bitstream -force Pipeline.bit - catch {write_debug_probes -quiet -force Pipeline} - catch {file copy -force Pipeline.ltx debug_nets.ltx} - close_msg_db -file write_bitstream.pb -} RESULT] -if {$rc} { - step_failed write_bitstream - return -code error $RESULT -} else { - end_step write_bitstream - unset ACTIVE_STEP -} - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi b/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi deleted file mode 100644 index 35f7c37..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi +++ /dev/null @@ -1,472 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 17:57:08 2023 -# Process ID: 144223 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1 -# Command line: vivado -log Pipeline.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/vivado.jou -#----------------------------------------------------------- -source Pipeline.tcl -notrace -Command: link_design -top Pipeline -part xc7a35tcpg236-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.2 -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 1e379f571 - -Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1e379f571 - -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 224c05fcb - -Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 237fe1223 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 237fe1223 - -Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -Ending Logic Optimization Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Common 17-83] Releasing license: Implementation -23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx -Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db - -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd - -Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Phase 1 Placer Initialization | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 15cb247ff - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Phase 3 Detail Placement | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Ending Placer Task | Checksum: 8268151a - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535 -INFO: [Common 17-83] Releasing license: Implementation -41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. -place_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537 -INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544 -INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs -Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437 -Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 - Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 16523de4e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 11b0f7581 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 97 - Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 -Phase 4 Rip-up And Reroute | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 -Phase 6 Post Hold Fix | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.153313 % - Global Horizontal Routing Utilization = 0.172046 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Congestion Report -North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 16fad2baa - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx -Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx -Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 6 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx -Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. -INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -Command: write_bitstream -force Pipeline.bit -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command write_bitstream -INFO: [DRC 23-27] Running DRC with 6 threads -WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. -WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7. -WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings -INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. -Loading data files... -Loading site data... -Loading route data... -Processing options... -Creating bitmap... -Creating bitstream... -Writing bitstream ./Pipeline.bit... -INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. -INFO: [Common 17-83] Releasing license: Implementation -84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered. -write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368 -INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023... diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb deleted file mode 100644 index 3390588..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt deleted file mode 100644 index d54e949..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt +++ /dev/null @@ -1,15 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:14 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx -| Design : Pipeline -| Device : 7a35t-cpg236 -| Speed File : -1 PRODUCTION 1.22 2018-03-21 ---------------------------------------------------------------------------------------------------------------------------------------------------------- - -Bus Skew Report - -No bus skew constraints - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx deleted file mode 100644 index 41eaae5..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt deleted file mode 100644 index abfe0fc..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt +++ /dev/null @@ -1,145 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:14 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt -| Design : Pipeline -| Device : 7a35t-cpg236 -| Speed File : -1 PRODUCTION 1.22 2018-03-21 --------------------------------------------------------------------------------------- - -Clock Utilization Report - -Table of Contents ------------------ -1. Clock Primitive Utilization -2. Global Clock Resources -3. Global Clock Source Details -4. Clock Regions: Key Resource Utilization -5. Clock Regions : Global Clock Summary -6. Device Cell Placement Summary for Global Clock g0 -7. Clock Region Cell Placement per Global Clock: Region X0Y0 - -1. Clock Primitive Utilization ------------------------------- - -+----------+------+-----------+-----+--------------+--------+ -| Type | Used | Available | LOC | Clock Region | Pblock | -+----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | -| BUFH | 0 | 72 | 0 | 0 | 0 | -| BUFIO | 0 | 20 | 0 | 0 | 0 | -| BUFMR | 0 | 10 | 0 | 0 | 0 | -| BUFR | 0 | 20 | 0 | 0 | 0 | -| MMCM | 0 | 5 | 0 | 0 | 0 | -| PLL | 0 | 5 | 0 | 0 | 0 | -+----------+------+-----------+-----+--------------+--------+ - - -2. Global Clock Resources -------------------------- - -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 342 | 0 | | | Clk_IBUF_BUFG_inst/O | Clk_IBUF_BUFG | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -3. Global Clock Source Details ------------------------------- - -+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| src0 | g0 | IBUF/O | None | IOB_X0Y128 | X0Y2 | 1 | 0 | | | Clk_IBUF_inst/O | Clk_IBUF | -+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -4. Clock Regions: Key Resource Utilization ------------------------------------------- - -+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 342 | 1200 | 136 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -* Global Clock column represents track count; while other columns represents cell counts - - -5. Clock Regions : Global Clock Summary ---------------------------------------- - -All Modules -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 1 | 0 | -+----+----+----+ - - -6. Device Cell Placement Summary for Global Clock g0 ----------------------------------------------------- - -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| g0 | BUFG/O | n/a | | | | 342 | 0 | 0 | 0 | Clk_IBUF_BUFG | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+------+----+ -| | X0 | X1 | -+----+------+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 342 | 0 | -+----+------+----+ - - -7. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ -| g0 | n/a | BUFG/O | None | 342 | 0 | 342 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_IBUF_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - - -# Location of BUFG Primitives -set_property LOC BUFGCTRL_X0Y16 [get_cells Clk_IBUF_BUFG_inst] - -# Location of IO Primitives which is load of clock spine - -# Location of clock ports -set_property LOC IOB_X0Y128 [get_ports Clk] - -# Clock net "Clk_IBUF_BUFG" driven by instance "Clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" -#startgroup -create_pblock {CLKAG_Clk_IBUF_BUFG} -add_cells_to_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_IBUF_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} -#endgroup diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt deleted file mode 100644 index 436bb01..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_control_sets_placed.rpt +++ /dev/null @@ -1,101 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:57:59 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt -| Design : Pipeline -| Device : xc7a35t -------------------------------------------------------------------------------------- - -Control Set Information - -Table of Contents ------------------ -1. Summary -2. Histogram -3. Flip-Flop Distribution -4. Detailed Control Set Information - -1. Summary ----------- - -+----------------------------------------------------------+-------+ -| Status | Count | -+----------------------------------------------------------+-------+ -| Number of unique control sets | 36 | -| Unused register locations in slices containing registers | 12 | -+----------------------------------------------------------+-------+ - - -2. Histogram ------------- - -+--------+--------------+ -| Fanout | Control Sets | -+--------+--------------+ -| 12 | 2 | -| 16+ | 34 | -+--------+--------------+ - - -3. Flip-Flop Distribution -------------------------- - -+--------------+-----------------------+------------------------+-----------------+--------------+ -| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | -+--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 132 | 23 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 24 | 4 | -| Yes | No | No | 528 | 111 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 0 | 0 | -+--------------+-----------------------+------------------------+-----------------+--------------+ - - -4. Detailed Control Set Information ------------------------------------ - -+----------------+-----------------------+---------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+----------------+-----------------------+---------------------+------------------+----------------+ -| Clk_IBUF_BUFG | | Stage1/Di_Op_Final1 | 2 | 12 | -| Clk_IBUF_BUFG | | Stage1/OP_LI_DI1 | 2 | 12 | -| Clk_IBUF_BUFG | Stage3/Mem[6]_8 | | 1 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[6]_9 | | 5 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[10]_8 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[11]_4 | | 5 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[12]_0 | | 5 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[13]_11 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[7]_5 | | 5 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[8]_1 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[9]_12 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs_reg[0][7] | | 2 | 16 | -| Clk_IBUF_BUFG | Stage1/aux_reg[7] | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[1]_14 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[2]_10 | | 5 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[8]_2 | | 1 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[9]_9 | | 3 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[4]_2 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[5]_13 | | 3 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[5]_0 | | 1 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem_reg[1][0] | | 2 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem_reg[2][0] | | 1 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[14]_7 | | 6 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[3]_7 | | 3 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem_reg[13][0] | | 1 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem_reg[14][0] | | 2 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[7]_6 | | 2 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[11]_5 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[12]_1 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[15]_3 | | 7 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[10]_10 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[15]_4 | | 2 | 16 | -| Clk_IBUF_BUFG | Stage4/Regs[3]_6 | | 4 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[0]_11 | | 2 | 16 | -| Clk_IBUF_BUFG | Stage3/Mem[4]_3 | | 3 | 16 | -| Clk_IBUF_BUFG | | | 23 | 132 | -+----------------+-----------------------+---------------------+------------------+----------------+ - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb deleted file mode 100644 index 6c5ff57..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt deleted file mode 100644 index 62607dd..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt +++ /dev/null @@ -1,72 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:57:56 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx -| Design : Pipeline -| Device : xc7a35tcpg236-1 -| Speed File : -1 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 5 -+----------+----------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+-----------------------------------------------------+------------+ -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 | -| NSTD-1 | Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Warning | Unconstrained Logical Port | 1 | -+----------+----------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - -LUTLP-2#1 Warning -Combinatorial Loop Allowed -1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. -Related violations: - -LUTLP-2#2 Warning -Combinatorial Loop Allowed -3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7. -Related violations: - -NSTD-1#1 Warning -Unspecified I/O Standard -1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -Related violations: - -UCIO-1#1 Warning -Unconstrained Logical Port -1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -Related violations: - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx deleted file mode 100644 index 9c362c1..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb deleted file mode 100644 index 6c5ff57..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt deleted file mode 100644 index 0285501..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt +++ /dev/null @@ -1,72 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:11 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx -| Design : Pipeline -| Device : xc7a35tcpg236-1 -| Speed File : -1 -| Design State : Routed ------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 5 -+----------+----------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+-----------------------------------------------------+------------+ -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 | -| NSTD-1 | Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Warning | Unconstrained Logical Port | 1 | -+----------+----------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - -LUTLP-2#1 Warning -Combinatorial Loop Allowed -1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. -Related violations: - -LUTLP-2#2 Warning -Combinatorial Loop Allowed -3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7. -Related violations: - -NSTD-1#1 Warning -Unspecified I/O Standard -1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -Related violations: - -UCIO-1#1 Warning -Unconstrained Logical Port -1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -Related violations: - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx deleted file mode 100644 index f0b91c6..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt deleted file mode 100644 index 5d86e7e..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_io_placed.rpt +++ /dev/null @@ -1,280 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:57:59 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_io -file Pipeline_io_placed.rpt -| Design : Pipeline -| Device : xc7a35t -| Speed File : -1 -| Package : cpg236 -| Package Version : FINAL 2014-02-19 -| Package Pin Delay Version : VERS. 2.0 2014-02-19 -------------------------------------------------------------------------------------------------- - -IO Information - -Table of Contents ------------------ -1. Summary -2. IO Assignments by Package Pin - -1. Summary ----------- - -+---------------+ -| Total User IO | -+---------------+ -| 13 | -+---------------+ - - -2. IO Assignments by Package Pin --------------------------------- - -+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | -| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | -| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | -| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | -| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | -| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | -| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | -| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | -| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | -| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | -| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | -| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | -| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | -| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | -| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | -| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | -| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | -| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | -| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | -| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | -| C15 | Clk | High Range | IO_L11P_T1_SRCC_16 | INPUT | LVCMOS18* | 16 | | | | NONE | | UNFIXED | | | | NONE | | | | -| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | -| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | -| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | -| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | -| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | -| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | -| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| E19 | reg_val[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | -| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | -| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | -| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.80 | | | | | | | | | -| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | -| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | -| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | -| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | -| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | -| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | -| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | -| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | -| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | -| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | -| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | -| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | -| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | -| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | -| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | -| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | -| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | -| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | -| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | -| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | -| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | -| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | -| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | -| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | -| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | -| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | -| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | -| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | -| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | -| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | -| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | -| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | -| U14 | reg_val[6] | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| U15 | reg_val[5] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| U16 | reg_val[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | -| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | -| U19 | reg_val[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | -| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | -| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | -| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | -| V14 | reg_val[7] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| V16 | reg_addr[1] | High Range | IO_L19P_T3_A10_D26_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | -| V17 | reg_addr[0] | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | -| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V19 | reg_val[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W7 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | -| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | -| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | -| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | -| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | -| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | -| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | -| W16 | reg_addr[2] | High Range | IO_L20P_T3_A08_D24_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | -| W17 | reg_addr[3] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | -| W18 | reg_val[4] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | -+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -* Default value -** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb deleted file mode 100644 index 793f977..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt deleted file mode 100644 index b080d6b..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt +++ /dev/null @@ -1,1751 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:13 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx -| Design : Pipeline -| Device : xc7a35tcpg236-1 -| Speed File : -1 -| Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Report Methodology - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Max violations: - Violations found: 343 -+-----------+----------+-----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-----------------------------+------------+ -| TIMING-17 | Warning | Non-clocked sequential cell | 342 | -| TIMING-23 | Warning | Combinational loop found | 1 | -+-----------+----------+-----------------------------+------------+ - -2. REPORT DETAILS ------------------ -TIMING-17#1 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#2 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#3 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#4 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#5 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#6 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#7 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#8 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[0][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#9 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#10 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#11 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#12 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#13 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#14 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#15 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#16 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[10][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#17 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#18 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#19 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#20 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#21 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#22 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#23 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#24 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[11][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#25 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#26 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#27 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#28 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#29 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#30 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#31 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#32 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[12][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#33 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#34 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#35 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#36 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#37 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#38 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#39 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#40 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[13][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#41 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#42 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#43 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#44 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#45 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#46 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#47 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#48 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[14][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#49 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#50 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#51 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#52 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#53 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#54 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#55 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#56 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[15][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#57 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#58 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#59 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#60 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#61 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#62 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#63 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#64 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[1][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#65 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#66 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#67 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#68 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#69 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#70 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#71 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#72 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[2][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#73 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#74 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#75 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#76 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#77 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#78 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#79 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#80 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[3][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#81 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#82 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#83 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#84 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#85 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#86 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#87 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#88 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[4][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#89 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#90 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#91 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#92 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#93 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#94 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#95 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#96 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[5][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#97 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#98 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#99 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#100 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#101 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#102 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#103 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#104 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[6][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#105 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#106 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#107 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#108 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#109 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#110 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#111 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#112 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[7][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#113 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#114 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#115 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#116 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#117 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#118 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#119 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#120 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[8][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#121 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#122 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#123 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#124 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#125 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#126 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#127 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#128 Warning -Non-clocked sequential cell -The clock pin DataMem/Mem_reg[9][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#129 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_A_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#130 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_A_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#131 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_A_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#132 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_A_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#133 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_B_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#134 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_B_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#135 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_B_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#136 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_B_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#137 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_B_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#138 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_C_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#139 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#140 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#141 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#142 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#143 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#144 Warning -Non-clocked sequential cell -The clock pin Stage1/Out_Op_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#145 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_A_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#146 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_A_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#147 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_A_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#148 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_A_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#149 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#150 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#151 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#152 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#153 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#154 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#155 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#156 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_B_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#157 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#158 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#159 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#160 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#161 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#162 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#163 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#164 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_C_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#165 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#166 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#167 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#168 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#169 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#170 Warning -Non-clocked sequential cell -The clock pin Stage2/Out_Op_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#171 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_A_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#172 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_A_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#173 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_A_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#174 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_A_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#175 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#176 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#177 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#178 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#179 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#180 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#181 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#182 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_B_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#183 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#184 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#185 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#186 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#187 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#188 Warning -Non-clocked sequential cell -The clock pin Stage3/Out_Op_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#189 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_A_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#190 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_A_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#191 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_A_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#192 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_A_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#193 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#194 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#195 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#196 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#197 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#198 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#199 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#200 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_B_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#201 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#202 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#203 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#204 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#205 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#206 Warning -Non-clocked sequential cell -The clock pin Stage4/Out_Op_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#207 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#208 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#209 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#210 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#211 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#212 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#213 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#214 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[0][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#215 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#216 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#217 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#218 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#219 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#220 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#221 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#222 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[10][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#223 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#224 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#225 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#226 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#227 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#228 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#229 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#230 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[11][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#231 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#232 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#233 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#234 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#235 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#236 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#237 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#238 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[12][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#239 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#240 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#241 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#242 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#243 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#244 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#245 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#246 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[13][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#247 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#248 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#249 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#250 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#251 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#252 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#253 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#254 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[14][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#255 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#256 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#257 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#258 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#259 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#260 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#261 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#262 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[15][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#263 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#264 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#265 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#266 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#267 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#268 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#269 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#270 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[1][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#271 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#272 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#273 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#274 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#275 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#276 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#277 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#278 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[2][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#279 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#280 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#281 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#282 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#283 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#284 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#285 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#286 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[3][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#287 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#288 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#289 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#290 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#291 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#292 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#293 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#294 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[4][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#295 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#296 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#297 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#298 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#299 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#300 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#301 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#302 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[5][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#303 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#304 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#305 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#306 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#307 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#308 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#309 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#310 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[6][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#311 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#312 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#313 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#314 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#315 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#316 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#317 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#318 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[7][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#319 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#320 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#321 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#322 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#323 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#324 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#325 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#326 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[8][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#327 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][0]/C is not reached by a timing clock -Related violations: - -TIMING-17#328 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#329 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#330 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#331 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#332 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#333 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#334 Warning -Non-clocked sequential cell -The clock pin StageRegisters/Regs_reg[9][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#335 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#336 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#337 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#338 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#339 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#340 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#341 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#342 Warning -Non-clocked sequential cell -The clock pin inst_point/aux_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-23#1 Warning -Combinational loop found -A timing loop has been detected on a combinational path. A timing arc has been disabled between Stage2/Out_Op[5]_i_3/I1 and Stage2/Out_Op[5]_i_3/O to disable the timing loop -Related violations: - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx deleted file mode 100644 index 697143f..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp deleted file mode 100644 index 3a2fd63..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp deleted file mode 100644 index 1957ed2..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt deleted file mode 100644 index 057b164..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpt +++ /dev/null @@ -1,153 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:13 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx -| Design : Pipeline -| Device : xc7a35tcpg236-1 -| Design State : routed -| Grade : commercial -| Process : typical -| Characterization : Production ----------------------------------------------------------------------------------------------------------------------------------------------- - -Power Report - -Table of Contents ------------------ -1. Summary -1.1 On-Chip Components -1.2 Power Supply Summary -1.3 Confidence Level -2. Settings -2.1 Environment -2.2 Clock Constraints -3. Detailed Reports -3.1 By Hierarchy - -1. Summary ----------- - -+--------------------------+--------------+ -| Total On-Chip Power (W) | 3.334 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 3.253 | -| Device Static (W) | 0.081 | -| Effective TJA (C/W) | 5.0 | -| Max Ambient (C) | 68.3 | -| Junction Temperature (C) | 41.7 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ -* Specify Design Power Budget using, set_operating_conditions -design_power_budget - - -1.1 On-Chip Components ----------------------- - -+----------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+----------------+-----------+----------+-----------+-----------------+ -| Slice Logic | 1.294 | 831 | --- | --- | -| LUT as Logic | 1.166 | 371 | 20800 | 1.78 | -| CARRY4 | 0.105 | 33 | 8150 | 0.40 | -| Register | 0.018 | 342 | 41600 | 0.82 | -| BUFG | 0.006 | 1 | 32 | 3.13 | -| F7/F8 Muxes | <0.001 | 19 | 32600 | 0.06 | -| Others | 0.000 | 13 | --- | --- | -| Signals | 1.154 | 691 | --- | --- | -| I/O | 0.804 | 13 | 106 | 12.26 | -| Static Power | 0.081 | | | | -| Total | 3.334 | | | | -+----------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 2.486 | 2.468 | 0.018 | -| Vccaux | 1.800 | 0.042 | 0.029 | 0.013 | -| Vcco33 | 3.300 | 0.223 | 0.222 | 0.001 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 5.0 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 4.6 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------+--------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------+--------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+------------------+-----------+ -| Name | Power (W) | -+------------------+-----------+ -| Pipeline | 3.253 | -| DataMem | 0.035 | -| Stage1 | 0.205 | -| Stage2 | 1.072 | -| Stage3 | 0.208 | -| Stage4 | 0.140 | -| StageRegisters | 0.099 | -| Ual | 0.165 | -| inst_point | 0.416 | -+------------------+-----------+ - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx deleted file mode 100644 index 1af5673..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_routed.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb deleted file mode 100644 index 5a6b2ef..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_power_summary_routed.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb deleted file mode 100644 index 4c5b016..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt deleted file mode 100644 index 2d1d87b..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_route_status.rpt +++ /dev/null @@ -1,11 +0,0 @@ -Design Route Status - : # nets : - ------------------------------------------- : ----------- : - # of logical nets.......................... : 914 : - # of nets not needing routing.......... : 221 : - # of internally routed nets........ : 221 : - # of routable nets..................... : 693 : - # of fully routed nets............. : 693 : - # of nets with routing errors.......... : 0 : - ------------------------------------------- : ----------- : - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp b/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp deleted file mode 100644 index ff740c4..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb deleted file mode 100644 index 4526e93..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.pb +++ /dev/null @@ -1,2 +0,0 @@ - -2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt deleted file mode 100644 index a9292b0..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpt +++ /dev/null @@ -1,173 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:58:13 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation -| Design : Pipeline -| Device : 7a35t-cpg236 -| Speed File : -1 PRODUCTION 1.22 2018-03-21 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : false - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock -2. checking constant_clock -3. checking pulse_width_clock -4. checking unconstrained_internal_endpoints -5. checking no_input_delay -6. checking no_output_delay -7. checking multiple_clock -8. checking generated_clocks -9. checking loops -10. checking partial_input_delay -11. checking partial_output_delay -12. checking latch_loops - -1. checking no_clock --------------------- - There are 342 register/latch pins with no clock driven by root clock pin: Clk (HIGH) - - -2. checking constant_clock --------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock ------------------------------ - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints --------------------------------------------- - There are 618 pins that are not constrained for maximum delay. (HIGH) - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay --------------------------- - There are 0 input ports with no input delay specified. - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay ---------------------------- - There are 8 ports with no output delay specified. (HIGH) - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock --------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks ----------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops ------------------ - There are 2 combinational loops in the design. (HIGH) - - -10. checking partial_input_delay --------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay ---------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops ------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - NA NA NA NA NA NA NA NA NA NA NA NA - - -There are no user specified timing constraints. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx b/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx deleted file mode 100644 index d313c26..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_timing_summary_routed.rpx and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb deleted file mode 100644 index 3e7476f..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt b/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt deleted file mode 100644 index 392c7d5..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/Pipeline_utilization_placed.rpt +++ /dev/null @@ -1,209 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:57:59 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb -| Design : Pipeline -| Device : 7a35tcpg236-1 -| Design State : Fully Placed -------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 371 | 0 | 20800 | 1.78 | -| LUT as Logic | 371 | 0 | 20800 | 1.78 | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 342 | 0 | 41600 | 0.82 | -| Register as Flip Flop | 342 | 0 | 41600 | 0.82 | -| Register as Latch | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 19 | 0 | 16300 | 0.12 | -| F8 Muxes | 0 | 0 | 8150 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 12 | Yes | Set | - | -| 330 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+-------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------------------------+------+-------+-----------+-------+ -| Slice | 158 | 0 | 8150 | 1.94 | -| SLICEL | 103 | 0 | | | -| SLICEM | 55 | 0 | | | -| LUT as Logic | 371 | 0 | 20800 | 1.78 | -| using O5 output only | 0 | | | | -| using O6 output only | 319 | | | | -| using O5 and O6 | 52 | | | | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| LUT Flip Flop Pairs | 48 | 0 | 20800 | 0.23 | -| fully used LUT-FF pairs | 5 | | | | -| LUT-FF pairs with one unused LUT output | 42 | | | | -| LUT-FF pairs with one unused Flip Flop | 37 | | | | -| Unique Control Sets | 36 | | | | -+-------------------------------------------+------+-------+-----------+-------+ -* Note: Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 50 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | -| RAMB18 | 0 | 0 | 100 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 90 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 13 | 12 | 106 | 12.26 | -| IOB Master Pads | 6 | | | | -| IOB Slave Pads | 6 | | | | -| Bonded IPADs | 0 | 0 | 10 | 0.00 | -| Bonded OPADs | 0 | 0 | 4 | 0.00 | -| PHY_CONTROL | 0 | 0 | 5 | 0.00 | -| PHASER_REF | 0 | 0 | 5 | 0.00 | -| OUT_FIFO | 0 | 0 | 20 | 0.00 | -| IN_FIFO | 0 | 0 | 20 | 0.00 | -| IDELAYCTRL | 0 | 0 | 5 | 0.00 | -| IBUFDS | 0 | 0 | 104 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 106 | 0.00 | -| OLOGIC | 0 | 0 | 106 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 20 | 0.00 | -| MMCME2_ADV | 0 | 0 | 5 | 0.00 | -| PLLE2_ADV | 0 | 0 | 5 | 0.00 | -| BUFMRCE | 0 | 0 | 10 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 20 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 330 | Flop & Latch | -| LUT6 | 209 | LUT | -| LUT3 | 67 | LUT | -| LUT5 | 55 | LUT | -| LUT2 | 51 | LUT | -| LUT4 | 41 | LUT | -| CARRY4 | 33 | CarryLogic | -| MUXF7 | 19 | MuxFx | -| FDSE | 12 | Flop & Latch | -| OBUF | 8 | IO | -| IBUF | 5 | IO | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/VHDL/ALU/ALU.runs/impl_1/gen_run.xml b/VHDL/ALU/ALU.runs/impl_1/gen_run.xml deleted file mode 100644 index 8005842..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,171 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/impl_1/htr.txt b/VHDL/ALU/ALU.runs/impl_1/htr.txt deleted file mode 100644 index 4c3500d..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -vivado -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/impl_1/init_design.pb b/VHDL/ALU/ALU.runs/impl_1/init_design.pb deleted file mode 100644 index 8ca3bfc..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/init_design.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/opt_design.pb b/VHDL/ALU/ALU.runs/impl_1/opt_design.pb deleted file mode 100644 index c2d41e5..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/opt_design.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/place_design.pb b/VHDL/ALU/ALU.runs/impl_1/place_design.pb deleted file mode 100644 index a57c02b..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/place_design.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/project.wdf b/VHDL/ALU/ALU.runs/impl_1/project.wdf deleted file mode 100644 index 279e5aa..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/project.wdf +++ /dev/null @@ -1,31 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00 -eof:1726599244 diff --git a/VHDL/ALU/ALU.runs/impl_1/route_design.pb b/VHDL/ALU/ALU.runs/impl_1/route_design.pb deleted file mode 100644 index fa0cf95..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/route_design.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/rundef.js b/VHDL/ALU/ALU.runs/impl_1/rundef.js deleted file mode 100644 index 7dc8d03..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/rundef.js +++ /dev/null @@ -1,44 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;"; -} else { - PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -// pre-commands: -ISETouchFile( "init_design", "begin" ); -ISEStep( "vivado", - "-log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace" ); - - - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.bat b/VHDL/ALU/ALU.runs/impl_1/runme.bat deleted file mode 100644 index 8eb74b1..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.log b/VHDL/ALU/ALU.runs/impl_1/runme.log deleted file mode 100644 index a508221..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/runme.log +++ /dev/null @@ -1,471 +0,0 @@ - -*** Running vivado - with args -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace - - -****** Vivado v2018.2 (64-bit) - **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 - **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 - ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - -source Pipeline.tcl -notrace -Command: link_design -top Pipeline -part xc7a35tcpg236-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.2 -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 1e379f571 - -Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1e379f571 - -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 224c05fcb - -Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 237fe1223 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 237fe1223 - -Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -Ending Logic Optimization Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 141d47eb5 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594 -INFO: [Common 17-83] Releasing license: Implementation -23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx -Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db - -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd - -Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -Phase 1 Placer Initialization | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: e4604ef0 - -Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539 -WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 15cb247ff - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Phase 3 Detail Placement | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 112e53995 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 - -Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529 -Ending Placer Task | Checksum: 8268151a - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535 -INFO: [Common 17-83] Releasing license: Implementation -41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. -place_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537 -INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544 -INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs -Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437 -Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 77742d47 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422 - Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 16523de4e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 11b0f7581 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 97 - Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 -Phase 4 Rip-up And Reroute | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 -Phase 6 Post Hold Fix | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.153313 % - Global Horizontal Routing Utilization = 0.172046 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Congestion Report -North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 14cade65a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 16fad2baa - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427 -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx -Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx -Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 6 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx -Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. -INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -Command: write_bitstream -force Pipeline.bit -Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' -Running DRC as a precondition to command write_bitstream -INFO: [DRC 23-27] Running DRC with 6 threads -WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2. -WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7. -WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings -INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. -Loading data files... -Loading site data... -Loading route data... -Processing options... -Creating bitmap... -Creating bitstream... -Writing bitstream ./Pipeline.bit... -INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. -INFO: [Common 17-83] Releasing license: Implementation -84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered. -write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368 -INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023... diff --git a/VHDL/ALU/ALU.runs/impl_1/runme.sh b/VHDL/ALU/ALU.runs/impl_1/runme.sh deleted file mode 100755 index 877ede8..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin -else - PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64 -else - LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -# pre-commands: -/bin/touch .init_design.begin.rst -EAStep vivado -log Pipeline.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace - - diff --git a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html deleted file mode 100644 index ce67df4..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html +++ /dev/null @@ -1,867 +0,0 @@ -Device Usage Statistics Report -

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

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software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedWed May 31 17:58:23 2023os_platformLIN64
product_versionVivado v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration12random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

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user_environment
cpu_nameIntel(R) Core(TM) i5-9500 CPU @ 3.00GHzcpu_speed3000.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram16.000 GBtotal_processors1

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vivado_usage
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gui_handlers
abstractcombinedpanel_add_element=36abstractcombinedpanel_remove_selected_elements=13abstractfileview_close=1abstractfileview_reload=1
addsrcwizard_specify_hdl_netlist_block_design=1addsrcwizard_specify_or_create_constraint_files=4addsrcwizard_specify_simulation_specific_hdl_files=3basedialog_apply=2
basedialog_cancel=31basedialog_no=2basedialog_ok=234basedialog_yes=40
clockcreationpanel_clock_name=1clockcreationpanel_enter_positive_number=5cmdmsgdialog_messages=6cmdmsgdialog_ok=33
cmdmsgdialog_open_messages_view=1combinationalconstraintstablepanel_table=1commandsinput_type_tcl_command_here=4constraintschooserpanel_add_existing_or_create_new_constraints=5
constraintschooserpanel_add_files=4constraintschooserpanel_create_file=4constraintschooserpanel_file_table=2createconstraintsfilepanel_file_name=3
createrunreportdialog_report_name=1createsrcfiledialog_file_name=15createsrcfiledialog_file_type=1definemodulesdialog_define_modules_and_specify_io_ports=148
definemodulesdialog_entity_name=3editcreateclocktablepanel_edit_create_clock_table=13expreporttreepanel_edit_report_options=1expreporttreepanel_exp_report_tree_table=9
expruntreepanel_exp_run_tree_table=2filesetpanel_file_set_panel_tree=606filesetpanel_messages=1flownavigatortreepanel_flow_navigator_tree=374
gettingstartedview_create_new_project=1gettingstartedview_open_project=3graphicalview_zoom_fit=6graphicalview_zoom_in=135
graphicalview_zoom_out=149hcodeeditor_close=2hcodeeditor_search_text_combo_box=40hinputhandler_toggle_line_comments=1
hpopuptitle_close=1inputoutputtablepanel_table=1logmonitor_monitor=1logpanel_copy=1
logpanel_find=1logpanel_pause_output=2logpanel_toggle_column_selection_mode=2mainmenumgr_checkpoint=18
mainmenumgr_edit=16mainmenumgr_export=7mainmenumgr_file=76mainmenumgr_flow=10
mainmenumgr_io_planning=1mainmenumgr_ip=12mainmenumgr_open_recent_project=25mainmenumgr_project=51
mainmenumgr_reports=12mainmenumgr_settings=2mainmenumgr_simulation_waveform=15mainmenumgr_text_editor=10
mainmenumgr_timing=1mainmenumgr_tools=16mainmenumgr_unselect_type=1mainmenumgr_view=8
mainmenumgr_window=16maintoolbarmgr_run=7mainwinmenumgr_layout=12mainwinmenumgr_load=1
messagewithoptiondialog_dont_show_this_dialog_again=1msgtreepanel_message_severity=1msgtreepanel_message_view_tree=172msgview_clear_messages_resulting_from_user_executed=9
msgview_critical_warnings=2msgview_error_messages=2msgview_information_messages=3msgview_warning_messages=1
navigabletimingreporttab_timing_report_navigation_tree=5numjobschooser_number_of_jobs=2openfileaction_cancel=2openfileaction_open_directory=4
opentargetwizard_connect_to=3packagetreepanel_package_tree_panel=5pacommandnames_add_config_memory=3pacommandnames_add_sources=21
pacommandnames_auto_connect_target=2pacommandnames_auto_update_hier=26pacommandnames_fileset_window=3pacommandnames_goto_instantiation=1
pacommandnames_log_window=10pacommandnames_open_project=1pacommandnames_open_recent_target=3pacommandnames_open_target_wizard=4
pacommandnames_program_fpga=4pacommandnames_report_clock_networks=1pacommandnames_reports_window=5pacommandnames_run_bitgen=1
pacommandnames_run_synthesis=3pacommandnames_set_as_top=6pacommandnames_set_target_ucf=3pacommandnames_simulation_relaunch=5
pacommandnames_simulation_reset=1pacommandnames_simulation_run=1pacommandnames_simulation_run_behavioral=174pacommandnames_simulation_run_post_synthesis_functional=1
pacommandnames_simulation_settings=9pacommandnames_src_replace_file=5paviews_code=41paviews_device=3
paviews_project_summary=2planaheadtab_show_flow_navigator=4primaryclockspanel_recommended_constraints_table=6programdebugtab_open_recently_opened_target=13
programdebugtab_open_target=2programdebugtab_refresh_device=1programfpgadialog_check_end_of_startup=1programfpgadialog_program=12
programfpgadialog_specify_bitstream_file=2progressdialog_background=16progressdialog_cancel=1projectsettingsgadget_edit_project_settings=2
projectsettingssimulationpanel_select_testbench_top_module=2projectsettingssimulationpanel_tabbed_pane=7projecttab_close_design=4projecttab_reload=7
rdicommands_custom_commands=4rdicommands_delete=5rdicommands_line_comment=23rdicommands_save_file=10
rdiviews_waveform_viewer=787removesourcesdialog_also_delete=1reportnavigationholder_rerun=2rtloptionspanel_select_top_module_of_your_design=2
rungadget_show_error_and_critical_warning_messages=1saveprojectutils_cancel=1saveprojectutils_save=46selecttopmoduledialog_select_top_module=8
settingsdialog_project_tree=1signaltreepanel_signal_tree_table=13simulationobjectspanel_simulation_objects_tree_table=55simulationscopespanel_simulate_scope_table=80
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=4srcchooserpanel_add_or_create_source_file=21srcchooserpanel_create_file=15srcchoosertable_src_chooser_table=2
srcmenu_ip_hierarchy=26srcmenu_refresh_hierarchy=2stalerundialog_yes=2statemonitor_reset_run=3
syntheticagettingstartedview_recent_projects=8syntheticastatemonitor_cancel=8taskbanner_close=6tclconsoleview_clear_all_output_in_tcl_console=3
tclconsoleview_tcl_console_code_editor=50timingconstraintswizard_create_check_timing_report=6timingconstraintswizard_create_methodology_report=2timingconstraintswizard_create_timing_summary_report=6
timingconstraintswizard_goto_constraints_summary_page=4timingconstraintswizard_view_timing_constraints=6touchpointsurveydialog_no=1waveformnametree_waveform_name_tree=275
waveformoptionsview_reset_to_defaults=1waveformoptionsview_show_signal_indices=4waveformview_add_marker=4waveformview_goto_last_time=4
waveformview_goto_time_0=3waveformview_next_marker=3xdceditorview_apply_all_changes_to_xdc_constraints=2xdcviewertreetablepanel_xdc_viewer_tree_table=4
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java_command_handlers
addcfgmem=1addsources=24autoconnecttarget=2closeproject=2
editdelete=5editpaste=5editundo=1launchopentarget=4
launchprogramfpga=15newproject=1openhardwaremanager=24openproject=4
openrecenttarget=14programdevice=18reporttimingsummary=1runbitgen=47
runimplementation=6runsynthesis=22savefileproxyhandler=4settargetconstrfile=3
settopnode=1showsource=1showview=53simulationrelaunch=5
simulationrun=172timingconstraintswizard=7toggleviewnavigator=4toolssettings=15
updatesourcefiles=5viewlayoutcmd=1viewtaskimplementation=4viewtasksynthesis=1
waveformsaveconfiguration=13xdccreateclock=1
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other_data
guimode=24
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project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=174simulator_language=Mixedsrcsetcount=11synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDLtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
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unisim_transformation
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post_unisim_transformation
bufg=1carry4=33fdre=330fdse=12
gnd=8ibuf=5lut2=51lut3=67
lut4=41lut5=55lut6=209muxf7=19
obuf=8vcc=5
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pre_unisim_transformation
bufg=1carry4=33fdre=330fdse=12
gnd=8ibuf=5lut2=51lut3=67
lut4=41lut5=55lut6=209muxf7=19
obuf=8vcc=5
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report_drc
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command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
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results
cfgbvs-1=1lutlp-2=2nstd-1=1ucio-1=1
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usage
nstd-1=Warningucio-1=Warning
-

- - - - - -
report_methodology
- - - - - - - - - - - -
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
-
- - - - -
results
timing-17=342timing-23=1
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- - - - -
usage
nstd-1=Warningucio-1=Warning
-

- - - - -
report_power
- - - - - - - - - - - - - - - -
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.081472die=xc7a35tcpg236-1
dsp_output_toggle=12.500000dynamic=3.252769effective_thetaja=5.0enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=0.804337input_toggle=12.500000junction_temp=41.7 (C)logic=1.293960
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=3.334241output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=cpg236pct_clock_constrained=0.860000
pct_inputs_defined=0platform=lin64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=1.154472simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=7.5 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=5.0user_junc_temp=41.7 (C)user_thetajb=7.5 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.028741vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.013356vccaux_total_current=0.042097
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000299vccbram_total_current=0.000299
vccbram_voltage=1.000000vccint_dynamic_current=2.468432vccint_static_current=0.017832vccint_total_current=2.486264
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=0.222001vcco33_static_current=0.001000vcco33_total_current=0.223001
vcco33_voltage=3.300000version=2018.2
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report_utilization
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clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
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dsp
dsps_available=90dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
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io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=1lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
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memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
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primitives
bufg_functional_category=Clockbufg_used=1carry4_functional_category=CarryLogiccarry4_used=33
fdre_functional_category=Flop & Latchfdre_used=330fdse_functional_category=Flop & Latchfdse_used=12
ibuf_functional_category=IOibuf_used=5lut2_functional_category=LUTlut2_used=51
lut3_functional_category=LUTlut3_used=67lut4_functional_category=LUTlut4_used=41
lut5_functional_category=LUTlut5_used=55lut6_functional_category=LUTlut6_used=209
muxf7_functional_category=MuxFxmuxf7_used=19obuf_functional_category=IOobuf_used=8
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slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=19f7_muxes_util_percentage=0.12
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=371lut_as_logic_util_percentage=1.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=342register_as_flip_flop_util_percentage=0.82
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=371slice_luts_util_percentage=1.78
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=342slice_registers_util_percentage=0.82
fully_used_lut_ff_pairs_fixed=0.82fully_used_lut_ff_pairs_used=5lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=371lut_as_logic_util_percentage=1.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=37
lut_ff_pairs_with_one_unused_lut_output_fixed=37lut_ff_pairs_with_one_unused_lut_output_used=42lut_flip_flop_pairs_available=20800lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=48lut_flip_flop_pairs_util_percentage=0.23slice_available=8150slice_fixed=0
slice_used=158slice_util_percentage=1.94slicel_fixed=0slicel_used=103
slicem_fixed=0slicem_used=55unique_control_sets_used=36using_o5_and_o6_fixed=36
using_o5_and_o6_used=52using_o5_output_only_fixed=52using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=319
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specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
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router
- - - - - - - - - - - - - - - - - - - - - - - - - -
usage
actual_expansions=336796bogomips=6000bram18=0bram36=0
bufg=0bufr=0ctrls=36dsp=0
effort=2estimated_expansions=475116ff=342global_clocks=1
high_fanout_nets=0iob=13lut=371movable_instances=844
nets=925pins=4840pll=0router_runtime=0.000000
router_timing_driven=1threads=6timing_constraints_exist=1
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- - - - -
synthesis
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a35tcpg236-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=Pipeline-verilog_define=default::[not_specified]
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usage
elapsed=00:00:23shls_ip=0memory_gain=491.398MBmemory_peak=1651.219MB
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xsim
- - - - -
command_line_options
-sim_mode=default::behavioral-sim_type=default::
-

- - diff --git a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml b/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml deleted file mode 100644 index 65eff10..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.xml +++ /dev/null @@ -1,790 +0,0 @@ - - -
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- diff --git a/VHDL/ALU/ALU.runs/impl_1/vivado.jou b/VHDL/ALU/ALU.runs/impl_1/vivado.jou deleted file mode 100644 index 52cab70..0000000 --- a/VHDL/ALU/ALU.runs/impl_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 17:57:08 2023 -# Process ID: 144223 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1 -# Command line: vivado -log Pipeline.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/vivado.jou -#----------------------------------------------------------- -source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/impl_1/vivado.pb b/VHDL/ALU/ALU.runs/impl_1/vivado.pb deleted file mode 100644 index d3f674c..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/vivado.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb b/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb deleted file mode 100644 index 63ae9a4..0000000 Binary files a/VHDL/ALU/ALU.runs/impl_1/write_bitstream.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst b/VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc b/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc deleted file mode 100644 index 252a926..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/.Xil/Pipeline_propImpl.xdc +++ /dev/null @@ -1,31 +0,0 @@ -set_property SRC_FILE_INFO {cfile:/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc rfile:../../../ALU.srcs/constrs_1/new/test_cpu.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R2 [get_ports CLK] -set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports CLK] -set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] -set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets {Stage2/Jump_Flag}] -set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[0]}] -set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[1]}] -set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[2]}] -set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[3]}] -set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {reg_val[0]}] -set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {reg_val[1]}] -set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {reg_val[2]}] -set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {reg_val[3]}] -set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {reg_val[4]}] -set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {reg_val[5]}] -set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {reg_val[6]}] -set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {reg_val[7]}] diff --git a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst b/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst deleted file mode 100644 index 7836eeb..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst b/VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/synth_1/ISEWrap.js b/VHDL/ALU/ALU.runs/synth_1/ISEWrap.js deleted file mode 100755 index 8284d2d..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/ISEWrap.js +++ /dev/null @@ -1,244 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh b/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh deleted file mode 100755 index e1a8f5d..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp b/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp deleted file mode 100644 index a133e7e..0000000 Binary files a/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl b/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl deleted file mode 100644 index 0ca503b..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl +++ /dev/null @@ -1,68 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param xicom.use_bs_reader 1 -create_project -in_memory -part xc7a35tcpg236-1 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project] -set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] -set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_vhdl -library xil_defaultlib { - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd - /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd -} -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc -set_property used_in_implementation false [get_files /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] - -set_param ips.enableIPCacheLiteLoad 0 -close [open __synthesis_is_running__ w] - -synth_design -top Pipeline -part xc7a35tcpg236-1 - - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef Pipeline.dcp -create_report "synth_1_synth_report_utilization_0" "report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb" -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds b/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds deleted file mode 100644 index 796a1fd..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds +++ /dev/null @@ -1,619 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 17:56:19 2023 -# Process ID: 144089 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 -# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou -#----------------------------------------------------------- -source Pipeline.tcl -notrace -Command: synth_design -top Pipeline -part xc7a35tcpg236-1 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 144101 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.828 ; free physical = 7354 ; free virtual = 19137 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:182] -INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:192] -INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:198] -INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:210] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:224] -INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:236] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] -WARNING: [Synth 8-614] signal 'JumpFlagIn' is read in the process but is not in the sensitivity list [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:68] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:249] -INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] -INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:268] -INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:339] -INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] -WARNING: [Synth 8-3331] design InstructionMemory has unconnected port Clk ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7345 ; free virtual = 19128 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-507] No nets matched 'Stage2/Jump_Flag'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Pipeline_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/Pipeline_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Completed Processing XDC Constraints - -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000 ; free physical = 7109 ; free virtual = 18892 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- -INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse -INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7161 ; free virtual = 18945 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 9 Bit Adders := 1 - 2 Input 8 Bit Adders := 2 - 3 Input 8 Bit Adders := 1 -+---Registers : - 8 Bit Registers := 287 -+---Muxes : - 257 Input 32 Bit Muxes := 1 - 2 Input 8 Bit Muxes := 13 - 2 Input 1 Bit Muxes := 279 - 12 Input 1 Bit Muxes := 3 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module Pipeline -Detailed RTL Component Info : -+---Muxes : - 2 Input 8 Bit Muxes := 7 - 2 Input 1 Bit Muxes := 1 -Module IP -Detailed RTL Component Info : -+---Adders : - 2 Input 8 Bit Adders := 1 -+---Registers : - 8 Bit Registers := 1 -+---Muxes : - 2 Input 8 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 1 -Module InstructionMemory -Detailed RTL Component Info : -+---Muxes : - 257 Input 32 Bit Muxes := 1 -Module Stage_Li_Di -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 4 -Module Registers -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 16 -+---Muxes : - 2 Input 8 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 16 -Module Stage_Di_Ex -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 4 -Module ALU -Detailed RTL Component Info : -+---Adders : - 2 Input 9 Bit Adders := 1 - 3 Input 8 Bit Adders := 1 - 2 Input 8 Bit Adders := 1 -+---Muxes : - 2 Input 8 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 5 - 12 Input 1 Bit Muxes := 3 -Module Stage_Ex_Mem -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 3 -Module DataMemory -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 256 -+---Muxes : - 2 Input 1 Bit Muxes := 256 -Module Stage_Mem_Re -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 3 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[5]' (FD) to 'Stage1/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[7]' (FD) to 'Stage1/Out_Op_reg[6]' -INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[6]' (FD) to 'Stage2/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[7]' (FD) to 'Stage2/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[6]' (FD) to 'Stage3/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[7]' (FD) to 'Stage3/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[6]' (FD) to 'Stage4/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[7]' (FD) to 'Stage4/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[46][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[47][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[44][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[45][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[42][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[43][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[40][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[41][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[38][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[39][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[36][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[37][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[34][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[35][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[32][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[33][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[62][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[63][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[60][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[61][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[58][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[59][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[56][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[57][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[54][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[55][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[52][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[53][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[50][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[51][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[48][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[49][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[30][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[31][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[28][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[29][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[26][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[27][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[24][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[25][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[22][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[23][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[20][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[21][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[18][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[19][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[16][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[17][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[238][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[239][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[236][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[237][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[234][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[235][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[232][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[233][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[230][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[231][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[228][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[229][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[226][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[227][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[224][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[225][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[254][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[255][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[252][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[253][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[250][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[251][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[248][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[249][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[246][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[247][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[244][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[245][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[242][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[243][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[240][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[241][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[206][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[207][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[204][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[205][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[202][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[203][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[200][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[201][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[198][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[199][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[196][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[197][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][3] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[153][7] ) -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[153][7]) is unused and will be removed from module Pipeline. ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7123 ; free virtual = 18911 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18799 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18798 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |BUFG | 1| -|2 |CARRY4 | 33| -|3 |LUT2 | 51| -|4 |LUT3 | 67| -|5 |LUT4 | 41| -|6 |LUT5 | 55| -|7 |LUT6 | 209| -|8 |MUXF7 | 19| -|9 |FDRE | 330| -|10 |FDSE | 12| -|11 |IBUF | 5| -|12 |OBUF | 8| -+------+-------+------+ - -Report Instance Areas: -+------+-----------------+-------------+------+ -| |Instance |Module |Cells | -+------+-----------------+-------------+------+ -|1 |top | | 831| -|2 | DataMem |DataMemory | 168| -|3 | Stage1 |Stage_Li_Di | 35| -|4 | Stage2 |Stage_Di_Ex | 213| -|5 | Stage3 |Stage_Ex_Mem | 63| -|6 | Stage4 |Stage_Mem_Re | 37| -|7 | StageRegisters |Registers | 230| -|8 | Ual |ALU | 35| -|9 | inst_point |IP | 36| -+------+-----------------+-------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1651.219 ; gain = 139.453 ; free physical = 7056 ; free virtual = 18845 -Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7056 ; free virtual = 18845 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -270 Infos, 15 Warnings, 3 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 1659.227 ; gain = 499.406 ; free physical = 7043 ; free virtual = 18832 -WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1683.238 ; gain = 0.000 ; free physical = 7046 ; free virtual = 18834 -INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:57:07 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb deleted file mode 100644 index 3e7476f..0000000 Binary files a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt b/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt deleted file mode 100644 index f247b36..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.rpt +++ /dev/null @@ -1,182 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Wed May 31 17:57:07 2023 -| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -| Design : Pipeline -| Device : 7a35tcpg236-1 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 371 | 0 | 20800 | 1.78 | -| LUT as Logic | 371 | 0 | 20800 | 1.78 | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 342 | 0 | 41600 | 0.82 | -| Register as Flip Flop | 342 | 0 | 41600 | 0.82 | -| Register as Latch | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 19 | 0 | 16300 | 0.12 | -| F8 Muxes | 0 | 0 | 8150 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 12 | Yes | Set | - | -| 330 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 50 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | -| RAMB18 | 0 | 0 | 100 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 90 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 13 | 0 | 106 | 12.26 | -| Bonded IPADs | 0 | 0 | 10 | 0.00 | -| Bonded OPADs | 0 | 0 | 4 | 0.00 | -| PHY_CONTROL | 0 | 0 | 5 | 0.00 | -| PHASER_REF | 0 | 0 | 5 | 0.00 | -| OUT_FIFO | 0 | 0 | 20 | 0.00 | -| IN_FIFO | 0 | 0 | 20 | 0.00 | -| IDELAYCTRL | 0 | 0 | 5 | 0.00 | -| IBUFDS | 0 | 0 | 104 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 106 | 0.00 | -| OLOGIC | 0 | 0 | 106 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 20 | 0.00 | -| MMCME2_ADV | 0 | 0 | 5 | 0.00 | -| PLLE2_ADV | 0 | 0 | 5 | 0.00 | -| BUFMRCE | 0 | 0 | 10 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 20 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 330 | Flop & Latch | -| LUT6 | 209 | LUT | -| LUT3 | 67 | LUT | -| LUT5 | 55 | LUT | -| LUT2 | 51 | LUT | -| LUT4 | 41 | LUT | -| CARRY4 | 33 | CarryLogic | -| MUXF7 | 19 | MuxFx | -| FDSE | 12 | Flop & Latch | -| OBUF | 8 | IO | -| IBUF | 5 | IO | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__ b/VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml deleted file mode 100644 index 2247bbd..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/ALU/ALU.runs/synth_1/htr.txt b/VHDL/ALU/ALU.runs/synth_1/htr.txt deleted file mode 100644 index 5197eaa..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -vivado -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl diff --git a/VHDL/ALU/ALU.runs/synth_1/rundef.js b/VHDL/ALU/ALU.runs/synth_1/rundef.js deleted file mode 100644 index 7a46510..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;"; -} else { - PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.bat b/VHDL/ALU/ALU.runs/synth_1/runme.bat deleted file mode 100644 index 8eb74b1..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.log b/VHDL/ALU/ALU.runs/synth_1/runme.log deleted file mode 100644 index f824df8..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/runme.log +++ /dev/null @@ -1,618 +0,0 @@ - -*** Running vivado - with args -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl - - -****** Vivado v2018.2 (64-bit) - **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 - **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 - ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - -source Pipeline.tcl -notrace -Command: synth_design -top Pipeline -part xc7a35tcpg236-1 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 144101 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1255.273 ; gain = 83.828 ; free physical = 7354 ; free virtual = 19137 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] -INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:182] -INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45] -INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:192] -INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41] -INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:198] -INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47] -INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:210] -INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] -INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:49] -INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:224] -INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47] -INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:236] -INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] -WARNING: [Synth 8-614] signal 'JumpFlagIn' is read in the process but is not in the sensitivity list [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:68] -INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:64] -INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:249] -INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45] -INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259] -INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44] -INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:268] -INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45] -INFO: [Synth 8-3491] module 'AleaControler' declared at '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:28' bound to instance 'CU' of component 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:339] -INFO: [Synth 8-638] synthesizing module 'AleaControler' [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -INFO: [Synth 8-256] done synthesizing module 'AleaControler' (10#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd:40] -INFO: [Synth 8-256] done synthesizing module 'Pipeline' (11#1) [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:40] -WARNING: [Synth 8-3331] design InstructionMemory has unconnected port Clk ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7345 ; free virtual = 19128 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1310.898 ; gain = 139.453 ; free physical = 7348 ; free virtual = 19131 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-507] No nets matched 'Stage2/Jump_Flag'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:9] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Pipeline_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/Pipeline_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Completed Processing XDC Constraints - -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000 ; free physical = 7109 ; free virtual = 18892 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7183 ; free virtual = 18967 ---------------------------------------------------------------------------------- -INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) -INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse -INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse -INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7161 ; free virtual = 18945 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 9 Bit Adders := 1 - 2 Input 8 Bit Adders := 2 - 3 Input 8 Bit Adders := 1 -+---Registers : - 8 Bit Registers := 287 -+---Muxes : - 257 Input 32 Bit Muxes := 1 - 2 Input 8 Bit Muxes := 13 - 2 Input 1 Bit Muxes := 279 - 12 Input 1 Bit Muxes := 3 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module Pipeline -Detailed RTL Component Info : -+---Muxes : - 2 Input 8 Bit Muxes := 7 - 2 Input 1 Bit Muxes := 1 -Module IP -Detailed RTL Component Info : -+---Adders : - 2 Input 8 Bit Adders := 1 -+---Registers : - 8 Bit Registers := 1 -+---Muxes : - 2 Input 8 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 1 -Module InstructionMemory -Detailed RTL Component Info : -+---Muxes : - 257 Input 32 Bit Muxes := 1 -Module Stage_Li_Di -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 4 -Module Registers -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 16 -+---Muxes : - 2 Input 8 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 16 -Module Stage_Di_Ex -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 4 -Module ALU -Detailed RTL Component Info : -+---Adders : - 2 Input 9 Bit Adders := 1 - 3 Input 8 Bit Adders := 1 - 2 Input 8 Bit Adders := 1 -+---Muxes : - 2 Input 8 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 5 - 12 Input 1 Bit Muxes := 3 -Module Stage_Ex_Mem -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 3 -Module DataMemory -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 256 -+---Muxes : - 2 Input 1 Bit Muxes := 256 -Module Stage_Mem_Re -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 3 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51] -WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55] -INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[5]' (FD) to 'Stage1/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage1/Out_Op_reg[7]' (FD) to 'Stage1/Out_Op_reg[6]' -INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[6]' (FD) to 'Stage2/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage2/Out_Op_reg[7]' (FD) to 'Stage2/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[6]' (FD) to 'Stage3/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage3/Out_Op_reg[7]' (FD) to 'Stage3/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[6]' (FD) to 'Stage4/Out_Op_reg[7]' -INFO: [Synth 8-3886] merging instance 'Stage4/Out_Op_reg[7]' (FD) to 'Stage4/Out_Op_reg[5]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[46][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[47][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[44][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[45][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[42][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[43][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[40][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[41][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[38][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[39][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[36][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[37][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[34][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[35][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[32][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[33][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[62][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[63][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[60][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[61][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[58][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[59][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[56][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[57][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[54][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[55][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[52][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[53][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[50][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[51][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[48][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[49][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[30][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[31][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[28][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[29][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[26][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[27][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[24][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[25][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[22][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[23][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[20][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[21][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[18][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[19][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[16][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[17][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[238][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[239][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[236][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[237][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[234][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[235][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[232][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[233][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[230][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[231][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[228][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[229][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[226][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[227][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[224][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[225][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[254][0]' (FDRE) to 'DataMem/Mem_reg[255][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[255][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[252][0]' (FDRE) to 'DataMem/Mem_reg[253][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[253][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[250][0]' (FDRE) to 'DataMem/Mem_reg[251][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[251][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[248][0]' (FDRE) to 'DataMem/Mem_reg[249][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[249][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[246][0]' (FDRE) to 'DataMem/Mem_reg[247][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[247][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[244][0]' (FDRE) to 'DataMem/Mem_reg[245][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[245][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[242][0]' (FDRE) to 'DataMem/Mem_reg[243][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[243][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[240][0]' (FDRE) to 'DataMem/Mem_reg[241][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[241][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[206][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[207][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[204][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[205][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[202][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[203][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[200][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[201][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[198][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[199][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[196][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Synth 8-3886] merging instance 'DataMem/Mem_reg[197][0]' (FDRE) to 'DataMem/Mem_reg[223][0]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][3] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[209][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[145][6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (\DataMem/Mem_reg[153][7] ) -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][0]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][1]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][2]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][3]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][4]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[209][5]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[145][6]) is unused and will be removed from module Pipeline. -WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[153][7]) is unused and will be removed from module Pipeline. ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7123 ; free virtual = 18911 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18799 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7010 ; free virtual = 18798 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-------+------+ -| |Cell |Count | -+------+-------+------+ -|1 |BUFG | 1| -|2 |CARRY4 | 33| -|3 |LUT2 | 51| -|4 |LUT3 | 67| -|5 |LUT4 | 41| -|6 |LUT5 | 55| -|7 |LUT6 | 209| -|8 |MUXF7 | 19| -|9 |FDRE | 330| -|10 |FDSE | 12| -|11 |IBUF | 5| -|12 |OBUF | 8| -+------+-------+------+ - -Report Instance Areas: -+------+-----------------+-------------+------+ -| |Instance |Module |Cells | -+------+-----------------+-------------+------+ -|1 |top | | 831| -|2 | DataMem |DataMemory | 168| -|3 | Stage1 |Stage_Li_Di | 35| -|4 | Stage2 |Stage_Di_Ex | 213| -|5 | Stage3 |Stage_Ex_Mem | 63| -|6 | Stage4 |Stage_Mem_Re | 37| -|7 | StageRegisters |Registers | 230| -|8 | Ual |ALU | 35| -|9 | inst_point |IP | 36| -+------+-----------------+-------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7000 ; free virtual = 18789 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1651.219 ; gain = 139.453 ; free physical = 7056 ; free virtual = 18845 -Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:38 . Memory (MB): peak = 1651.219 ; gain = 479.773 ; free physical = 7056 ; free virtual = 18845 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -270 Infos, 15 Warnings, 3 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 1659.227 ; gain = 499.406 ; free physical = 7043 ; free virtual = 18832 -WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1683.238 ; gain = 0.000 ; free physical = 7046 ; free virtual = 18834 -INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:57:07 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.sh b/VHDL/ALU/ALU.runs/synth_1/runme.sh deleted file mode 100755 index ae5d7fd..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin -else - PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64 -else - LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.jou b/VHDL/ALU/ALU.runs/synth_1/vivado.jou deleted file mode 100644 index 8c57bba..0000000 --- a/VHDL/ALU/ALU.runs/synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 17:56:19 2023 -# Process ID: 144089 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 -# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou -#----------------------------------------------------------- -source Pipeline.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.pb b/VHDL/ALU/ALU.runs/synth_1/vivado.pb deleted file mode 100644 index e50866e..0000000 Binary files a/VHDL/ALU/ALU.runs/synth_1/vivado.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl deleted file mode 100644 index 1094e45..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run 1000ns diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb deleted file mode 100644 index 3907a60..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_behav.wdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_vhdl.prj b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_vhdl.prj deleted file mode 100644 index 5563d21..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Pipeline_vhdl.prj +++ /dev/null @@ -1,16 +0,0 @@ -# compile vhdl design source files -vhdl xil_defaultlib \ -"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ -"../../../../ALU.srcs/sources_1/new/AleaControler.vhd" \ -"../../../../ALU.srcs/sources_1/new/IP.vhd" \ -"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \ -"../../../../ALU.srcs/sources_1/new/Memory.vhd" \ -"../../../../ALU.srcs/sources_1/new/Registers.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \ -"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \ - -# Do not sort compile order -nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl deleted file mode 100644 index 1094e45..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run 1000ns diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb deleted file mode 100644 index f944d5a..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj deleted file mode 100644 index 566e460..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj +++ /dev/null @@ -1,7 +0,0 @@ -# compile vhdl design source files -vhdl xil_defaultlib \ -"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ -"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ - -# Do not sort compile order -nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl deleted file mode 100644 index bcdbdc2..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run 100us diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb deleted file mode 100644 index c62301b..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj deleted file mode 100644 index bfcc4c8..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj +++ /dev/null @@ -1,17 +0,0 @@ -# compile vhdl design source files -vhdl xil_defaultlib \ -"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ -"../../../../ALU.srcs/sources_1/new/AleaControler.vhd" \ -"../../../../ALU.srcs/sources_1/new/IP.vhd" \ -"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \ -"../../../../ALU.srcs/sources_1/new/Memory.vhd" \ -"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \ -"../../../../ALU.srcs/sources_1/new/Registers.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \ -"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \ -"../../../../ALU.srcs/sim_1/new/test_total.vhd" \ - -# Do not sort compile order -nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log deleted file mode 100644 index abd0c43..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log +++ /dev/null @@ -1,428 +0,0 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:88] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -ERROR: [VRFC 10-1412] syntax error near B [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:74] -ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61] -INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity IP -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Li_Di -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_Alu -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity IP -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Li_Di -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity IP -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -ERROR: [VRFC 10-825] illegal identifier : __En [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:38] -ERROR: [VRFC 10-1504] unit instructionmemory ignored due to previous errors [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35] -INFO: [VRFC 10-240] VHDL file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd ignored due to errors -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity DataMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity InstructionMemory -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Test_total -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Registers -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity ALU -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity AleaControler -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh deleted file mode 100755 index 5525f79..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/bash -f -# **************************************************************************** -# Vivado (TM) v2018.2 (64-bit) -# -# Filename : compile.sh -# Simulator : Xilinx Vivado Simulator -# Description : Script for compiling the simulation design source files -# -# Generated by Vivado on Wed May 31 18:24:50 CEST 2023 -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# -# usage: compile.sh -# -# **************************************************************************** -ExecStep() -{ -"$@" -RETVAL=$? -if [ $RETVAL -ne 0 ] -then -exit $RETVAL -fi -} -echo "xvhdl --incr --relax -prj Test_total_vhdl.prj" -ExecStep xvhdl --incr --relax -prj Test_total_vhdl.prj 2>&1 | tee -a compile.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log deleted file mode 100644 index e0fb715..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log +++ /dev/null @@ -1,28 +0,0 @@ -Vivado Simulator 2018.2 -Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. -Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log -Using 8 slave threads. -Starting static elaboration -Completed static elaboration -Starting simulation data flow analysis -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling package std.standard -Compiling package std.textio -Compiling package ieee.std_logic_1164 -Compiling package ieee.std_logic_arith -Compiling package ieee.std_logic_unsigned -Compiling package ieee.numeric_std -Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default] -Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default] -Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default] -Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default] -Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default] -Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default] -Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default] -Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default] -Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default] -Compiling architecture behavioral of entity xil_defaultlib.AleaControler [aleacontroler_default] -Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default] -Compiling architecture behavioral of entity xil_defaultlib.test_total -Built simulation snapshot Test_total_behav diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh deleted file mode 100755 index 06902b4..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash -f -# **************************************************************************** -# Vivado (TM) v2018.2 (64-bit) -# -# Filename : elaborate.sh -# Simulator : Xilinx Vivado Simulator -# Description : Script for elaborating the compiled design -# -# Generated by Vivado on Wed May 31 18:24:52 CEST 2023 -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# -# usage: elaborate.sh -# -# **************************************************************************** -ExecStep() -{ -"$@" -RETVAL=$? -if [ $RETVAL -ne 0 ] -then -exit $RETVAL -fi -} -ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log deleted file mode 100644 index 2cc3412..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log +++ /dev/null @@ -1,2 +0,0 @@ -Vivado Simulator 2018.2 -Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh deleted file mode 100755 index bc7c372..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash -f -# **************************************************************************** -# Vivado (TM) v2018.2 (64-bit) -# -# Filename : simulate.sh -# Simulator : Xilinx Vivado Simulator -# Description : Script for simulating the design by launching the simulator -# -# Generated by Vivado on Wed May 31 18:24:54 CEST 2023 -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# -# usage: simulate.sh -# -# **************************************************************************** -ExecStep() -{ -"$@" -RETVAL=$? -if [ $RETVAL -ne 0 ] -then -exit $RETVAL -fi -} -ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou deleted file mode 100644 index 4f85255..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 16:13:36 2023 -# Process ID: 12761 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log deleted file mode 100644 index 0df3749..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 16:13:36 2023 -# Process ID: 12761 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Wed May 31 16:13:37 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou deleted file mode 100644 index e8fe47e..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 16:08:55 2023 -# Process ID: 2956 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log deleted file mode 100644 index 4572683..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_2956.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Wed May 31 16:08:55 2023 -# Process ID: 2956 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Wed May 31 16:08:56 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.jou deleted file mode 100644 index c30ec12..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:49:02 2023 -# Process ID: 507565 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.log deleted file mode 100644 index 8061852..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.log +++ /dev/null @@ -1,14 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:49:02 2023 -# Process ID: 507565 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace -couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory -INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:49:02 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou deleted file mode 100644 index ad71808..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:55:04 2023 -# Process ID: 509586 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log deleted file mode 100644 index 57760b0..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_509586.backup.log +++ /dev/null @@ -1,14 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Mon May 29 21:55:04 2023 -# Process ID: 509586 -# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst -notrace -couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory -INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou deleted file mode 100644 index 7a74134..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:10 2023 -# Process ID: 5794 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log deleted file mode 100644 index a9563c6..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5794.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:10 2023 -# Process ID: 5794 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:11 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou deleted file mode 100644 index 00a9a20..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:34 2023 -# Process ID: 5876 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log deleted file mode 100644 index 1837e58..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_5876.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Tue May 30 08:48:34 2023 -# Process ID: 5876 -# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim -# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log -# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou -#----------------------------------------------------------- -source /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Tue May 30 08:48:35 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb deleted file mode 100644 index 10c3cab..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt deleted file mode 100644 index 6314351..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/Compile_Options.txt +++ /dev/null @@ -1 +0,0 @@ --wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Pipeline_behav" "xil_defaultlib.Pipeline" -log "elaborate.log" diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt deleted file mode 100644 index fdbc612..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/TempBreakPointFile.txt +++ /dev/null @@ -1 +0,0 @@ -Breakpoint File Version 1.0 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o deleted file mode 100644 index c6458fd..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c deleted file mode 100644 index 892e97c..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.c +++ /dev/null @@ -1,122 +0,0 @@ -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -typedef void (*funcp)(char *, char *); -extern void execute_76(char*, char *); -extern void execute_77(char*, char *); -extern void execute_78(char*, char *); -extern void execute_79(char*, char *); -extern void execute_80(char*, char *); -extern void execute_81(char*, char *); -extern void execute_82(char*, char *); -extern void execute_87(char*, char *); -extern void execute_51(char*, char *); -extern void execute_52(char*, char *); -extern void execute_58(char*, char *); -extern void execute_60(char*, char *); -extern void execute_62(char*, char *); -extern void execute_63(char*, char *); -extern void execute_64(char*, char *); -extern void execute_66(char*, char *); -extern void execute_68(char*, char *); -extern void execute_69(char*, char *); -extern void execute_71(char*, char *); -extern void execute_73(char*, char *); -extern void execute_75(char*, char *); -extern void execute_84(char*, char *); -extern void execute_85(char*, char *); -extern void execute_86(char*, char *); -extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); -extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[26] = {(funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_87, (funcp)execute_51, (funcp)execute_52, (funcp)execute_58, (funcp)execute_60, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_66, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 26; - -void relocate(char *dp) -{ - iki_relocate(dp, "xsim.dir/Pipeline_behav/xsim.reloc", (void **)funcTab, 26); - iki_vhdl_file_variable_register(dp + 24592); - iki_vhdl_file_variable_register(dp + 24648); - - - /*Populate the transaction function pointer field in the whole net structure */ -} - -void sensitize(char *dp) -{ - iki_sensitize(dp, "xsim.dir/Pipeline_behav/xsim.reloc"); -} - -void simulate(char *dp) -{ - iki_schedule_processes_at_time_zero(dp, "xsim.dir/Pipeline_behav/xsim.reloc"); - // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net - iki_execute_processes(); - - // Schedule resolution functions for the multiply driven Verilog nets that have strength - // Schedule transaction functions for the singly driven Verilog nets that have strength - -} -#include "iki_bridge.h" -void relocate(char *); - -void sensitize(char *); - -void simulate(char *); - -extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); -extern void implicit_HDL_SCinstatiate(); - -extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; -extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; - -int main(int argc, char **argv) -{ - iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; - iki_set_sv_type_file_path_name("xsim.dir/Pipeline_behav/xsim.svtype"); - iki_set_crvs_dump_file_path_name("xsim.dir/Pipeline_behav/xsim.crvsdump"); - void* design_handle = iki_create_design("xsim.dir/Pipeline_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); - iki_set_rc_trial_count(100); - (void) design_handle; - return iki_simulate_design(); -} diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o deleted file mode 100644 index dbb268f..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/.xsim_webtallk.info deleted file mode 100644 index 88c1217..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/.xsim_webtallk.info +++ /dev/null @@ -1,5 +0,0 @@ -1685429290 -1685429313 -6 -1 -aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html deleted file mode 100644 index 7fe932f..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html +++ /dev/null @@ -1,53 +0,0 @@ -Device Usage Statistics Report -

XSIM Usage Report


- - - - - - - - - - - - - - - - - -
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedTue May 30 08:48:33 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration2random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

- - - - - - - - -
user_environment
cpu_nameIntel(R) Core(TM) i7-8700 CPU @ 3.20GHzcpu_speed3200.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram67.000 GBtotal_processors1

- - -
vivado_usage

- - - - -
xsim
- - - -
command_line_options
command=xsim
-
- - - - - - - -
usage
iteration=0runtime=1 ussimulation_memory=118556_KBsimulation_time=0.01_sec
trace_waveform=true
-

- - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm deleted file mode 100644 index 0410530..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm +++ /dev/null @@ -1,38 +0,0 @@ -version = "1.0"; -clients = -( - { client_name = "project"; - rules = ( - { - context="software_version_and_target_device"; - xml_map="software_version_and_target_device"; - html_map="software_version_and_target_device"; - html_format="UserEnvStyle"; - }, - { - context="user_environment"; - xml_map="user_environment"; - html_map="user_environment"; - html_format="UserEnvStyle"; - } - ); - }, - - { client_name = "xsim"; - rules = ( - { - context="xsim\\command_line_options"; - xml_map="xsim\\command_line_options"; - html_map="xsim\\command_line_options"; - html_format="UnisimStatsStyle"; - }, - { - context="xsim\\usage"; - xml_map="xsim\\usage"; - html_map="xsim\\usage"; - html_format="UnisimStatsStyle"; - } - ); - } -); - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml deleted file mode 100644 index 539a45a..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml +++ /dev/null @@ -1,44 +0,0 @@ - - -
-
- - - - - - - - - - - - - - - -
-
- - - - - - -
-
-
-
-
- -
-
- - - - - -
-
-
- diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl deleted file mode 100644 index 1180ec3..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/xsim_webtalk.tcl +++ /dev/null @@ -1,32 +0,0 @@ -webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/ -webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Tue May 30 13:19:41 2023" -context "software_version_and_target_device" -webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" -webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" -webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" -webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3200.000 MHz" -context "user_environment" -webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" -webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.02_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "118560_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3468895090 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" -webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.dbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.dbg deleted file mode 100644 index 5a8e1d2..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.dbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.mem b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.mem deleted file mode 100644 index e4f7adf..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.mem and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.reloc b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.reloc deleted file mode 100644 index c10664f..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.reloc and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rlx deleted file mode 100644 index e4aabac..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rlx +++ /dev/null @@ -1,12 +0,0 @@ - -{ - crc : 6748289172475844442 , - ccp_crc : 0 , - cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Pipeline_behav xil_defaultlib.Pipeline" , - buildDate : "Jun 14 2018" , - buildTime : "20:07:38" , - linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Pipeline_behav/xsimk\" \"xsim.dir/Pipeline_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Pipeline_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" , - aggregate_nets : - [ - ] -} \ No newline at end of file diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rtti b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rtti deleted file mode 100644 index 456346c..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.rtti and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.svtype b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.svtype deleted file mode 100644 index 6dc1deb..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.svtype and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.type b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.type deleted file mode 100644 index bc603f6..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.type and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.xdbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.xdbg deleted file mode 100644 index 915fc2b..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsim.xdbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimSettings.ini b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimSettings.ini deleted file mode 100644 index 38f4bee..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimSettings.ini +++ /dev/null @@ -1,41 +0,0 @@ -[General] -ARRAY_DISPLAY_LIMIT=1024 -RADIX=hex -TIME_UNIT=ns -TRACE_LIMIT=65536 -VHDL_ENTITY_SCOPE_FILTER=true -VHDL_PACKAGE_SCOPE_FILTER=false -VHDL_BLOCK_SCOPE_FILTER=true -VHDL_PROCESS_SCOPE_FILTER=false -VHDL_PROCEDURE_SCOPE_FILTER=false -VERILOG_MODULE_SCOPE_FILTER=true -VERILOG_PACKAGE_SCOPE_FILTER=false -VERILOG_BLOCK_SCOPE_FILTER=false -VERILOG_TASK_SCOPE_FILTER=false -VERILOG_PROCESS_SCOPE_FILTER=false -INPUT_OBJECT_FILTER=true -OUTPUT_OBJECT_FILTER=true -INOUT_OBJECT_FILTER=true -INTERNAL_OBJECT_FILTER=true -CONSTANT_OBJECT_FILTER=true -VARIABLE_OBJECT_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=75 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 -SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=75 -OBJECT_VALUE_COLUMN_WIDTH=75 -OBJECT_DATA_TYPE_COLUMN_WIDTH=75 -PROCESS_NAME_COLUMN_WIDTH=75 -PROCESS_TYPE_COLUMN_WIDTH=75 -FRAME_INDEX_COLUMN_WIDTH=75 -FRAME_NAME_COLUMN_WIDTH=75 -FRAME_FILE_NAME_COLUMN_WIDTH=75 -FRAME_LINE_NUM_COLUMN_WIDTH=75 -LOCAL_NAME_COLUMN_WIDTH=75 -LOCAL_VALUE_COLUMN_WIDTH=75 -INPUT_LOCAL_FILTER=1 -OUTPUT_LOCAL_FILTER=1 -INOUT_LOCAL_FILTER=1 -INTERNAL_LOCAL_FILTER=1 -CONSTANT_LOCAL_FILTER=1 -VARIABLE_LOCAL_FILTER=1 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimcrash.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimcrash.log deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimk b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimk deleted file mode 100755 index 40040ce..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimk and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimkernel.log deleted file mode 100644 index 9a834d2..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Pipeline_behav/xsimkernel.log +++ /dev/null @@ -1,7 +0,0 @@ -Running: xsim.dir/Pipeline_behav/xsimk -simmode gui -wdb Pipeline_behav.wdb -simrunnum 0 -socket 54161 -Design successfully loaded -Design Loading Memory Usage: 32724 KB (Peak: 32776 KB) -Design Loading CPU Usage: 0 ms -Simulation completed -Simulation Memory Usage: 118560 KB (Peak: 179996 KB) -Simulation CPU Usage: 20 ms diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/Compile_Options.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/Compile_Options.txt deleted file mode 100644 index 8d475f1..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/Compile_Options.txt +++ /dev/null @@ -1 +0,0 @@ --wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Test_Alu_behav" "xil_defaultlib.Test_Alu" -log "elaborate.log" diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/TempBreakPointFile.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/TempBreakPointFile.txt deleted file mode 100644 index fdbc612..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/TempBreakPointFile.txt +++ /dev/null @@ -1 +0,0 @@ -Breakpoint File Version 1.0 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o deleted file mode 100644 index 503e594..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c deleted file mode 100644 index 7fda4d1..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c +++ /dev/null @@ -1,102 +0,0 @@ -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -typedef void (*funcp)(char *, char *); -extern void execute_53(char*, char *); -extern void execute_54(char*, char *); -extern void execute_55(char*, char *); -extern void execute_51(char*, char *); -extern void execute_52(char*, char *); -extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[6] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_51, (funcp)execute_52, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 6; - -void relocate(char *dp) -{ - iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 6); - iki_vhdl_file_variable_register(dp + 3576); - iki_vhdl_file_variable_register(dp + 3632); - - - /*Populate the transaction function pointer field in the whole net structure */ -} - -void sensitize(char *dp) -{ - iki_sensitize(dp, "xsim.dir/Test_Alu_behav/xsim.reloc"); -} - -void simulate(char *dp) -{ - iki_schedule_processes_at_time_zero(dp, "xsim.dir/Test_Alu_behav/xsim.reloc"); - // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net - iki_execute_processes(); - - // Schedule resolution functions for the multiply driven Verilog nets that have strength - // Schedule transaction functions for the singly driven Verilog nets that have strength - -} -#include "iki_bridge.h" -void relocate(char *); - -void sensitize(char *); - -void simulate(char *); - -extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); -extern void implicit_HDL_SCinstatiate(); - -extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; -extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; - -int main(int argc, char **argv) -{ - iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; - iki_set_sv_type_file_path_name("xsim.dir/Test_Alu_behav/xsim.svtype"); - iki_set_crvs_dump_file_path_name("xsim.dir/Test_Alu_behav/xsim.crvsdump"); - void* design_handle = iki_create_design("xsim.dir/Test_Alu_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); - iki_set_rc_trial_count(100); - (void) design_handle; - return iki_simulate_design(); -} diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o deleted file mode 100644 index f444053..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info deleted file mode 100644 index b587b16..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info +++ /dev/null @@ -1,5 +0,0 @@ -1685381189 -1685382347 -78 -1 -aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html deleted file mode 100644 index 6b6f6e9..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html +++ /dev/null @@ -1,53 +0,0 @@ -Device Usage Statistics Report -

XSIM Usage Report


- - - - - - - - - - - - - - - - - -
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedMon May 29 19:45:47 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration52random_id48ade6b1-45bb-42c1-b620-33b3e004d501
registration_id48ade6b1-45bb-42c1-b620-33b3e004d501route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

- - - - - - - - -
user_environment
cpu_nameIntel(R) Xeon(R) Silver 4216 CPU @ 2.10GHzcpu_speed800.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram134.000 GBtotal_processors2

- - -
vivado_usage

- - - - -
xsim
- - - -
command_line_options
command=xsim
-
- - - - - - - -
usage
iteration=0runtime=1 ussimulation_memory=122616_KBsimulation_time=0.03_sec
trace_waveform=true
-

- - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm deleted file mode 100644 index 0410530..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm +++ /dev/null @@ -1,38 +0,0 @@ -version = "1.0"; -clients = -( - { client_name = "project"; - rules = ( - { - context="software_version_and_target_device"; - xml_map="software_version_and_target_device"; - html_map="software_version_and_target_device"; - html_format="UserEnvStyle"; - }, - { - context="user_environment"; - xml_map="user_environment"; - html_map="user_environment"; - html_format="UserEnvStyle"; - } - ); - }, - - { client_name = "xsim"; - rules = ( - { - context="xsim\\command_line_options"; - xml_map="xsim\\command_line_options"; - html_map="xsim\\command_line_options"; - html_format="UnisimStatsStyle"; - }, - { - context="xsim\\usage"; - xml_map="xsim\\usage"; - html_map="xsim\\usage"; - html_format="UnisimStatsStyle"; - } - ); - } -); - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml deleted file mode 100644 index 8797eef..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml +++ /dev/null @@ -1,44 +0,0 @@ - - -
-
- - - - - - - - - - - - - - - -
-
- - - - - - -
-
-
-
-
- -
-
- - - - - -
-
-
- diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl deleted file mode 100644 index b6e0518..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl +++ /dev/null @@ -1,32 +0,0 @@ -webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/ -webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Mon May 29 23:52:36 2023" -context "software_version_and_target_device" -webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" -webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" -webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "77" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" -webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "user_environment" -webtalk_add_data -client project -key total_processors -value "2" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment" -webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122616_KB" -context "xsim\\usage" -webtalk_transmit -clientid 1575937485 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" -webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg deleted file mode 100644 index 21c6448..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem deleted file mode 100644 index 4c83522..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc deleted file mode 100644 index 328b55c..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx deleted file mode 100644 index 90b86b0..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx +++ /dev/null @@ -1,12 +0,0 @@ - -{ - crc : 3751694400990100050 , - ccp_crc : 0 , - cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" , - buildDate : "Jun 14 2018" , - buildTime : "20:07:38" , - linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Test_Alu_behav/xsimk\" \"xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" , - aggregate_nets : - [ - ] -} \ No newline at end of file diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti deleted file mode 100644 index 11bd8cf..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.svtype b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.svtype deleted file mode 100644 index 6dc1deb..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.svtype and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type deleted file mode 100644 index 20d26bf..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg deleted file mode 100644 index 8e1d872..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimSettings.ini b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimSettings.ini deleted file mode 100644 index 38f4bee..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimSettings.ini +++ /dev/null @@ -1,41 +0,0 @@ -[General] -ARRAY_DISPLAY_LIMIT=1024 -RADIX=hex -TIME_UNIT=ns -TRACE_LIMIT=65536 -VHDL_ENTITY_SCOPE_FILTER=true -VHDL_PACKAGE_SCOPE_FILTER=false -VHDL_BLOCK_SCOPE_FILTER=true -VHDL_PROCESS_SCOPE_FILTER=false -VHDL_PROCEDURE_SCOPE_FILTER=false -VERILOG_MODULE_SCOPE_FILTER=true -VERILOG_PACKAGE_SCOPE_FILTER=false -VERILOG_BLOCK_SCOPE_FILTER=false -VERILOG_TASK_SCOPE_FILTER=false -VERILOG_PROCESS_SCOPE_FILTER=false -INPUT_OBJECT_FILTER=true -OUTPUT_OBJECT_FILTER=true -INOUT_OBJECT_FILTER=true -INTERNAL_OBJECT_FILTER=true -CONSTANT_OBJECT_FILTER=true -VARIABLE_OBJECT_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=75 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 -SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=75 -OBJECT_VALUE_COLUMN_WIDTH=75 -OBJECT_DATA_TYPE_COLUMN_WIDTH=75 -PROCESS_NAME_COLUMN_WIDTH=75 -PROCESS_TYPE_COLUMN_WIDTH=75 -FRAME_INDEX_COLUMN_WIDTH=75 -FRAME_NAME_COLUMN_WIDTH=75 -FRAME_FILE_NAME_COLUMN_WIDTH=75 -FRAME_LINE_NUM_COLUMN_WIDTH=75 -LOCAL_NAME_COLUMN_WIDTH=75 -LOCAL_VALUE_COLUMN_WIDTH=75 -INPUT_LOCAL_FILTER=1 -OUTPUT_LOCAL_FILTER=1 -INOUT_LOCAL_FILTER=1 -INTERNAL_LOCAL_FILTER=1 -CONSTANT_LOCAL_FILTER=1 -VARIABLE_LOCAL_FILTER=1 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimcrash.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimcrash.log deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk deleted file mode 100755 index 1cfb693..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log deleted file mode 100644 index 125067c..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log +++ /dev/null @@ -1,7 +0,0 @@ -Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 49525 -Design successfully loaded -Design Loading Memory Usage: 32680 KB (Peak: 32740 KB) -Design Loading CPU Usage: 20 ms -Simulation completed -Simulation Memory Usage: 122616 KB (Peak: 179952 KB) -Simulation CPU Usage: 30 ms diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/Compile_Options.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/Compile_Options.txt deleted file mode 100644 index 14d4555..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/Compile_Options.txt +++ /dev/null @@ -1 +0,0 @@ --wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Test_total_behav" "xil_defaultlib.Test_total" -log "elaborate.log" diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/TempBreakPointFile.txt b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/TempBreakPointFile.txt deleted file mode 100644 index fdbc612..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/TempBreakPointFile.txt +++ /dev/null @@ -1 +0,0 @@ -Breakpoint File Version 1.0 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o deleted file mode 100644 index a697b16..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c deleted file mode 100644 index 903aeed..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.c +++ /dev/null @@ -1,127 +0,0 @@ -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - - -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -typedef void (*funcp)(char *, char *); -extern void execute_94(char*, char *); -extern void execute_81(char*, char *); -extern void execute_82(char*, char *); -extern void execute_83(char*, char *); -extern void execute_84(char*, char *); -extern void execute_85(char*, char *); -extern void execute_86(char*, char *); -extern void execute_87(char*, char *); -extern void execute_90(char*, char *); -extern void execute_91(char*, char *); -extern void execute_92(char*, char *); -extern void execute_93(char*, char *); -extern void execute_53(char*, char *); -extern void execute_54(char*, char *); -extern void execute_60(char*, char *); -extern void execute_62(char*, char *); -extern void execute_64(char*, char *); -extern void execute_65(char*, char *); -extern void execute_66(char*, char *); -extern void execute_67(char*, char *); -extern void execute_69(char*, char *); -extern void execute_71(char*, char *); -extern void execute_72(char*, char *); -extern void execute_73(char*, char *); -extern void execute_75(char*, char *); -extern void execute_77(char*, char *); -extern void execute_78(char*, char *); -extern void execute_80(char*, char *); -extern void execute_89(char*, char *); -extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); -extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[31] = {(funcp)execute_94, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_53, (funcp)execute_54, (funcp)execute_60, (funcp)execute_62, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_69, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_75, (funcp)execute_77, (funcp)execute_78, (funcp)execute_80, (funcp)execute_89, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 31; - -void relocate(char *dp) -{ - iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 31); - iki_vhdl_file_variable_register(dp + 24832); - iki_vhdl_file_variable_register(dp + 24888); - - - /*Populate the transaction function pointer field in the whole net structure */ -} - -void sensitize(char *dp) -{ - iki_sensitize(dp, "xsim.dir/Test_total_behav/xsim.reloc"); -} - -void simulate(char *dp) -{ - iki_schedule_processes_at_time_zero(dp, "xsim.dir/Test_total_behav/xsim.reloc"); - // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net - iki_execute_processes(); - - // Schedule resolution functions for the multiply driven Verilog nets that have strength - // Schedule transaction functions for the singly driven Verilog nets that have strength - -} -#include "iki_bridge.h" -void relocate(char *); - -void sensitize(char *); - -void simulate(char *); - -extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); -extern void implicit_HDL_SCinstatiate(); - -extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; -extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; - -int main(int argc, char **argv) -{ - iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; - iki_set_sv_type_file_path_name("xsim.dir/Test_total_behav/xsim.svtype"); - iki_set_crvs_dump_file_path_name("xsim.dir/Test_total_behav/xsim.crvsdump"); - void* design_handle = iki_create_design("xsim.dir/Test_total_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); - iki_set_rc_trial_count(100); - (void) design_handle; - return iki_simulate_design(); -} diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o deleted file mode 100644 index 9aa9332..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info deleted file mode 100644 index 99c4d45..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/.xsim_webtallk.info +++ /dev/null @@ -1,5 +0,0 @@ -1685542134 -1685542416 -171 -1 -aef36ef3a0d94dac9e6058b656907afd diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html deleted file mode 100644 index 0d26e76..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html +++ /dev/null @@ -1,53 +0,0 @@ -Device Usage Statistics Report -

XSIM Usage Report


- - - - - - - - - - - - - - - - - -
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedWed May 31 16:13:36 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration153random_id6ef722b6-53ec-42dc-bc5c-9d79054a9923
registration_id6ef722b6-53ec-42dc-bc5c-9d79054a9923route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

- - - - - - - - -
user_environment
cpu_nameIntel(R) Core(TM) i5-9500 CPU @ 3.00GHzcpu_speed3000.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram16.000 GBtotal_processors1

- - -
vivado_usage

- - - - -
xsim
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command_line_options
command=xsim
-
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usage
iteration=4runtime=100 ussimulation_memory=122672_KBsimulation_time=0.02_sec
trace_waveform=true
-

- - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm deleted file mode 100644 index 0410530..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm +++ /dev/null @@ -1,38 +0,0 @@ -version = "1.0"; -clients = -( - { client_name = "project"; - rules = ( - { - context="software_version_and_target_device"; - xml_map="software_version_and_target_device"; - html_map="software_version_and_target_device"; - html_format="UserEnvStyle"; - }, - { - context="user_environment"; - xml_map="user_environment"; - html_map="user_environment"; - html_format="UserEnvStyle"; - } - ); - }, - - { client_name = "xsim"; - rules = ( - { - context="xsim\\command_line_options"; - xml_map="xsim\\command_line_options"; - html_map="xsim\\command_line_options"; - html_format="UnisimStatsStyle"; - }, - { - context="xsim\\usage"; - xml_map="xsim\\usage"; - html_map="xsim\\usage"; - html_format="UnisimStatsStyle"; - } - ); - } -); - diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml deleted file mode 100644 index 76e4ff4..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml +++ /dev/null @@ -1,44 +0,0 @@ - - -
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- diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl deleted file mode 100644 index cec9ee2..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl +++ /dev/null @@ -1,32 +0,0 @@ -webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/ -webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Wed May 31 18:34:59 2023" -context "software_version_and_target_device" -webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" -webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" -webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "170" -context "software_version_and_target_device" -webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" -webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3000.000 MHz" -context "user_environment" -webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" -webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "100 us" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "122672_KB" -context "xsim\\usage" -webtalk_transmit -clientid 1544091380 -regid "" -xml /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" -webtalk_terminate diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg deleted file mode 100644 index 14752d5..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.dbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem deleted file mode 100644 index 695ee5d..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.mem and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc deleted file mode 100644 index aefc4c8..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.reloc and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx deleted file mode 100644 index d1425c9..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rlx +++ /dev/null @@ -1,12 +0,0 @@ - -{ - crc : 2677193059207045368 , - ccp_crc : 0 , - cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" , - buildDate : "Jun 14 2018" , - buildTime : "20:07:38" , - linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Test_total_behav/xsimk\" \"xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" , - aggregate_nets : - [ - ] -} \ No newline at end of file diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti deleted file mode 100644 index 4574d4f..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.rtti and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.svtype b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.svtype deleted file mode 100644 index 6dc1deb..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.svtype and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type deleted file mode 100644 index b22217f..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.type and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg deleted file mode 100644 index dc21d13..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsim.xdbg and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimSettings.ini b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimSettings.ini deleted file mode 100644 index 1d585e2..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimSettings.ini +++ /dev/null @@ -1,41 +0,0 @@ -[General] -ARRAY_DISPLAY_LIMIT=1024 -RADIX=hex -TIME_UNIT=ns -TRACE_LIMIT=65536 -VHDL_ENTITY_SCOPE_FILTER=true -VHDL_PACKAGE_SCOPE_FILTER=false -VHDL_BLOCK_SCOPE_FILTER=true -VHDL_PROCESS_SCOPE_FILTER=false -VHDL_PROCEDURE_SCOPE_FILTER=false -VERILOG_MODULE_SCOPE_FILTER=true -VERILOG_PACKAGE_SCOPE_FILTER=false -VERILOG_BLOCK_SCOPE_FILTER=false -VERILOG_TASK_SCOPE_FILTER=false -VERILOG_PROCESS_SCOPE_FILTER=false -INPUT_OBJECT_FILTER=true -OUTPUT_OBJECT_FILTER=true -INOUT_OBJECT_FILTER=true -INTERNAL_OBJECT_FILTER=true -CONSTANT_OBJECT_FILTER=true -VARIABLE_OBJECT_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=169 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 -SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=75 -OBJECT_VALUE_COLUMN_WIDTH=75 -OBJECT_DATA_TYPE_COLUMN_WIDTH=75 -PROCESS_NAME_COLUMN_WIDTH=75 -PROCESS_TYPE_COLUMN_WIDTH=75 -FRAME_INDEX_COLUMN_WIDTH=75 -FRAME_NAME_COLUMN_WIDTH=75 -FRAME_FILE_NAME_COLUMN_WIDTH=75 -FRAME_LINE_NUM_COLUMN_WIDTH=75 -LOCAL_NAME_COLUMN_WIDTH=75 -LOCAL_VALUE_COLUMN_WIDTH=75 -INPUT_LOCAL_FILTER=1 -OUTPUT_LOCAL_FILTER=1 -INOUT_LOCAL_FILTER=1 -INTERNAL_LOCAL_FILTER=1 -CONSTANT_LOCAL_FILTER=1 -VARIABLE_LOCAL_FILTER=1 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimcrash.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimcrash.log deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk deleted file mode 100755 index 3c185ca..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log deleted file mode 100644 index 15d0cbf..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimkernel.log +++ /dev/null @@ -1,7 +0,0 @@ -Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 53223 -Design successfully loaded -Design Loading Memory Usage: 32736 KB (Peak: 32788 KB) -Design Loading CPU Usage: 30 ms -Simulation completed -Simulation Memory Usage: 122672 KB (Peak: 180008 KB) -Simulation CPU Usage: 30 ms diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb deleted file mode 100644 index 8327d80..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/aleacontroler.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb deleted file mode 100644 index a86cd06..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb deleted file mode 100644 index 87f0799..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb deleted file mode 100644 index bcda625..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb deleted file mode 100644 index a7dadb1..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb deleted file mode 100644 index 822ff0a..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb deleted file mode 100644 index 16492cc..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb deleted file mode 100644 index 7a055fc..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb deleted file mode 100644 index 586ab08..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb deleted file mode 100644 index ed7918a..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb deleted file mode 100644 index 985dcff..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb deleted file mode 100644 index 027758c..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb deleted file mode 100644 index 7dc3221..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_total.vdb and /dev/null differ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx deleted file mode 100644 index 0f13ad9..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ /dev/null @@ -1,16 +0,0 @@ -0.6 -2018.2 -Jun 14 2018 -20:07:38 -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685465261,vhdl,,,,test_total,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685542123,vhdl,,,,alu,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd,1685543740,vhdl,,,,aleacontroler,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685436168,vhdl,,,,ip,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685456575,vhdl,,,,instructionmemory,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685445542,vhdl,,,,datamemory,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685545934,vhdl,,,,pipeline,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685467153,vhdl,,,,registers,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,, -/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,, diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini deleted file mode 100644 index e8199b2..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini +++ /dev/null @@ -1 +0,0 @@ -xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log deleted file mode 100644 index b6abecb..0000000 --- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log +++ /dev/null @@ -1,2 +0,0 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib -INFO: [VRFC 10-307] analyzing entity Pipeline diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb deleted file mode 100644 index c765b72..0000000 Binary files a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb and /dev/null differ diff --git a/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc b/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc deleted file mode 100644 index 6c1e4bf..0000000 --- a/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc +++ /dev/null @@ -1 +0,0 @@ -create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk] diff --git a/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc b/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc deleted file mode 100644 index c9f590c..0000000 --- a/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc +++ /dev/null @@ -1,26 +0,0 @@ -set_property PACKAGE_PIN R2 [get_ports CLK] - set_property IOSTANDARD LVCMOS33 [get_ports CLK] -#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK] - -#set_property -dicset_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports CLK] -#set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports CLK] -#create_clock -period 10.000 -name -sysclk_pin -waveform {0.000 5.000} [get_ports CLK] - -set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets {Stage2/Jump_Flag}] - -set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[0]}] -set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[1]}] -set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {reg_addr[2]}] -set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {reg_addr[3]}] - -set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {reg_val[0]}] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {reg_val[1]}] -set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {reg_val[2]}] -set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {reg_val[3]}] -set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {reg_val[4]}] -set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {reg_val[5]}] -set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {reg_val[6]}] -set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {reg_val[7]}] - -set_property SEVERITY {Warning} [get_drc_checks NSTD-1] -set_property SEVERITY {Warning} [get_drc_checks UCIO-1] diff --git a/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc b/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc deleted file mode 100644 index da05bd1..0000000 --- a/VHDL/ALU/ALU.srcs/constrs_1/new/uP.xdc +++ /dev/null @@ -1 +0,0 @@ -#create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk] diff --git a/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd b/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd deleted file mode 100644 index f543e0e..0000000 --- a/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd +++ /dev/null @@ -1,145 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12.05.2023 17:40:52 --- Design Name: --- Module Name: Test_Alu - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Test_Alu is --- Port ( ); -end Test_Alu; - -architecture Behavioral of Test_Alu is - - - component ALU - Port ( A : in STD_LOGIC_VECTOR (7 downto 0); - B : in STD_LOGIC_VECTOR (7 downto 0); - Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); -- 000 + / 001 - / 010 * / 100 Div - S : out STD_LOGIC_VECTOR (7 downto 0); - N : out STD_LOGIC; - O : out STD_LOGIC; - Z : out STD_LOGIC; - C : out STD_LOGIC); - end component; - - -- inputs - signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal local_Ctrl_Alu : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - - --outputs - signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal local_N : STD_LOGIC := '0'; - signal local_O : STD_LOGIC := '0'; - signal local_Z : STD_LOGIC := '0'; - signal local_C : STD_LOGIC := '0'; - - -- constant Clock_period : time := 10ns; - -begin - --- instantiate -instance : ALU PORT MAP ( - A => local_A, - B => local_B, - Ctrl_Alu => local_Ctrl_Alu, - S => local_S, - N => local_N, - O => local_O, - Z => local_Z, - C => local_C -); - -local_Ctrl_Alu <= x"01", -- ADD - x"02" after 40 ns, -- MUL - x"03" after 60 ns, -- SUB - x"04" after 90 ns, -- DIV - x"09" after 120 ns, -- INF - x"0A" after 140 ns, -- SUP - x"0B" after 160 ns, -- EQ - x"0C" after 180 ns, -- NOT - x"0D" after 210 ns, -- XOR - x"0E" after 240 ns, -- OR - x"0F" after 270 ns; -- XOR - -local_A <= x"00", - x"00" after 10 ns, - x"0A" after 20 ns, - x"96" after 30 ns, - x"1D" after 40 ns, - x"0A" after 50 ns, - x"0B" after 60 ns, - x"0F" after 70 ns, - x"19" after 80 ns, - x"12" after 90 ns, - x"18" after 100 ns, - x"19" after 110 ns, - x"10" after 120 ns, - x"20" after 130 ns, - x"10" after 150 ns, - x"0A" after 160 ns, - x"0B" after 170 ns, - x"01" after 180 ns, - x"25" after 190 ns, - x"00" after 200 ns, - x"0A" after 210 ns, - x"00" after 230 ns, - x"0A" after 240 ns, - x"00" after 260 ns, - x"0A" after 270 ns, - x"00" after 290 ns; - -local_B <= x"00", - x"00" after 10 ns, - x"82" after 20 ns, - x"A0" after 30 ns, - x"09" after 40 ns, - x"04" after 50 ns, - x"0B" after 60 ns, - x"12" after 70 ns, - x"0B" after 80 ns, - x"00" after 90 ns, - x"06" after 100 ns, - x"07" after 110 ns, - x"20" after 120 ns, - x"10" after 130 ns, - x"20" after 150 ns, - x"0A" after 160 ns, - x"02" after 170 ns, - x"00" after 190 ns, - x"0B" after 210 ns, - x"00" after 220 ns, - x"0B" after 240 ns, - x"00" after 250 ns, - x"0B" after 270 ns, - x"00" after 280 ns; - - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd deleted file mode 100644 index 407233b..0000000 --- a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd +++ /dev/null @@ -1,65 +0,0 @@ - ---------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12.05.2023 17:40:52 --- Design Name: --- Module Name: Test_Alu - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Test_total is --- Port ( ); -end Test_total; - -architecture Behavioral of test_total is - - - component Pipeline - Port (Clk : in STD_LOGIC; - reg_addr : in STD_LOGIC_VECTOR(3 downto 0); - reg_val : out STD_LOGIC_VECTOR(7 downto 0)); - end component; - constant clock_period : time := 10 ns; - - signal clock : Std_logic := '0'; - signal a : STD_LOGIC_VECTOR(7 downto 0); - -begin - -- instantiate - Pl : Pipeline PORT MAP ( - Clk => clock, - reg_addr => x"0", - reg_val => a - ); - - Clock_process : process - begin - clock <= not(clock); - wait for 100ns; - end process; - -end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd deleted file mode 100644 index 8e96a44..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd +++ /dev/null @@ -1,92 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12.05.2023 16:14:24 --- Design Name: --- Module Name: ALU - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; --- use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ALU is - Port ( A : in STD_LOGIC_VECTOR (7 downto 0); - B : in STD_LOGIC_VECTOR (7 downto 0); - Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); - S : out STD_LOGIC_VECTOR (7 downto 0); - N : out STD_LOGIC; - O : out STD_LOGIC; - Z : out STD_LOGIC; - C : out STD_LOGIC; - JumpFlagOut : out STD_LOGIC; -- 0 false 1 true - JumpFlagIn : in STD_LOGIC - ); -end ALU; - --- Instruction code - -- ADD x"01" - -- MUL x"02" - -- SUB x"03" - -- DIV x"04" - -- INF x"09" - -- SUP x"0A" - -- EQ x"0B" - -- NOT x"0C" - -- AND x"0D" - -- OR x"0E" - -- XOR x"0F" - - -architecture Behavioral of ALU is - signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000"; - signal flag : STD_LOGIC := '0'; -begin - process(A, B, Ctrl_Alu) - begin - N <= '0'; - O <= '0'; - Z <= '0'; - C <= '0'; - flag <= JumpFlagIn; - case Ctrl_Alu is - when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD - when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL - when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB - when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV - when x"09" => if A < B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0A" => if A > B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0B" => if A = B then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0C" => if A > 0 then res <= x"0001"; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; flag <= '1'; else res <= x"0000"; flag <= '0'; end if; - when others => res <= x"0000"; - end case; - end process; - JumpFlagOut <= flag; - S <= res(7 downto 0); -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd deleted file mode 100644 index c6e728e..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd +++ /dev/null @@ -1,77 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.all; - --- Instruction coEX - -- ADD 00000001 - -- MUL 00000010 - -- SUB 00000011 - -- DIV 00000100 - -- COP 00000101 - -- AFC 00000110 - -- LOAD 00000111 - -- STORE 00001000 - -- INF 00001001 - -- SUP 00001010 - -- EQ 00001011 - -- NOT 00001100 - -- AND 00001101 - -- OR 00001110 - -- NOP 11111111 - - - --- when the just entered instruction causes a problem with an instruction already in the EX or Mem stage (a write-Back stage would not cause any harm) we: - -- we freeze IP on the current instruction - -- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish - -entity AleaControler is - Port ( - -- get the current op and variables from the 3 pipelines stages that can interract - Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0); - A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0); - B_DI : in STD_LOGIC_VECTOR (7 downto 0); - C_DI : in STD_LOGIC_VECTOR (7 downto 0); - - CNTRL : out STD_LOGIC); -end AleaControler; - - -architecture Behavioral of AleaControler is - signal alea_DI_EX, alea_DI_MEM: STD_LOGIC; - signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC; -begin - CNTRL <= -- either a problem between the 1st and 2nd or 1st and 3rd - '1' when - -- read after write : Op1 other than STORE/NOP/JMP/JMF, op2 other than AFC/NOP/JMP/JMF, R(write) = R(read) - ( - -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_EX /= x"08" and Op_EX /= x"ff" and Op_EX /= x"0f" and Op_EX /= x"10")) and - - -- check Registers are the same - ((A_Ex = B_DI) or (A_EX = C_DI)) - ) or - - -- read after write : Op1 other than STORE/NOP/JMP/JMF, op3 other than AFC/NOP/JMP/JMF, R(write) = R(read) - ( - -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_Mem /= x"08" and Op_Mem /= x"ff" and Op_Mem /= x"0f" and Op_Mem /= x"10")) and - - -- check Registers are the same - ((A_Mem = B_DI) or (A_Mem = C_DI)) - ) or - - -- read after write : Op1 other than STORE/NOP/JMP/JMF, op4 other than AFC/NOP/JMP/JMF, R(write) = R(read) - ( - -- check Op1 & Op2 - ((OP_DI /= x"06" and OP_DI /= x"ff" and OP_Di /= x"0F" and OP_DI /= x"10") and (Op_Re /= x"08" and Op_Re /= x"ff" and Op_Re /= x"0f" and Op_Re /= x"10")) and - - -- check Registers are the same - ((A_Re = B_DI) or (A_Re = C_DI)) - ) - or - ( - Op_EX = x"10" -- or Op_Mem = x"10" or Op_Re = x"10" - ) - else '0'; -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd deleted file mode 100644 index d4cade3..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd +++ /dev/null @@ -1,61 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21.03.2023 15:57:28 --- Design Name: --- Module Name: compteur_8bits - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity IP is - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; -- rst when 1 - LOAD : in STD_LOGIC; - EN : in STD_LOGIC; -- enable when 0 - Din : in STD_LOGIC_VECTOR (7 downto 0); - Dout : out STD_LOGIC_VECTOR (7 downto 0)); -end IP; - -architecture Behavioral of IP is - signal aux: STD_LOGIC_VECTOR (7 downto 0) := x"00"; -begin - process - begin - wait until rising_edge(CLK); - - if (RST = '1') then - aux <= x"00"; - elsif (LOAD = '1') then - aux <= Din; - elsif (EN = '0') then - aux <= aux + x"01"; - end if; - end process; - Dout <= aux; -end Behavioral; \ No newline at end of file diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd deleted file mode 100644 index 7f4f048..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd +++ /dev/null @@ -1,53 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 13:55:29 --- Design Name: --- Module Name: InstructionMemory - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity InstructionMemory is - Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); -end InstructionMemory; - -architecture Behavioral of InstructionMemory is - type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); --- signal Mem : Mem_array := ((x"06000200"),(x"08020000"),(x"07000200"),(x"08000000"),(x"06000200"),(x"08020000"),(x"07000000"),(x"07010200"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08010000"),others => (x"ff000000")); --- signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000600"),(x"08030000"),(x"07000000"),(x"07010300"),(x"02000001"),(x"08040000"),(x"07000400"),(x"08010000"),(x"06000200"),(x"08030000"),(x"07000100"),(x"07010300"),(x"04000001"),(x"08040000"),(x"07000400"),(x"07010000"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); --- test JMP signal Mem : Mem_array := ((x"06000200"),(x"08030000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08030000"),(x"07000300"),(x"08010000"),(x"0F0D0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08020000"),(x"06000900"),(x"08030000"),(x"07000300"),(x"08020000"),others => (x"ff000000")); --- test JMF signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"100F0000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); --- test if else signal Mem : Mem_array := ((x"06000200"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10021000"),(x"06000800"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F140000"),(x"06000C00"),(x"08020000"),(x"07000200"),(x"08000000"),(x"FF000000"),others => (x"ff000000")); --- test boucle while -signal Mem : Mem_array := ((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000500"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"10001B00"),(x"06001400"),(x"08030000"),(x"07000000"),(x"07010300"),(x"09020001"),(x"08040200"),(x"10041B00"),(x"06000200"),(x"08010000"),(x"07000000"),(x"07010100"),(x"01000001"),(x"08030000"),(x"07000300"),(x"08000000"),(x"0F0B0000"),(x"FF000000"),others => (x"ff000000")); --- signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000")); -begin - Inst_out <= Mem(to_integer(unsigned(Addr))); -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd deleted file mode 100644 index 7ae32ec..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd +++ /dev/null @@ -1,60 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 13:37:41 --- Design Name: --- Module Name: DataMemory - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity DataMemory is - Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); - Data_in : in STD_LOGIC_VECTOR (7 downto 0); - Rw : in STD_LOGIC; - Rst : in STD_LOGIC; - Clk : in STD_LOGIC; - Data_out : out STD_LOGIC_VECTOR (7 downto 0)); -end DataMemory; - -architecture Behavioral of DataMemory is - type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); - signal Mem : Mem_array := (others => x"00"); -begin - - process - begin - wait until clk'event and clk = '1'; - if Rst = '1' then -- Reset - mem <= (others => x"00"); - else if Rw = '0' then --writing - Mem(to_integer(unsigned(Addr))) <= Data_in; - end if; - end if; - end process; - Data_out <= Mem(to_integer(unsigned(Addr))); --reading -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd deleted file mode 100644 index ed83102..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ /dev/null @@ -1,364 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 14:29:58 --- Design Name: --- Module Name: Pipeline - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Pipeline is - Port (Clk : in STD_LOGIC := '0'; - reg_addr : in STD_LOGIC_VECTOR(3 downto 0) := "0000"; - reg_val : out STD_LOGIC_VECTOR(7 downto 0)); -end Pipeline; - -architecture Behavioral of Pipeline is - - component IP is - port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; -- rst when 1 - LOAD : in STD_LOGIC; - EN : in STD_LOGIC; -- enable when 0 - Din : in STD_LOGIC_VECTOR (7 downto 0); - Dout : out STD_LOGIC_VECTOR (7 downto 0)); - end component; - - signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal rst : STD_LOGIC := '0'; - - component InstructionMemory - Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); - end component; - - signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '1'); - - component Stage_Li_Di - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_C : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0); - Out_C : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - - component Registers - Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); - Addr_B : in STD_LOGIC_VECTOR (3 downto 0); - Addr_W : in STD_LOGIC_VECTOR (3 downto 0); - Addr_C : in STD_LOGIC_VECTOR (3 downto 0); -- display on FPGA - W : in STD_LOGIC; - Data : in STD_LOGIC_VECTOR (7 downto 0); - Rst : in STD_LOGIC; - Clk : in STD_LOGIC; - QA : out STD_LOGIC_VECTOR (7 downto 0); - QB : out STD_LOGIC_VECTOR (7 downto 0); - QC : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - - signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - - component Stage_Di_Ex - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_C : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0); - Out_C : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - - signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - - component ALU - Port ( A : in STD_LOGIC_VECTOR (7 downto 0); - B : in STD_LOGIC_VECTOR (7 downto 0); - Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); - S : out STD_LOGIC_VECTOR (7 downto 0); - N : out STD_LOGIC; - O : out STD_LOGIC; - Z : out STD_LOGIC; - C : out STD_LOGIC; - JumpFlagOut : out STD_LOGIC; -- 0 false 1 true - JumpFlagIn : in STD_LOGIC - ); - end component; - - signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag, Jump_Flag : STD_LOGIC; - - component Stage_Ex_Mem - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - - signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal Mem_RW : STD_LOGIC; - signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - - component DataMemory - Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); - Data_in : in STD_LOGIC_VECTOR (7 downto 0); - Rw : in STD_LOGIC; - Rst : in STD_LOGIC; - Clk : in STD_LOGIC; - Data_out : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - - component Stage_Mem_Re - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0) - ); - end component; - component AleaControler is - Port ( Op_DI, Op_EX, Op_Mem, Op_Re : in STD_LOGIC_VECTOR (7 downto 0); - A_EX, A_Mem, A_Re : in STD_LOGIC_VECTOR (7 downto 0); - B_DI : in STD_LOGIC_VECTOR (7 downto 0); - C_DI : in STD_LOGIC_VECTOR (7 downto 0); - CNTRL : out STD_LOGIC - ); - end component; - - signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal Re_W : STD_LOGIC; - - -- to control jumping and where to jump - signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); - signal jump : STD_LOGIC := '0'; - - signal nop_Cntrl : STD_LOGIC; - signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); - signal Di_Op_Final : STD_LOGIC_VECTOR (7 downto 0) := (others => '1'); -begin - --- instructionPointer -inst_point : IP port map ( - CLK=> clk, - Dout=> IP_out, - Din => addr_to_jump, - RST => rst, - EN => nop_Cntrl, - LOAD => jump); - - --- instructionMemory -MemInst : InstructionMemory PORT MAP ( - Addr => IP_out, - Clk => Clk, - Inst_out => Li); - --- Stage_Li_Di -Stage1 : Stage_Li_Di PORT MAP ( - In_A => Li(23 downto 16), - In_B => Li(15 downto 8), - In_C => Li(7 downto 0), - In_Op => OP_LI_DI, - Clk => Clk, - Out_A => Di_A, - Out_B => Di_B, - Out_Op => Di_Op, - Out_C => Di_C); - --- Registers -StageRegisters : Registers PORT MAP ( - Addr_A => Di_B(3 downto 0), -- because the registers are on 4 bits - Addr_B => Di_C(3 downto 0), - Addr_W => Re_A(3 downto 0), - Addr_C => reg_addr, - W => Re_W, - Data => Re_B, - Rst => Rst, - Clk => Clk, - QA => Di_RegB, - QB => Di_C2, - QC => reg_val); - --- Stage DI/EX -Stage2 : Stage_Di_Ex PORT MAP ( - In_A => Di_A, - In_B => Di_FinalB, - In_C => Di_C2, - In_Op => Di_Op_Final, - Clk => Clk, - Out_A => Ex_A, - Out_B => Ex_B, - Out_Op => Ex_Op, - Out_C => Ex_C); - --- ALU -Ual : ALU PORT MAP ( - A => Ex_B, - B => Ex_C, - Ctrl_Alu => Ex_Ctrl_ALu, - S => Ex_Res_Alu, - N => S_NFlag, - O => S_OFlag, - Z => S_ZFlag, - C => S_CFlag, - JumpFlagOut => Jump_Flag, - JumpFlagIn => Jump_Flag); - --- Stage Ex/Mem -Stage3 : Stage_Ex_Mem PORT MAP ( - In_A => Ex_A, - In_B => Ex_FinalB, - In_Op => Ex_Op, - Clk => Clk, - Out_A => Mem_A, - Out_B => Mem_B, - Out_Op => Mem_Op); - --- DataMemory -DataMem : DataMemory PORT MAP ( - Addr => Mem_Addr, - Data_in => Mem_B, - Rw => Mem_RW, - Rst => Rst, - Clk => Clk, - Data_out => Mem_Data_Out); - --- Stage Mem/RE -Stage4 : Stage_Mem_Re PORT MAP ( - In_A => Mem_A, - In_B => Mem_FinalB, - In_Op => Mem_Op, - Clk => Clk, - Out_A => Re_A, - Out_B => Re_B, - Out_Op => Re_Op); - --- Instruction code - -- ADD x"01" - -- MUL x"02" - -- SUB x"03" - -- DIV x"04" - -- COP x"05" - -- AFC x"06" - -- LOAD x"07" - -- STORE x"08" - -- INF x"09" - -- SUP x"0A" - -- EQ x"0B" - -- NOT x"0C" - -- AND x"0D" - -- OR x"0E" - -- JMP x"0F" - -- JMF x"10" - -- CAL x"11" - -- RET x"12" - -- PRI x"13" - -- NOP x"FF" - --- Mux post registers -Di_FinalB <= Di_B when - Di_OP = x"06" or -- AFC - Di_OP = x"07" -- LOAD - else Di_RegB; - --- Mux post ALU -Ex_FinalB <= Ex_B when - Ex_Op = x"06" --AFC - or Ex_Op = x"05" --COP - or Ex_Op = x"07" --LOAD - or Ex_Op = x"08" --STORE - else Ex_Res_Alu; - --- LC pre ALU -Ex_Ctrl_ALu <= x"00" when Ex_Op = x"05" or Ex_Op = x"06" or Ex_Op = x"07" or Ex_Op = x"08" --(not using ALU) - else Ex_Op; - --- Mux post data memory -Mem_FinalB <= Mem_B when - Mem_Op = x"06" --AFC - or Mem_Op = x"05" --COP - or Mem_Op = x"01" --ADD - or Mem_Op = x"03" -- SUB - or Mem_Op = x"02" -- MUL - or Mem_Op = x"04" -- DIV - else Mem_Data_out ; --LOAD & STORE - --- Mux pre data memory -Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD - else Mem_A; --STORE - --- LC pre data memory -Mem_RW <= '0' when Mem_Op = x"08" --STORE - else '1'; --STORE - --- LC post Pip_Mem_Re -Re_W <= '0' when Re_Op = x"08" or Re_Op = x"ff" --STORE - else '1'; - -CU : AleaControler port map ( - Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op, Op_Re => Mem_Op, - A_EX => Di_A, A_Mem => Ex_A, A_Re => Mem_A, - B_DI => Li(15 downto 8), - C_DI => Li(7 downto 0), - CNTRL => nop_Cntrl); - - -- in case of alea : replace li(31 downto 24) by NOP - OP_LI_DI <= X"ff" when (nop_Cntrl='1' or - (Di_Op = x"10" and Jump_Flag = '1')) -- to prevent JMF - else Li(31 downto 24); - --- jump JMP - addr_to_jump <= DI_A when (DI_OP = x"0F") -- JMP - else Di_B when (Di_Op = x"10" and Jump_Flag = '0') -- JMF - else (others => '0'); - jump <= '1' when DI_OP = x"0F" -- JMP - or (Di_Op = x"10" and Jump_Flag = '0') -- JMF - else '0'; - --- case of JMF not triggering - Di_Op_Final <= x"ff" when (Di_Op = x"10" and Jump_Flag = '1') - else Di_Op; - - - end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd deleted file mode 100644 index 6b04c78..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd +++ /dev/null @@ -1,79 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 12:56:05 --- Design Name: --- Module Name: registers - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Registers is - Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); - Addr_B : in STD_LOGIC_VECTOR (3 downto 0); - Addr_W : in STD_LOGIC_VECTOR (3 downto 0); - Addr_C : in STD_LOGIC_VECTOR (3 downto 0); -- display on FPGA - W : in STD_LOGIC; - Data : in STD_LOGIC_VECTOR (7 downto 0); - Rst : in STD_LOGIC; - Clk : in STD_LOGIC; - QA : out STD_LOGIC_VECTOR (7 downto 0); - QB : out STD_LOGIC_VECTOR (7 downto 0); - QC : out STD_LOGIC_VECTOR (7 downto 0)); -end Registers; - -architecture Behavioral of Registers is - type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0); - signal Regs : Reg_array := (others => x"00"); -begin - process - begin - wait until clk'event and clk = '1'; - - if Rst = '1' then -- Reset - Regs <= (others => x"00"); - elsif W = '1' then -- Writing - Regs(to_integer(unsigned(Addr_W))) <= Data; - end if; - - end process; - - QA <= Regs(to_integer(unsigned(Addr_A))) - when W = '0' or Addr_W /= Addr_A - else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q - - QB <= Regs(to_integer(unsigned(Addr_B))) - when W = '0' or Addr_W /= Addr_B - else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q - - QC <= Regs(to_integer(unsigned(Addr_C))) - when W = '0' or Addr_W /= Addr_C - --else Regs(to_integer(unsigned(Addr_W))) - else - x"11" ; -- to bypass D --> Q - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd deleted file mode 100644 index 38fe1e4..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd +++ /dev/null @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 14:09:59 --- Design Name: --- Module Name: Pipeline - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Stage_Di_Ex is - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_C : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0); - Out_C : out STD_LOGIC_VECTOR (7 downto 0) - ); -end Stage_Di_Ex; - -architecture Behavioral of Stage_Di_Ex is - -begin - process - begin - wait until clk'event and clk = '1'; - Out_A <= In_A; - Out_B <= In_B; - Out_C <= In_C; - Out_Op <= In_Op; - end process; - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd deleted file mode 100644 index 082b4e3..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd +++ /dev/null @@ -1,56 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 14:09:59 --- Design Name: --- Module Name: Pipeline - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Stage_Ex_Mem is - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0) - ); -end Stage_Ex_Mem; - -architecture Behavioral of Stage_Ex_Mem is - -begin - process - begin - wait until clk'event and clk = '1'; - Out_A <= In_A; - Out_B <= In_B; - Out_Op <= In_Op; - end process; - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd deleted file mode 100644 index 88424f3..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd +++ /dev/null @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 14:09:59 --- Design Name: --- Module Name: Pipeline - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Stage_Li_Di is - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_C : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0); - Out_C : out STD_LOGIC_VECTOR (7 downto 0) - ); -end Stage_Li_Di; - -architecture Behavioral of Stage_Li_Di is - -begin - process - begin - wait until clk'event and clk = '1'; - Out_A <= In_A; - Out_B <= In_B; - Out_C <= In_C; - Out_Op <= In_Op; - end process; - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd deleted file mode 100644 index 4528761..0000000 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd +++ /dev/null @@ -1,56 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15.05.2023 14:09:59 --- Design Name: --- Module Name: Pipeline - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Stage_Mem_Re is - Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); - In_B : in STD_LOGIC_VECTOR (7 downto 0); - In_Op : in STD_LOGIC_VECTOR (7 downto 0); - Clk : in STD_LOGIC; - Out_A : out STD_LOGIC_VECTOR (7 downto 0); - Out_B : out STD_LOGIC_VECTOR (7 downto 0); - Out_Op : out STD_LOGIC_VECTOR (7 downto 0) - ); -end Stage_Mem_Re; - -architecture Behavioral of Stage_Mem_Re is - -begin - process - begin - wait until clk'event and clk = '1'; - Out_A <= In_A; - Out_B <= In_B; - Out_Op <= In_Op; - end process; - -end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/register.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/register.vhd deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr deleted file mode 100644 index a09f0c2..0000000 --- a/VHDL/ALU/ALU.xpr +++ /dev/null @@ -1,236 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/ALU/Test_Alu_behav.wcfg b/VHDL/ALU/Test_Alu_behav.wcfg deleted file mode 100644 index 13be292..0000000 --- a/VHDL/ALU/Test_Alu_behav.wcfg +++ /dev/null @@ -1,267 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - clock - clock - - - control signals - label - - - Clk - Clk - - - nop_Cntrl - nop_Cntrl - - - rst - rst - - - - LI - label - - - Li[31:0] - Li[31:0] - - - IP_out[7:0] - IP_out[7:0] - - - OP_LI_DI[7:0] - OP_LI_DI[7:0] - - - - DI - label - - Di_A[7:0] - Di_A[7:0] - - - Di_Op[7:0] - Di_Op[7:0] - - - Di_B[7:0] - Di_B[7:0] - - - Di_C[7:0] - Di_C[7:0] - - - Di_RegB[7:0] - Di_RegB[7:0] - - - Di_FinalB[7:0] - Di_FinalB[7:0] - - - Di_C2[7:0] - Di_C2[7:0] - - - - Ex - label - - Ex_A[7:0] - Ex_A[7:0] - - - Ex_Op[7:0] - Ex_Op[7:0] - - - Ex_B[7:0] - Ex_B[7:0] - - - Ex_C[7:0] - Ex_C[7:0] - - - Ex_Ctrl_ALu[7:0] - Ex_Ctrl_ALu[7:0] - - - Ex_Res_Alu[7:0] - Ex_Res_Alu[7:0] - - - Ex_FinalB[7:0] - Ex_FinalB[7:0] - - - S_NFlag - S_NFlag - - - S_Oflag - S_Oflag - - - S_CFlag - S_CFlag - - - S_ZFlag - S_ZFlag - - - - Mem - label - - Mem_A[7:0] - Mem_A[7:0] - - - Mem_Op[7:0] - Mem_Op[7:0] - - - Mem_B[7:0] - Mem_B[7:0] - - - Mem_RW - Mem_RW - - - Mem_Addr[7:0] - Mem_Addr[7:0] - - - Mem_Data_Out[7:0] - Mem_Data_Out[7:0] - UNSIGNEDDECRADIX - - - Mem_FinalB[7:0] - Mem_FinalB[7:0] - - - - Re - label - - Re_A[7:0] - Re_A[7:0] - - - Re_Op[7:0] - Re_Op[7:0] - - - Re_B[7:0] - Re_B[7:0] - - - Re_W - Re_W - - - addr_to_jump[7:0] - addr_to_jump[7:0] - - - jump - jump - - - W - W - - - - registers - label - - - [0][7:0] - [0][7:0] - UNSIGNEDDECRADIX - - - [1][7:0] - [1][7:0] - UNSIGNEDDECRADIX - - - [2][7:0] - [2][7:0] - - - [3][7:0] - [3][7:0] - - - [4][7:0] - [4][7:0] - - - [5][7:0] - [5][7:0] - - - - memory - label - - - [0][7:0] - [0][7:0] - SIGNEDDECRADIX - - - [1][7:0] - [1][7:0] - - - [2][7:0] - [2][7:0] - - - [3][7:0] - [3][7:0] - SIGNEDDECRADIX - - - [4][7:0] - [4][7:0] - - - diff --git a/asm2 b/asm2 deleted file mode 100644 index 334dc98..0000000 --- a/asm2 +++ /dev/null @@ -1,31 +0,0 @@ -AFC 0 5 -STORE 1 0 -LOAD 0 1 -STORE 0 0 -AFC 0 8 -STORE 1 0 -LOAD 0 0 -LOAD 1 1 -EQ 2 1 0 -STORE 2 2 -LOAD 0 2 -NOT 2 0 -STORE 3 2 -JMF 3 30 -AFC 0 20 -STORE 4 0 -LOAD 0 0 -LOAD 1 4 -INF 2 0 1 -STORE 2 2 -JMF 2 30 -AFC 0 2 -STORE 1 0 -LOAD 0 0 -LOAD 1 1 -ADD 0 0 1 -STORE 4 0 -LOAD 0 4 -STORE 0 0 -JMP 14 -NOP \ No newline at end of file diff --git a/asm3 b/asm3 deleted file mode 100644 index 8bc10dd..0000000 --- a/asm3 +++ /dev/null @@ -1 +0,0 @@ -((x"06000500"),(x"08010000"),(x"07000100"),(x"08000000"),(x"06000800"),(x"08010000"),(x"07000000"),(x"07010100"),(x"0B020100"),(x"08020200"),(x"07000200"),(x"0C020000"),(x"08030200"),(x"10031E00"),(x"06001400"),(x"08040000"),(x"07000000"),(x"07010400"),(x"09020001"),(x"08020200"),(x"10021E00"),(x"06000200"),(x"08010000"),(x"07000000"),(x"07010100"),(x"01000001"),(x"08040000"),(x"07000400"),(x"08000000"),(x"0F0E0000"),(x"FF000000"),others => (x"ff000000")) \ No newline at end of file diff --git a/asmTable.c b/asmTable.c deleted file mode 100644 index 875c979..0000000 --- a/asmTable.c +++ /dev/null @@ -1,109 +0,0 @@ - -#include -#include "asmTable.h" -#include "stdlib.h" -#include - -static int labelCounter = 0; - -/*At the start of the execution : the whole array is empty*/ -static ASMLine* asmTable; -static int lineCounter = 0; -static int maxIndex = START_TABLE_SIZE; - - -#include "asmTable.h" -#include "table.h" - -/* /!\ To be called at the beginning - * Initializes the array of Symbols*/ -void initASMTable(){ - asmTable = malloc(sizeof(ASMLine) * START_TABLE_SIZE); -} - -/*Checks for the length of the array and reallocates if necessary*/ -void checkASMArraySanity(){ - if (lineCounter == maxIndex){ - reallocateASMArray(maxIndex * 2); - } -} - -/*reallocates the array with the specified size*/ -void reallocateASMArray(int size){ - ASMLine *temp = (ASMLine*) realloc(asmTable, (sizeof(ASMLine) * size)); - if (temp != NULL){ - asmTable = temp; - } - else { - error("Cannot allocate more memory.\n"); - } -} - -/*inserts an asm code line at the current index*/ -void addLine(char* s) { - strcpy(asmTable[lineCounter].name,s); - asmTable[lineCounter].jumpLine = -1; - asmTable[lineCounter].conditionAddr = -1; - lineCounter++; - checkASMArraySanity(); - displayASMTable(); -} - -/*inserts the address in case of jumps*/ -void setJumpLine(int index, int addr) { - asmTable[index].jumpLine = addr; - displayASMTable(); -} - - -/*inserts the condition's address in case of jumps*/ -void setConditionAddr(int index, int addr) { - asmTable[index].conditionAddr = addr; - displayASMTable(); -} - -/*returns the current line (i.e. next one to insert)*/ -int getCurrentLineNumber() { - return lineCounter; -} - -/*displays the entire table at this moment*/ -void displayASMTable(){ - printf("\n"); - doubleLine(); - for (int i = 0; i < lineCounter; ++i) { - ASMLine a = asmTable[i]; - if(a.jumpLine == -1) { - printf("%d | %s\n", i, a.name); - } else { - if(a.conditionAddr == -1) { - printf("%d | %s %d\n", i, a.name,a.jumpLine); - } else { - printf("%d | %s %d %d\n", i, a.name,a.conditionAddr,a.jumpLine); - } - } - if (i != lineCounter -1) { - line(); - } - } - doubleLine(); -} - -/*exports the entire table to asm*/ -void exportASMTable(){ - FILE* fp; - fp = fopen("asm", "a"); - for (int i = 0; i < lineCounter; ++i) { - ASMLine a = asmTable[i]; - if(a.jumpLine == -1) { - fprintf(fp,"%s\n", a.name); - } else { - if(a.conditionAddr == -1) { - fprintf(fp,"%s %d\n", a.name,a.jumpLine); - } else { - fprintf(fp,"%s %d %d\n", a.name,a.conditionAddr,a.jumpLine); - } - } - } - fclose(fp); -} \ No newline at end of file diff --git a/asmTable.h b/asmTable.h deleted file mode 100644 index 489db7c..0000000 --- a/asmTable.h +++ /dev/null @@ -1,48 +0,0 @@ -// -// Created by chepycou on 4/18/23. -// - -#ifndef PROJET_SYSTEMES_INFORMATIQUES_ASMTABLE_H -#define PROJET_SYSTEMES_INFORMATIQUES_ASMTABLE_H - -#define START_TABLE_SIZE 128 -#define LINE_MAX_LENGTH 50 - -typedef struct { - char name[LINE_MAX_LENGTH]; - int conditionAddr; - int jumpLine; -} ASMLine; - -/*============================ - Array and Reallocation - ============================*/ - -/*reallocates the array with the specified size*/ -void reallocateASMArray(int size); - -/*Checks for the length of the array and reallocates if necessary*/ -void checkASMArraySanity(); - -/*inserts an asm code line at the current index*/ -void addLine(char* s); - -/* /!\ To be called at the beginning - * Initializes the array of Symbols*/ -void initASMTable(); - -/*inserts the address in case of jumps*/ -void setJumpLine(int index, int addr); - -/*inserts the condition's address in case of jumps*/ -void setConditionAddr(int index, int addr); - -/*returns the current line (i.e. next one to insert)*/ -int getCurrentLineNumber(); - -/*displays the entire table at this moment*/ -void displayASMTable(); - -/*exports the entire table to asm*/ -void exportASMTable(); -#endif //PROJET_SYSTEMES_INFORMATIQUES_ASMTABLE_H diff --git a/asmTable.o b/asmTable.o deleted file mode 100644 index 84e9255..0000000 Binary files a/asmTable.o and /dev/null differ diff --git a/blocs.c b/blocs.c deleted file mode 100644 index c9a601d..0000000 --- a/blocs.c +++ /dev/null @@ -1,59 +0,0 @@ -// -// Created by chepycou on 4/18/23. -// - -#include "blocs.h" -#include "operations.h" -#include -#include - -/*TODO on écrit tout dans un fichier asm extérieur puis on : - * - fait un parcours pour stocker dans une liste chaînée par exemple les valeur de ligne des labels - * - faire un parcours pour retirer les labels au début des lignes - * - faire un parcours pour remplacer les labels par leur valeur - * */ -/* -int labelCount = 0; - -int getNextLabel(){ - return(labelCount++); -} - - -void printLabel(int labelWhile){ - char label[LABEL_MAX_LENGTH]; - sprintf(label,"%d_LABEL\n",labelWhile); - printf("%s",label); - FILE* fp; - fp = fopen("asm", "a"); - fputs(label, fp); - fclose(fp); -} - -int printNewLabel(){ - int l = getNextLabel(); - printLabel(l); - return l; -} - -void printJumpToLabel(int labelWhile) { - char instr[ASM_TEXT_LEN]; - sprintf(instr,"JMP %d_LABEL\n",labelWhile); - printf("%s",instr); - FILE* fp; - fp = fopen("asm", "a"); - fputs(instr, fp); - fclose(fp); -} - -void printJumpFToLabel(int labelWhile) { - char label[LABEL_MAX_LENGTH]; - sprintf(label,"%d_LABEL\n",labelWhile); - printf("JMF %s",label); - FILE* fp; - fp = fopen("asm", "a"); - fputs(label, fp); - fclose(fp); -}*/ - - diff --git a/blocs.h b/blocs.h deleted file mode 100644 index 1cddf09..0000000 --- a/blocs.h +++ /dev/null @@ -1,26 +0,0 @@ -// -// Created by chepycou on 4/18/23. -// - -#ifndef PROJET_SYSTEMES_INFORMATIQUES_BLOCS_H -#define PROJET_SYSTEMES_INFORMATIQUES_BLOCS_H - -#define LABEL_MAX_LENGTH 20 - -/*====================== - Label Management - ======================*/ - -/*returns the next label*/ -int getNextLabel(); - -// prints a new label and returns the index of it -int printNewLabel(); - -// prints a label and returns the index of it -void printLabel(int labelWhile); - -// prints a jump to the label and returns the index of it -void printJumpToLabel(int labelWhile); - -#endif //PROJET_SYSTEMES_INFORMATIQUES_BLOCS_H diff --git a/blocs.o b/blocs.o deleted file mode 100644 index 4668e20..0000000 Binary files a/blocs.o and /dev/null differ diff --git a/graph_interpreter.py b/graph_interpreter.py deleted file mode 100644 index b3384bb..0000000 --- a/graph_interpreter.py +++ /dev/null @@ -1,140 +0,0 @@ -import sys - - -try: - from textual.color import Color - from textual import events - from textual.app import App, ComposeResult - from textual.containers import Container, VerticalScroll - from textual.widgets import Footer, Header, Static -except: - print("please install textual and rich !") - - -def getLinesToShow(ip, lines): - if ip > 1 and ip + 2 < len(lines): - l= lines[ip - 2: ip + 3] - l[2] = "> " + l[2] + " <" - elif ip <= 1: - l= lines[0: 5] - l[ip] = "> " + l[ip] + " <" - else: - l= lines[-5:] - l[ip-len(lines)] = "> " + l[ip-len(lines)] + " <" - return l - - -def update_interpreter(self): - global ip - global ASMLines - global dataMem - if "NOP" not in ASMLines[ip]: - incr = 1 - currLine = ASMLines[ip].split() - match currLine[0]: - case "ADD": - dataMem[currLine[1]] = dataMem[currLine[2]] + dataMem[currLine[3]] - case "MUL": - dataMem[currLine[1]] = dataMem[currLine[2]] * dataMem[currLine[3]] - case "SUB": - dataMem[currLine[1]] = dataMem[currLine[2]] - dataMem[currLine[3]] - case "DIV": - dataMem[currLine[1]] = dataMem[currLine[2]] / dataMem[currLine[3]] - case "COP": - dataMem[currLine[1]] = dataMem[currLine[2]] - case "AFC": - dataMem[currLine[1]] = int(currLine[2]) - case "SUP": - dataMem[currLine[1]] = dataMem[currLine[2]] > dataMem[currLine[3]] - case "EQ": - dataMem[currLine[1]] = dataMem[currLine[2]] == dataMem[currLine[3]] - case "NOT": - dataMem[currLine[1]] = not dataMem[currLine[2]] - case "INF": - dataMem[currLine[1]] = dataMem[currLine[2]] < dataMem[currLine[3]] - case "AND": - dataMem[currLine[1]] = dataMem[currLine[2]] and dataMem[currLine[3]] - case "OR": - dataMem[currLine[1]] = dataMem[currLine[2]] and dataMem[currLine[3]] - case "JMP": - ip = int(currLine[1]) - incr = 0 - case "JMF": - if not dataMem[currLine[1]]: - incr = 0 - ip = int(currLine[2]) - print(ip) - case "CAL": - pass - case "RET": - pass - case "PRI": - pass - case default: - pass - print(ASMLines[ip], ", ".join([f"{i}:{dataMem.get(i)}" for i in dataMem])) - ip += incr - else: - cont = self.query_one("#cont", Container) - cont.styles.background = Color.parse("#151E3D") - - code = self.query_one("#code", Static) - code.update(" ") - -class codeLines(Static): - """one line of assembly code""" - def update_code(self, line) -> None: - self.update(line) -class registers(Static): - """one line of assembly code""" - def update_regs(self, line) -> None: - self.update(line) - - -class interpreter(App): - """A Textual app to see your asm code run !.""" - TITLE = "A Textual app to see your asm code run !." - CSS_PATH = "style.css" - BINDINGS = [ - ("q", "quit", "Quit"), - ] - - def compose(self) -> ComposeResult: - """Compose our UI.""" - path = "./" if len(sys.argv) < 2 else sys.argv[1] - yield Header() - with Container(id="cont"): - with VerticalScroll(id="code-view"): - yield codeLines("\n".join(getLinesToShow(ip, ASMLines)),id="code", expand=True) - yield registers(id="regs", expand=True) - yield Footer() - - def on_key(self, event: events.Key) -> None: - code = self.query_one("#code", Static) - regs = self.query_one("#regs", Static) - update_interpreter(self) - - global ip, ASMLines - code.update_code("\n".join(getLinesToShow(ip, ASMLines))) - l = [] - for i in range(max([int(i)+1 for i in dataMem.keys()])): - if str(i) in dataMem.keys(): - l.append([i, dataMem[str(i)]]) - - regs.update_regs("\n".join([f"@{k[0]} : {k[1]}" for k in l])) - -if __name__ == "__main__": - - fileInput = open("asm", "r") - global ASMLines - ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines())) - fileInput.close() - ASMLines.append("NOP") - - global dataMem - dataMem = {} - - global ip - ip = 0 - - interpreter().run() diff --git a/interpreter.py b/interpreter.py deleted file mode 100644 index 192e619..0000000 --- a/interpreter.py +++ /dev/null @@ -1,61 +0,0 @@ -from rich.console import Console -from rich.table import Table -table = Table() - -table.add_column("Operation", justify="left", style="red", no_wrap=True) -table.add_column("Register State", justify="center", style="green") - -fileInput = open("asm", "r") -ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines())) -fileInput.close() -ASMLines.append("NOP") - -dataMem = {} -ip = 0 -while ip < len(ASMLines): - incr = 1 - currLine = ASMLines[ip].split() - match currLine[0]: - case "ADD": - dataMem[currLine[1]] = dataMem[currLine[2]] + dataMem[currLine[3]] - case "MUL": - dataMem[currLine[1]] = dataMem[currLine[2]] * dataMem[currLine[3]] - case "SUB": - dataMem[currLine[1]] = dataMem[currLine[2]] - dataMem[currLine[3]] - case "DIV": - dataMem[currLine[1]] = dataMem[currLine[2]] / dataMem[currLine[3]] - case "COP": - dataMem[currLine[1]] = dataMem[currLine[2]] - case "AFC": - dataMem[currLine[1]] = int(currLine[2]) - case "SUP": - dataMem[currLine[1]] = dataMem[currLine[2]] > dataMem[currLine[3]] - case "EQ": - dataMem[currLine[1]] = dataMem[currLine[2]] == dataMem[currLine[3]] - case "NOT": - dataMem[currLine[1]] = not dataMem[currLine[2]] - case "INF": - dataMem[currLine[1]] = dataMem[currLine[2]] < dataMem[currLine[3]] - case "AND": - dataMem[currLine[1]] = dataMem[currLine[2]] and dataMem[currLine[3]] - case "OR": - dataMem[currLine[1]] = dataMem[currLine[2]] and dataMem[currLine[3]] - case "JMP": - ip = int(currLine[1]) - incr = 0 - case "JMF": - if not dataMem[currLine[1]]: - incr = 0 - ip = int(currLine[2]) - case "CAL": - pass - case "RET": - pass - case "PRI": - pass - case default: - pass - table.add_row(ASMLines[ip], ", ".join([f"{i}:{dataMem.get(i)}" for i in dataMem])) - ip += incr -console = Console() -console.print(table) diff --git a/lex.l b/lex.l deleted file mode 100644 index f4da442..0000000 --- a/lex.l +++ /dev/null @@ -1,71 +0,0 @@ -%{ -#include "table.h" -#include "yacc.tab.h" -%} - -/*options for compiling*/ -%option noyywrap -%option noinput -%option nounput - - - /*definition of the different types of comments*/ -M_COMMENT (\/\/).* -S_COMMENT \/\*(.|\n)*?\*\/ - - - /*definition of the Ids and types of ints*/ -ID [a-zA-Z][a-zA-Z0-9]* -INT_DEC [0-9]+ -INT_HEX 0x[0-9a-fA-F]+ - - -%% - - -"if" return(tIF); -"else" return(tELSE); -"while" return(tWHILE); -"print" return(tPRINT); -"return" return(tRETURN); -"float" return(tFLOAT); -"int" return(tINT); -"void" return(tVOID); -"+" return(tADD); -"-" return(tSUB); -"*" return(tMUL); -"/" return(tDIV); -"<" return(tLT); -">" return(tGT); -"!=" return(tNE); -"==" return(tEQ); -">=" return(tGE); -"<=" return(tLE); -"=" return(tASSIGN); -"&&" return(tAND); -"||" return(tOR); -"!" return(tNOT); -"{" return(tLBRACE); -"}" return(tRBRACE); -"(" return(tLPAR); -")" return(tRPAR); -";" return(tSEMI); -"," return(tCOMMA); - -{ID} {strncpy(yylval.str, yytext, NAME_MAX_LENGTH); return(tID);} -{INT_DEC} {yylval.nbInt = atoi(yytext); return(tNB);} -{INT_HEX} {yylval.nbInt = atoi(yytext); return(tNB);} - - - /*comments are ignored, same for spaces and lines*/ -{M_COMMENT} ; -{S_COMMENT} ; -[ ]+ ; -\n ; - - /*anything else is considered an error*/ -. yyerror(yytext); - -%% - - // SI >> SC diff --git a/lex.yy.c b/lex.yy.c deleted file mode 100644 index 6009c51..0000000 --- a/lex.yy.c +++ /dev/null @@ -1,1941 +0,0 @@ - -#line 3 "lex.yy.c" - -#define YY_INT_ALIGNED short int - -/* A lexical scanner generated by flex */ - -#define FLEX_SCANNER -#define YY_FLEX_MAJOR_VERSION 2 -#define YY_FLEX_MINOR_VERSION 6 -#define YY_FLEX_SUBMINOR_VERSION 4 -#if YY_FLEX_SUBMINOR_VERSION > 0 -#define FLEX_BETA -#endif - -/* First, we deal with platform-specific or compiler-specific issues. */ - -/* begin standard C headers. */ -#include -#include -#include -#include - -/* end standard C headers. */ - -/* flex integer type definitions */ - -#ifndef FLEXINT_H -#define FLEXINT_H - -/* C99 systems have . Non-C99 systems may or may not. */ - -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L - -/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, - * if you want the limit (max/min) macros for int types. - */ -#ifndef __STDC_LIMIT_MACROS -#define __STDC_LIMIT_MACROS 1 -#endif - -#include -typedef int8_t flex_int8_t; -typedef uint8_t flex_uint8_t; -typedef int16_t flex_int16_t; -typedef uint16_t flex_uint16_t; -typedef int32_t flex_int32_t; -typedef uint32_t flex_uint32_t; -#else -typedef signed char flex_int8_t; -typedef short int flex_int16_t; -typedef int flex_int32_t; -typedef unsigned char flex_uint8_t; -typedef unsigned short int flex_uint16_t; -typedef unsigned int flex_uint32_t; - -/* Limits of integral types. */ -#ifndef INT8_MIN -#define INT8_MIN (-128) -#endif -#ifndef INT16_MIN -#define INT16_MIN (-32767-1) -#endif -#ifndef INT32_MIN -#define INT32_MIN (-2147483647-1) -#endif -#ifndef INT8_MAX -#define INT8_MAX (127) -#endif -#ifndef INT16_MAX -#define INT16_MAX (32767) -#endif -#ifndef INT32_MAX -#define INT32_MAX (2147483647) -#endif -#ifndef UINT8_MAX -#define UINT8_MAX (255U) -#endif -#ifndef UINT16_MAX -#define UINT16_MAX (65535U) -#endif -#ifndef UINT32_MAX -#define UINT32_MAX (4294967295U) -#endif - -#ifndef SIZE_MAX -#define SIZE_MAX (~(size_t)0) -#endif - -#endif /* ! C99 */ - -#endif /* ! FLEXINT_H */ - -/* begin standard C++ headers. */ - -/* TODO: this is always defined, so inline it */ -#define yyconst const - -#if defined(__GNUC__) && __GNUC__ >= 3 -#define yynoreturn __attribute__((__noreturn__)) -#else -#define yynoreturn -#endif - -/* Returned upon end-of-file. */ -#define YY_NULL 0 - -/* Promotes a possibly negative, possibly signed char to an - * integer in range [0..255] for use as an array index. - */ -#define YY_SC_TO_UI(c) ((YY_CHAR) (c)) - -/* Enter a start condition. This macro really ought to take a parameter, - * but we do it the disgusting crufty way forced on us by the ()-less - * definition of BEGIN. - */ -#define BEGIN (yy_start) = 1 + 2 * -/* Translate the current start state into a value that can be later handed - * to BEGIN to return to the state. The YYSTATE alias is for lex - * compatibility. - */ -#define YY_START (((yy_start) - 1) / 2) -#define YYSTATE YY_START -/* Action number for EOF rule of a given start state. */ -#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) -/* Special action meaning "start processing a new file". */ -#define YY_NEW_FILE yyrestart( yyin ) -#define YY_END_OF_BUFFER_CHAR 0 - -/* Size of default input buffer. */ -#ifndef YY_BUF_SIZE -#ifdef __ia64__ -/* On IA-64, the buffer size is 16k, not 8k. - * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. - * Ditto for the __ia64__ case accordingly. - */ -#define YY_BUF_SIZE 32768 -#else -#define YY_BUF_SIZE 16384 -#endif /* __ia64__ */ -#endif - -/* The state buf must be large enough to hold one state per character in the main buffer. - */ -#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type)) - -#ifndef YY_TYPEDEF_YY_BUFFER_STATE -#define YY_TYPEDEF_YY_BUFFER_STATE -typedef struct yy_buffer_state *YY_BUFFER_STATE; -#endif - -#ifndef YY_TYPEDEF_YY_SIZE_T -#define YY_TYPEDEF_YY_SIZE_T -typedef size_t yy_size_t; -#endif - -extern int yyleng; - -extern FILE *yyin, *yyout; - -#define EOB_ACT_CONTINUE_SCAN 0 -#define EOB_ACT_END_OF_FILE 1 -#define EOB_ACT_LAST_MATCH 2 - - #define YY_LESS_LINENO(n) - #define YY_LINENO_REWIND_TO(ptr) - -/* Return all but the first "n" matched characters back to the input stream. */ -#define yyless(n) \ - do \ - { \ - /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ - YY_LESS_LINENO(yyless_macro_arg);\ - *yy_cp = (yy_hold_char); \ - YY_RESTORE_YY_MORE_OFFSET \ - (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \ - YY_DO_BEFORE_ACTION; /* set up yytext again */ \ - } \ - while ( 0 ) -#define unput(c) yyunput( c, (yytext_ptr) ) - -#ifndef YY_STRUCT_YY_BUFFER_STATE -#define YY_STRUCT_YY_BUFFER_STATE -struct yy_buffer_state - { - FILE *yy_input_file; - - char *yy_ch_buf; /* input buffer */ - char *yy_buf_pos; /* current position in input buffer */ - - /* Size of input buffer in bytes, not including room for EOB - * characters. - */ - int yy_buf_size; - - /* Number of characters read into yy_ch_buf, not including EOB - * characters. - */ - int yy_n_chars; - - /* Whether we "own" the buffer - i.e., we know we created it, - * and can realloc() it to grow it, and should free() it to - * delete it. - */ - int yy_is_our_buffer; - - /* Whether this is an "interactive" input source; if so, and - * if we're using stdio for input, then we want to use getc() - * instead of fread(), to make sure we stop fetching input after - * each newline. - */ - int yy_is_interactive; - - /* Whether we're considered to be at the beginning of a line. - * If so, '^' rules will be active on the next match, otherwise - * not. - */ - int yy_at_bol; - - int yy_bs_lineno; /**< The line count. */ - int yy_bs_column; /**< The column count. */ - - /* Whether to try to fill the input buffer when we reach the - * end of it. - */ - int yy_fill_buffer; - - int yy_buffer_status; - -#define YY_BUFFER_NEW 0 -#define YY_BUFFER_NORMAL 1 - /* When an EOF's been seen but there's still some text to process - * then we mark the buffer as YY_EOF_PENDING, to indicate that we - * shouldn't try reading from the input source any more. We might - * still have a bunch of tokens to match, though, because of - * possible backing-up. - * - * When we actually see the EOF, we change the status to "new" - * (via yyrestart()), so that the user can continue scanning by - * just pointing yyin at a new input file. - */ -#define YY_BUFFER_EOF_PENDING 2 - - }; -#endif /* !YY_STRUCT_YY_BUFFER_STATE */ - -/* Stack of input buffers. */ -static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */ -static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */ -static YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */ - -/* We provide macros for accessing buffer states in case in the - * future we want to put the buffer states in a more general - * "scanner state". - * - * Returns the top of the stack, or NULL. - */ -#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ - ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ - : NULL) -/* Same as previous macro, but useful when we know that the buffer stack is not - * NULL or when we need an lvalue. For internal use only. - */ -#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)] - -/* yy_hold_char holds the character lost when yytext is formed. */ -static char yy_hold_char; -static int yy_n_chars; /* number of characters read into yy_ch_buf */ -int yyleng; - -/* Points to current character in buffer. */ -static char *yy_c_buf_p = NULL; -static int yy_init = 0; /* whether we need to initialize */ -static int yy_start = 0; /* start state number */ - -/* Flag which is used to allow yywrap()'s to do buffer switches - * instead of setting up a fresh yyin. A bit of a hack ... - */ -static int yy_did_buffer_switch_on_eof; - -void yyrestart ( FILE *input_file ); -void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer ); -YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size ); -void yy_delete_buffer ( YY_BUFFER_STATE b ); -void yy_flush_buffer ( YY_BUFFER_STATE b ); -void yypush_buffer_state ( YY_BUFFER_STATE new_buffer ); -void yypop_buffer_state ( void ); - -static void yyensure_buffer_stack ( void ); -static void yy_load_buffer_state ( void ); -static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file ); -#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER ) - -YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size ); -YY_BUFFER_STATE yy_scan_string ( const char *yy_str ); -YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len ); - -void *yyalloc ( yy_size_t ); -void *yyrealloc ( void *, yy_size_t ); -void yyfree ( void * ); - -#define yy_new_buffer yy_create_buffer -#define yy_set_interactive(is_interactive) \ - { \ - if ( ! YY_CURRENT_BUFFER ){ \ - yyensure_buffer_stack (); \ - YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer( yyin, YY_BUF_SIZE ); \ - } \ - YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ - } -#define yy_set_bol(at_bol) \ - { \ - if ( ! YY_CURRENT_BUFFER ){\ - yyensure_buffer_stack (); \ - YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer( yyin, YY_BUF_SIZE ); \ - } \ - YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ - } -#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) - -/* Begin user sect3 */ - -#define yywrap() (/*CONSTCOND*/1) -#define YY_SKIP_YYWRAP -typedef flex_uint8_t YY_CHAR; - -FILE *yyin = NULL, *yyout = NULL; - -typedef int yy_state_type; - -extern int yylineno; -int yylineno = 1; - -extern char *yytext; -#ifdef yytext_ptr -#undef yytext_ptr -#endif -#define yytext_ptr yytext - -static yy_state_type yy_get_previous_state ( void ); -static yy_state_type yy_try_NUL_trans ( yy_state_type current_state ); -static int yy_get_next_buffer ( void ); -static void yynoreturn yy_fatal_error ( const char* msg ); - -/* Done after the current pattern has been matched and before the - * corresponding action - sets up yytext. - */ -#define YY_DO_BEFORE_ACTION \ - (yytext_ptr) = yy_bp; \ - yyleng = (int) (yy_cp - yy_bp); \ - (yy_hold_char) = *yy_cp; \ - *yy_cp = '\0'; \ - (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 37 -#define YY_END_OF_BUFFER 38 -/* This struct is not used in this scanner, - but its presence is necessary. */ -struct yy_trans_info - { - flex_int32_t yy_verify; - flex_int32_t yy_nxt; - }; -static const flex_int16_t yy_accept[77] = - { 0, - 0, 0, 38, 36, 35, 34, 22, 36, 25, 26, - 11, 9, 28, 10, 12, 30, 30, 27, 13, 19, - 14, 29, 29, 29, 29, 29, 29, 29, 29, 23, - 36, 24, 34, 15, 20, 0, 32, 30, 0, 18, - 16, 17, 29, 29, 29, 1, 29, 29, 29, 29, - 29, 21, 0, 0, 32, 31, 29, 29, 7, 29, - 29, 29, 29, 33, 2, 29, 29, 29, 8, 29, - 6, 4, 29, 3, 5, 0 - } ; - -static const YY_CHAR yy_ec[256] = - { 0, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 3, 4, 1, 1, 1, 1, 5, 1, 6, - 7, 8, 9, 10, 11, 1, 12, 13, 14, 14, - 14, 14, 14, 14, 14, 14, 14, 1, 15, 16, - 17, 18, 1, 1, 19, 19, 19, 19, 19, 19, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 1, 1, 1, 1, 1, 1, 21, 19, 19, 22, - - 23, 24, 20, 25, 26, 20, 20, 27, 20, 28, - 29, 30, 20, 31, 32, 33, 34, 35, 36, 37, - 20, 20, 38, 39, 40, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1 - } ; - -static const YY_CHAR yy_meta[41] = - { 0, - 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 3, 3, 1, 1, 1, 1, 3, 4, - 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 1, 1, 1 - } ; - -static const flex_int16_t yy_base[81] = - { 0, - 0, 0, 99, 100, 100, 95, 80, 91, 100, 100, - 100, 100, 100, 100, 33, 29, 33, 100, 78, 77, - 76, 0, 65, 64, 20, 59, 66, 59, 62, 100, - 47, 100, 82, 100, 100, 76, 0, 36, 0, 100, - 100, 100, 0, 51, 53, 0, 48, 54, 46, 52, - 51, 100, 66, 43, 0, 0, 42, 43, 0, 35, - 28, 39, 33, 51, 0, 25, 24, 25, 0, 31, - 0, 0, 25, 0, 0, 100, 64, 68, 72, 49 - } ; - -static const flex_int16_t yy_def[81] = - { 0, - 76, 1, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 77, 77, 77, 77, 77, 77, 77, 77, 76, - 76, 76, 76, 76, 76, 78, 79, 76, 80, 76, - 76, 76, 77, 77, 77, 77, 77, 77, 77, 77, - 77, 76, 78, 78, 79, 80, 77, 77, 77, 77, - 77, 77, 77, 78, 77, 77, 77, 77, 77, 77, - 77, 77, 77, 77, 77, 0, 76, 76, 76, 76 - } ; - -static const flex_int16_t yy_nxt[141] = - { 0, - 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, - 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, - 22, 22, 23, 24, 22, 25, 22, 22, 22, 26, - 27, 22, 22, 22, 28, 29, 22, 30, 31, 32, - 36, 38, 38, 46, 37, 38, 38, 47, 38, 38, - 54, 56, 75, 74, 64, 73, 72, 71, 54, 70, - 69, 68, 67, 66, 65, 39, 43, 43, 53, 53, - 53, 53, 55, 54, 55, 55, 63, 62, 61, 60, - 59, 58, 57, 54, 33, 52, 51, 50, 49, 48, - 45, 44, 42, 41, 40, 35, 34, 33, 76, 3, - - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76 - } ; - -static const flex_int16_t yy_chk[141] = - { 0, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 15, 16, 16, 25, 15, 17, 17, 25, 38, 38, - 54, 80, 73, 70, 54, 68, 67, 66, 64, 63, - 62, 61, 60, 58, 57, 16, 77, 77, 78, 78, - 78, 78, 79, 53, 79, 79, 51, 50, 49, 48, - 47, 45, 44, 36, 33, 31, 29, 28, 27, 26, - 24, 23, 21, 20, 19, 8, 7, 6, 3, 76, - - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 76 - } ; - -static yy_state_type yy_last_accepting_state; -static char *yy_last_accepting_cpos; - -extern int yy_flex_debug; -int yy_flex_debug = 0; - -/* The intent behind this definition is that it'll catch - * any uses of REJECT which flex missed. - */ -#define REJECT reject_used_but_not_detected -#define yymore() yymore_used_but_not_detected -#define YY_MORE_ADJ 0 -#define YY_RESTORE_YY_MORE_OFFSET -char *yytext; -#line 1 "lex.l" -#line 2 "lex.l" -#include "table.h" -#include "yacc.tab.h" -#line 499 "lex.yy.c" -/*options for compiling*/ -#define YY_NO_INPUT 1 -#line 13 "lex.l" - /*definition of the different types of comments*/ - /*definition of the Ids and types of ints*/ -#line 505 "lex.yy.c" - -#define INITIAL 0 - -#ifndef YY_NO_UNISTD_H -/* Special case for "unistd.h", since it is non-ANSI. We include it way - * down here because we want the user's section 1 to have been scanned first. - * The user has a chance to override it with an option. - */ -#include -#endif - -#ifndef YY_EXTRA_TYPE -#define YY_EXTRA_TYPE void * -#endif - -static int yy_init_globals ( void ); - -/* Accessor methods to globals. - These are made visible to non-reentrant scanners for convenience. */ - -int yylex_destroy ( void ); - -int yyget_debug ( void ); - -void yyset_debug ( int debug_flag ); - -YY_EXTRA_TYPE yyget_extra ( void ); - -void yyset_extra ( YY_EXTRA_TYPE user_defined ); - -FILE *yyget_in ( void ); - -void yyset_in ( FILE * _in_str ); - -FILE *yyget_out ( void ); - -void yyset_out ( FILE * _out_str ); - - int yyget_leng ( void ); - -char *yyget_text ( void ); - -int yyget_lineno ( void ); - -void yyset_lineno ( int _line_number ); - -/* Macros after this point can all be overridden by user definitions in - * section 1. - */ - -#ifndef YY_SKIP_YYWRAP -#ifdef __cplusplus -extern "C" int yywrap ( void ); -#else -extern int yywrap ( void ); -#endif -#endif - -#ifndef YY_NO_UNPUT - -#endif - -#ifndef yytext_ptr -static void yy_flex_strncpy ( char *, const char *, int ); -#endif - -#ifdef YY_NEED_STRLEN -static int yy_flex_strlen ( const char * ); -#endif - -#ifndef YY_NO_INPUT -#ifdef __cplusplus -static int yyinput ( void ); -#else -static int input ( void ); -#endif - -#endif - -/* Amount of stuff to slurp up with each read. */ -#ifndef YY_READ_BUF_SIZE -#ifdef __ia64__ -/* On IA-64, the buffer size is 16k, not 8k */ -#define YY_READ_BUF_SIZE 16384 -#else -#define YY_READ_BUF_SIZE 8192 -#endif /* __ia64__ */ -#endif - -/* Copy whatever the last rule matched to the standard output. */ -#ifndef ECHO -/* This used to be an fputs(), but since the string might contain NUL's, - * we now use fwrite(). - */ -#define ECHO do { if (fwrite( yytext, (size_t) yyleng, 1, yyout )) {} } while (0) -#endif - -/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, - * is returned in "result". - */ -#ifndef YY_INPUT -#define YY_INPUT(buf,result,max_size) \ - if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ - { \ - int c = '*'; \ - int n; \ - for ( n = 0; n < max_size && \ - (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ - buf[n] = (char) c; \ - if ( c == '\n' ) \ - buf[n++] = (char) c; \ - if ( c == EOF && ferror( yyin ) ) \ - YY_FATAL_ERROR( "input in flex scanner failed" ); \ - result = n; \ - } \ - else \ - { \ - errno=0; \ - while ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \ - { \ - if( errno != EINTR) \ - { \ - YY_FATAL_ERROR( "input in flex scanner failed" ); \ - break; \ - } \ - errno=0; \ - clearerr(yyin); \ - } \ - }\ -\ - -#endif - -/* No semi-colon after return; correct usage is to write "yyterminate();" - - * we don't want an extra ';' after the "return" because that will cause - * some compilers to complain about unreachable statements. - */ -#ifndef yyterminate -#define yyterminate() return YY_NULL -#endif - -/* Number of entries by which start-condition stack grows. */ -#ifndef YY_START_STACK_INCR -#define YY_START_STACK_INCR 25 -#endif - -/* Report a fatal error. */ -#ifndef YY_FATAL_ERROR -#define YY_FATAL_ERROR(msg) yy_fatal_error( msg ) -#endif - -/* end tables serialization structures and prototypes */ - -/* Default declaration of generated scanner - a define so the user can - * easily add parameters. - */ -#ifndef YY_DECL -#define YY_DECL_IS_OURS 1 - -extern int yylex (void); - -#define YY_DECL int yylex (void) -#endif /* !YY_DECL */ - -/* Code executed at the beginning of each rule, after yytext and yyleng - * have been set up. - */ -#ifndef YY_USER_ACTION -#define YY_USER_ACTION -#endif - -/* Code executed at the end of each rule. */ -#ifndef YY_BREAK -#define YY_BREAK /*LINTED*/break; -#endif - -#define YY_RULE_SETUP \ - YY_USER_ACTION - -/** The main scanner function which does all the work. - */ -YY_DECL -{ - yy_state_type yy_current_state; - char *yy_cp, *yy_bp; - int yy_act; - - if ( !(yy_init) ) - { - (yy_init) = 1; - -#ifdef YY_USER_INIT - YY_USER_INIT; -#endif - - if ( ! (yy_start) ) - (yy_start) = 1; /* first start state */ - - if ( ! yyin ) - yyin = stdin; - - if ( ! yyout ) - yyout = stdout; - - if ( ! YY_CURRENT_BUFFER ) { - yyensure_buffer_stack (); - YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer( yyin, YY_BUF_SIZE ); - } - - yy_load_buffer_state( ); - } - - { -#line 24 "lex.l" - - - -#line 724 "lex.yy.c" - - while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */ - { - yy_cp = (yy_c_buf_p); - - /* Support of yytext. */ - *yy_cp = (yy_hold_char); - - /* yy_bp points to the position in yy_ch_buf of the start of - * the current run. - */ - yy_bp = yy_cp; - - yy_current_state = (yy_start); -yy_match: - do - { - YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; - if ( yy_accept[yy_current_state] ) - { - (yy_last_accepting_state) = yy_current_state; - (yy_last_accepting_cpos) = yy_cp; - } - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 77 ) - yy_c = yy_meta[yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - ++yy_cp; - } - while ( yy_base[yy_current_state] != 100 ); - -yy_find_action: - yy_act = yy_accept[yy_current_state]; - if ( yy_act == 0 ) - { /* have to back up */ - yy_cp = (yy_last_accepting_cpos); - yy_current_state = (yy_last_accepting_state); - yy_act = yy_accept[yy_current_state]; - } - - YY_DO_BEFORE_ACTION; - -do_action: /* This label is used only to access EOF actions. */ - - switch ( yy_act ) - { /* beginning of action switch */ - case 0: /* must back up */ - /* undo the effects of YY_DO_BEFORE_ACTION */ - *yy_cp = (yy_hold_char); - yy_cp = (yy_last_accepting_cpos); - yy_current_state = (yy_last_accepting_state); - goto yy_find_action; - -case 1: -YY_RULE_SETUP -#line 27 "lex.l" -return(tIF); - YY_BREAK -case 2: -YY_RULE_SETUP -#line 28 "lex.l" -return(tELSE); - YY_BREAK -case 3: -YY_RULE_SETUP -#line 29 "lex.l" -return(tWHILE); - YY_BREAK -case 4: -YY_RULE_SETUP -#line 30 "lex.l" -return(tPRINT); - YY_BREAK -case 5: -YY_RULE_SETUP -#line 31 "lex.l" -return(tRETURN); - YY_BREAK -case 6: -YY_RULE_SETUP -#line 32 "lex.l" -return(tFLOAT); - YY_BREAK -case 7: -YY_RULE_SETUP -#line 33 "lex.l" -return(tINT); - YY_BREAK -case 8: -YY_RULE_SETUP -#line 34 "lex.l" -return(tVOID); - YY_BREAK -case 9: -YY_RULE_SETUP -#line 35 "lex.l" -return(tADD); - YY_BREAK -case 10: -YY_RULE_SETUP -#line 36 "lex.l" -return(tSUB); - YY_BREAK -case 11: -YY_RULE_SETUP -#line 37 "lex.l" -return(tMUL); - YY_BREAK -case 12: -YY_RULE_SETUP -#line 38 "lex.l" -return(tDIV); - YY_BREAK -case 13: -YY_RULE_SETUP -#line 39 "lex.l" -return(tLT); - YY_BREAK -case 14: -YY_RULE_SETUP -#line 40 "lex.l" -return(tGT); - YY_BREAK -case 15: -YY_RULE_SETUP -#line 41 "lex.l" -return(tNE); - YY_BREAK -case 16: -YY_RULE_SETUP -#line 42 "lex.l" -return(tEQ); - YY_BREAK -case 17: -YY_RULE_SETUP -#line 43 "lex.l" -return(tGE); - YY_BREAK -case 18: -YY_RULE_SETUP -#line 44 "lex.l" -return(tLE); - YY_BREAK -case 19: -YY_RULE_SETUP -#line 45 "lex.l" -return(tASSIGN); - YY_BREAK -case 20: -YY_RULE_SETUP -#line 46 "lex.l" -return(tAND); - YY_BREAK -case 21: -YY_RULE_SETUP -#line 47 "lex.l" -return(tOR); - YY_BREAK -case 22: -YY_RULE_SETUP -#line 48 "lex.l" -return(tNOT); - YY_BREAK -case 23: -YY_RULE_SETUP -#line 49 "lex.l" -return(tLBRACE); - YY_BREAK -case 24: -YY_RULE_SETUP -#line 50 "lex.l" -return(tRBRACE); - YY_BREAK -case 25: -YY_RULE_SETUP -#line 51 "lex.l" -return(tLPAR); - YY_BREAK -case 26: -YY_RULE_SETUP -#line 52 "lex.l" -return(tRPAR); - YY_BREAK -case 27: -YY_RULE_SETUP -#line 53 "lex.l" -return(tSEMI); - YY_BREAK -case 28: -YY_RULE_SETUP -#line 54 "lex.l" -return(tCOMMA); - YY_BREAK -case 29: -YY_RULE_SETUP -#line 56 "lex.l" -{strncpy(yylval.str, yytext, NAME_MAX_LENGTH); return(tID);} - YY_BREAK -case 30: -YY_RULE_SETUP -#line 57 "lex.l" -{yylval.nbInt = atoi(yytext); return(tNB);} - YY_BREAK -case 31: -YY_RULE_SETUP -#line 58 "lex.l" -{yylval.nbInt = atoi(yytext); return(tNB);} - YY_BREAK -/*comments are ignored, same for spaces and lines*/ -case 32: -YY_RULE_SETUP -#line 62 "lex.l" -; - YY_BREAK -case 33: -/* rule 33 can match eol */ -YY_RULE_SETUP -#line 63 "lex.l" -; - YY_BREAK -case 34: -YY_RULE_SETUP -#line 64 "lex.l" -; - YY_BREAK -case 35: -/* rule 35 can match eol */ -YY_RULE_SETUP -#line 65 "lex.l" -; - YY_BREAK -/*anything else is considered an error*/ -case 36: -YY_RULE_SETUP -#line 68 "lex.l" -yyerror(yytext); - YY_BREAK -case 37: -YY_RULE_SETUP -#line 70 "lex.l" -ECHO; - YY_BREAK -#line 970 "lex.yy.c" -case YY_STATE_EOF(INITIAL): - yyterminate(); - - case YY_END_OF_BUFFER: - { - /* Amount of text matched not including the EOB char. */ - int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1; - - /* Undo the effects of YY_DO_BEFORE_ACTION. */ - *yy_cp = (yy_hold_char); - YY_RESTORE_YY_MORE_OFFSET - - if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW ) - { - /* We're scanning a new file or input source. It's - * possible that this happened because the user - * just pointed yyin at a new source and called - * yylex(). If so, then we have to assure - * consistency between YY_CURRENT_BUFFER and our - * globals. Here is the right place to do so, because - * this is the first action (other than possibly a - * back-up) that will match for the new input source. - */ - (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; - YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin; - YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL; - } - - /* Note that here we test for yy_c_buf_p "<=" to the position - * of the first EOB in the buffer, since yy_c_buf_p will - * already have been incremented past the NUL character - * (since all states make transitions on EOB to the - * end-of-buffer state). Contrast this with the test - * in input(). - */ - if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) - { /* This was really a NUL. */ - yy_state_type yy_next_state; - - (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; - - yy_current_state = yy_get_previous_state( ); - - /* Okay, we're now positioned to make the NUL - * transition. We couldn't have - * yy_get_previous_state() go ahead and do it - * for us because it doesn't know how to deal - * with the possibility of jamming (and we don't - * want to build jamming into it because then it - * will run more slowly). - */ - - yy_next_state = yy_try_NUL_trans( yy_current_state ); - - yy_bp = (yytext_ptr) + YY_MORE_ADJ; - - if ( yy_next_state ) - { - /* Consume the NUL. */ - yy_cp = ++(yy_c_buf_p); - yy_current_state = yy_next_state; - goto yy_match; - } - - else - { - yy_cp = (yy_c_buf_p); - goto yy_find_action; - } - } - - else switch ( yy_get_next_buffer( ) ) - { - case EOB_ACT_END_OF_FILE: - { - (yy_did_buffer_switch_on_eof) = 0; - - if ( yywrap( ) ) - { - /* Note: because we've taken care in - * yy_get_next_buffer() to have set up - * yytext, we can now set up - * yy_c_buf_p so that if some total - * hoser (like flex itself) wants to - * call the scanner after we return the - * YY_NULL, it'll still work - another - * YY_NULL will get returned. - */ - (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ; - - yy_act = YY_STATE_EOF(YY_START); - goto do_action; - } - - else - { - if ( ! (yy_did_buffer_switch_on_eof) ) - YY_NEW_FILE; - } - break; - } - - case EOB_ACT_CONTINUE_SCAN: - (yy_c_buf_p) = - (yytext_ptr) + yy_amount_of_matched_text; - - yy_current_state = yy_get_previous_state( ); - - yy_cp = (yy_c_buf_p); - yy_bp = (yytext_ptr) + YY_MORE_ADJ; - goto yy_match; - - case EOB_ACT_LAST_MATCH: - (yy_c_buf_p) = - &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)]; - - yy_current_state = yy_get_previous_state( ); - - yy_cp = (yy_c_buf_p); - yy_bp = (yytext_ptr) + YY_MORE_ADJ; - goto yy_find_action; - } - break; - } - - default: - YY_FATAL_ERROR( - "fatal flex scanner internal error--no action found" ); - } /* end of action switch */ - } /* end of scanning one token */ - } /* end of user's declarations */ -} /* end of yylex */ - -/* yy_get_next_buffer - try to read in a new buffer - * - * Returns a code representing an action: - * EOB_ACT_LAST_MATCH - - * EOB_ACT_CONTINUE_SCAN - continue scanning from current position - * EOB_ACT_END_OF_FILE - end of file - */ -static int yy_get_next_buffer (void) -{ - char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; - char *source = (yytext_ptr); - int number_to_move, i; - int ret_val; - - if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) - YY_FATAL_ERROR( - "fatal flex scanner internal error--end of buffer missed" ); - - if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 ) - { /* Don't try to fill the buffer, so this is an EOF. */ - if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 ) - { - /* We matched a single character, the EOB, so - * treat this as a final EOF. - */ - return EOB_ACT_END_OF_FILE; - } - - else - { - /* We matched some text prior to the EOB, first - * process it. - */ - return EOB_ACT_LAST_MATCH; - } - } - - /* Try to read more data. */ - - /* First move last chars to start of buffer. */ - number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); - - for ( i = 0; i < number_to_move; ++i ) - *(dest++) = *(source++); - - if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING ) - /* don't do the read, it's not guaranteed to return an EOF, - * just force an EOF - */ - YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0; - - else - { - int num_to_read = - YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; - - while ( num_to_read <= 0 ) - { /* Not enough room in the buffer - grow it. */ - - /* just a shorter name for the current buffer */ - YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE; - - int yy_c_buf_p_offset = - (int) ((yy_c_buf_p) - b->yy_ch_buf); - - if ( b->yy_is_our_buffer ) - { - int new_size = b->yy_buf_size * 2; - - if ( new_size <= 0 ) - b->yy_buf_size += b->yy_buf_size / 8; - else - b->yy_buf_size *= 2; - - b->yy_ch_buf = (char *) - /* Include room in for 2 EOB chars. */ - yyrealloc( (void *) b->yy_ch_buf, - (yy_size_t) (b->yy_buf_size + 2) ); - } - else - /* Can't grow it, we don't own it. */ - b->yy_ch_buf = NULL; - - if ( ! b->yy_ch_buf ) - YY_FATAL_ERROR( - "fatal error - scanner input buffer overflow" ); - - (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset]; - - num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - - number_to_move - 1; - - } - - if ( num_to_read > YY_READ_BUF_SIZE ) - num_to_read = YY_READ_BUF_SIZE; - - /* Read in more data. */ - YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), - (yy_n_chars), num_to_read ); - - YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); - } - - if ( (yy_n_chars) == 0 ) - { - if ( number_to_move == YY_MORE_ADJ ) - { - ret_val = EOB_ACT_END_OF_FILE; - yyrestart( yyin ); - } - - else - { - ret_val = EOB_ACT_LAST_MATCH; - YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = - YY_BUFFER_EOF_PENDING; - } - } - - else - ret_val = EOB_ACT_CONTINUE_SCAN; - - if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { - /* Extend the array by 50%, plus the number we really need. */ - int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc( - (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size ); - if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) - YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); - /* "- 2" to take care of EOB's */ - YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2); - } - - (yy_n_chars) += number_to_move; - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR; - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR; - - (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0]; - - return ret_val; -} - -/* yy_get_previous_state - get the state just before the EOB char was reached */ - - static yy_state_type yy_get_previous_state (void) -{ - yy_state_type yy_current_state; - char *yy_cp; - - yy_current_state = (yy_start); - - for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) - { - YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); - if ( yy_accept[yy_current_state] ) - { - (yy_last_accepting_state) = yy_current_state; - (yy_last_accepting_cpos) = yy_cp; - } - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 77 ) - yy_c = yy_meta[yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - } - - return yy_current_state; -} - -/* yy_try_NUL_trans - try to make a transition on the NUL character - * - * synopsis - * next_state = yy_try_NUL_trans( current_state ); - */ - static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) -{ - int yy_is_jam; - char *yy_cp = (yy_c_buf_p); - - YY_CHAR yy_c = 1; - if ( yy_accept[yy_current_state] ) - { - (yy_last_accepting_state) = yy_current_state; - (yy_last_accepting_cpos) = yy_cp; - } - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 77 ) - yy_c = yy_meta[yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 76); - - return yy_is_jam ? 0 : yy_current_state; -} - -#ifndef YY_NO_UNPUT - -#endif - -#ifndef YY_NO_INPUT -#ifdef __cplusplus - static int yyinput (void) -#else - static int input (void) -#endif - -{ - int c; - - *(yy_c_buf_p) = (yy_hold_char); - - if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) - { - /* yy_c_buf_p now points to the character we want to return. - * If this occurs *before* the EOB characters, then it's a - * valid NUL; if not, then we've hit the end of the buffer. - */ - if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) - /* This was really a NUL. */ - *(yy_c_buf_p) = '\0'; - - else - { /* need more input */ - int offset = (int) ((yy_c_buf_p) - (yytext_ptr)); - ++(yy_c_buf_p); - - switch ( yy_get_next_buffer( ) ) - { - case EOB_ACT_LAST_MATCH: - /* This happens because yy_g_n_b() - * sees that we've accumulated a - * token and flags that we need to - * try matching the token before - * proceeding. But for input(), - * there's no matching to consider. - * So convert the EOB_ACT_LAST_MATCH - * to EOB_ACT_END_OF_FILE. - */ - - /* Reset buffer status. */ - yyrestart( yyin ); - - /*FALLTHROUGH*/ - - case EOB_ACT_END_OF_FILE: - { - if ( yywrap( ) ) - return 0; - - if ( ! (yy_did_buffer_switch_on_eof) ) - YY_NEW_FILE; -#ifdef __cplusplus - return yyinput(); -#else - return input(); -#endif - } - - case EOB_ACT_CONTINUE_SCAN: - (yy_c_buf_p) = (yytext_ptr) + offset; - break; - } - } - } - - c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */ - *(yy_c_buf_p) = '\0'; /* preserve yytext */ - (yy_hold_char) = *++(yy_c_buf_p); - - return c; -} -#endif /* ifndef YY_NO_INPUT */ - -/** Immediately switch to a different input stream. - * @param input_file A readable stream. - * - * @note This function does not reset the start condition to @c INITIAL . - */ - void yyrestart (FILE * input_file ) -{ - - if ( ! YY_CURRENT_BUFFER ){ - yyensure_buffer_stack (); - YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer( yyin, YY_BUF_SIZE ); - } - - yy_init_buffer( YY_CURRENT_BUFFER, input_file ); - yy_load_buffer_state( ); -} - -/** Switch to a different input buffer. - * @param new_buffer The new input buffer. - * - */ - void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) -{ - - /* TODO. We should be able to replace this entire function body - * with - * yypop_buffer_state(); - * yypush_buffer_state(new_buffer); - */ - yyensure_buffer_stack (); - if ( YY_CURRENT_BUFFER == new_buffer ) - return; - - if ( YY_CURRENT_BUFFER ) - { - /* Flush out information for old buffer. */ - *(yy_c_buf_p) = (yy_hold_char); - YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); - YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); - } - - YY_CURRENT_BUFFER_LVALUE = new_buffer; - yy_load_buffer_state( ); - - /* We don't actually know whether we did this switch during - * EOF (yywrap()) processing, but the only time this flag - * is looked at is after yywrap() is called, so it's safe - * to go ahead and always set it. - */ - (yy_did_buffer_switch_on_eof) = 1; -} - -static void yy_load_buffer_state (void) -{ - (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; - (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos; - yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file; - (yy_hold_char) = *(yy_c_buf_p); -} - -/** Allocate and initialize an input buffer state. - * @param file A readable stream. - * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. - * - * @return the allocated buffer state. - */ - YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) -{ - YY_BUFFER_STATE b; - - b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); - if ( ! b ) - YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); - - b->yy_buf_size = size; - - /* yy_ch_buf has to be 2 characters longer than the size given because - * we need to put in 2 end-of-buffer characters. - */ - b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) ); - if ( ! b->yy_ch_buf ) - YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); - - b->yy_is_our_buffer = 1; - - yy_init_buffer( b, file ); - - return b; -} - -/** Destroy the buffer. - * @param b a buffer created with yy_create_buffer() - * - */ - void yy_delete_buffer (YY_BUFFER_STATE b ) -{ - - if ( ! b ) - return; - - if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */ - YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; - - if ( b->yy_is_our_buffer ) - yyfree( (void *) b->yy_ch_buf ); - - yyfree( (void *) b ); -} - -/* Initializes or reinitializes a buffer. - * This function is sometimes called more than once on the same buffer, - * such as during a yyrestart() or at EOF. - */ - static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file ) - -{ - int oerrno = errno; - - yy_flush_buffer( b ); - - b->yy_input_file = file; - b->yy_fill_buffer = 1; - - /* If b is the current buffer, then yy_init_buffer was _probably_ - * called from yyrestart() or through yy_get_next_buffer. - * In that case, we don't want to reset the lineno or column. - */ - if (b != YY_CURRENT_BUFFER){ - b->yy_bs_lineno = 1; - b->yy_bs_column = 0; - } - - b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0; - - errno = oerrno; -} - -/** Discard all buffered characters. On the next scan, YY_INPUT will be called. - * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. - * - */ - void yy_flush_buffer (YY_BUFFER_STATE b ) -{ - if ( ! b ) - return; - - b->yy_n_chars = 0; - - /* We always need two end-of-buffer characters. The first causes - * a transition to the end-of-buffer state. The second causes - * a jam in that state. - */ - b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR; - b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR; - - b->yy_buf_pos = &b->yy_ch_buf[0]; - - b->yy_at_bol = 1; - b->yy_buffer_status = YY_BUFFER_NEW; - - if ( b == YY_CURRENT_BUFFER ) - yy_load_buffer_state( ); -} - -/** Pushes the new state onto the stack. The new state becomes - * the current state. This function will allocate the stack - * if necessary. - * @param new_buffer The new state. - * - */ -void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) -{ - if (new_buffer == NULL) - return; - - yyensure_buffer_stack(); - - /* This block is copied from yy_switch_to_buffer. */ - if ( YY_CURRENT_BUFFER ) - { - /* Flush out information for old buffer. */ - *(yy_c_buf_p) = (yy_hold_char); - YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); - YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); - } - - /* Only push if top exists. Otherwise, replace top. */ - if (YY_CURRENT_BUFFER) - (yy_buffer_stack_top)++; - YY_CURRENT_BUFFER_LVALUE = new_buffer; - - /* copied from yy_switch_to_buffer. */ - yy_load_buffer_state( ); - (yy_did_buffer_switch_on_eof) = 1; -} - -/** Removes and deletes the top of the stack, if present. - * The next element becomes the new top. - * - */ -void yypop_buffer_state (void) -{ - if (!YY_CURRENT_BUFFER) - return; - - yy_delete_buffer(YY_CURRENT_BUFFER ); - YY_CURRENT_BUFFER_LVALUE = NULL; - if ((yy_buffer_stack_top) > 0) - --(yy_buffer_stack_top); - - if (YY_CURRENT_BUFFER) { - yy_load_buffer_state( ); - (yy_did_buffer_switch_on_eof) = 1; - } -} - -/* Allocates the stack if it does not exist. - * Guarantees space for at least one push. - */ -static void yyensure_buffer_stack (void) -{ - yy_size_t num_to_alloc; - - if (!(yy_buffer_stack)) { - - /* First allocation is just for 2 elements, since we don't know if this - * scanner will even need a stack. We use 2 instead of 1 to avoid an - * immediate realloc on the next call. - */ - num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ - (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc - (num_to_alloc * sizeof(struct yy_buffer_state*) - ); - if ( ! (yy_buffer_stack) ) - YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); - - memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); - - (yy_buffer_stack_max) = num_to_alloc; - (yy_buffer_stack_top) = 0; - return; - } - - if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ - - /* Increase the buffer to prepare for a possible push. */ - yy_size_t grow_size = 8 /* arbitrary grow size */; - - num_to_alloc = (yy_buffer_stack_max) + grow_size; - (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc - ((yy_buffer_stack), - num_to_alloc * sizeof(struct yy_buffer_state*) - ); - if ( ! (yy_buffer_stack) ) - YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); - - /* zero only the new slots.*/ - memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*)); - (yy_buffer_stack_max) = num_to_alloc; - } -} - -/** Setup the input buffer state to scan directly from a user-specified character buffer. - * @param base the character buffer - * @param size the size in bytes of the character buffer - * - * @return the newly allocated buffer state object. - */ -YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) -{ - YY_BUFFER_STATE b; - - if ( size < 2 || - base[size-2] != YY_END_OF_BUFFER_CHAR || - base[size-1] != YY_END_OF_BUFFER_CHAR ) - /* They forgot to leave room for the EOB's. */ - return NULL; - - b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); - if ( ! b ) - YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); - - b->yy_buf_size = (int) (size - 2); /* "- 2" to take care of EOB's */ - b->yy_buf_pos = b->yy_ch_buf = base; - b->yy_is_our_buffer = 0; - b->yy_input_file = NULL; - b->yy_n_chars = b->yy_buf_size; - b->yy_is_interactive = 0; - b->yy_at_bol = 1; - b->yy_fill_buffer = 0; - b->yy_buffer_status = YY_BUFFER_NEW; - - yy_switch_to_buffer( b ); - - return b; -} - -/** Setup the input buffer state to scan a string. The next call to yylex() will - * scan from a @e copy of @a str. - * @param yystr a NUL-terminated string to scan - * - * @return the newly allocated buffer state object. - * @note If you want to scan bytes that may contain NUL values, then use - * yy_scan_bytes() instead. - */ -YY_BUFFER_STATE yy_scan_string (const char * yystr ) -{ - - return yy_scan_bytes( yystr, (int) strlen(yystr) ); -} - -/** Setup the input buffer state to scan the given bytes. The next call to yylex() will - * scan from a @e copy of @a bytes. - * @param yybytes the byte buffer to scan - * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. - * - * @return the newly allocated buffer state object. - */ -YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) -{ - YY_BUFFER_STATE b; - char *buf; - yy_size_t n; - int i; - - /* Get memory for full buffer, including space for trailing EOB's. */ - n = (yy_size_t) (_yybytes_len + 2); - buf = (char *) yyalloc( n ); - if ( ! buf ) - YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); - - for ( i = 0; i < _yybytes_len; ++i ) - buf[i] = yybytes[i]; - - buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; - - b = yy_scan_buffer( buf, n ); - if ( ! b ) - YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); - - /* It's okay to grow etc. this buffer, and we should throw it - * away when we're done. - */ - b->yy_is_our_buffer = 1; - - return b; -} - -#ifndef YY_EXIT_FAILURE -#define YY_EXIT_FAILURE 2 -#endif - -static void yynoreturn yy_fatal_error (const char* msg ) -{ - fprintf( stderr, "%s\n", msg ); - exit( YY_EXIT_FAILURE ); -} - -/* Redefine yyless() so it works in section 3 code. */ - -#undef yyless -#define yyless(n) \ - do \ - { \ - /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ - YY_LESS_LINENO(yyless_macro_arg);\ - yytext[yyleng] = (yy_hold_char); \ - (yy_c_buf_p) = yytext + yyless_macro_arg; \ - (yy_hold_char) = *(yy_c_buf_p); \ - *(yy_c_buf_p) = '\0'; \ - yyleng = yyless_macro_arg; \ - } \ - while ( 0 ) - -/* Accessor methods (get/set functions) to struct members. */ - -/** Get the current line number. - * - */ -int yyget_lineno (void) -{ - - return yylineno; -} - -/** Get the input stream. - * - */ -FILE *yyget_in (void) -{ - return yyin; -} - -/** Get the output stream. - * - */ -FILE *yyget_out (void) -{ - return yyout; -} - -/** Get the length of the current token. - * - */ -int yyget_leng (void) -{ - return yyleng; -} - -/** Get the current token. - * - */ - -char *yyget_text (void) -{ - return yytext; -} - -/** Set the current line number. - * @param _line_number line number - * - */ -void yyset_lineno (int _line_number ) -{ - - yylineno = _line_number; -} - -/** Set the input stream. This does not discard the current - * input buffer. - * @param _in_str A readable stream. - * - * @see yy_switch_to_buffer - */ -void yyset_in (FILE * _in_str ) -{ - yyin = _in_str ; -} - -void yyset_out (FILE * _out_str ) -{ - yyout = _out_str ; -} - -int yyget_debug (void) -{ - return yy_flex_debug; -} - -void yyset_debug (int _bdebug ) -{ - yy_flex_debug = _bdebug ; -} - -static int yy_init_globals (void) -{ - /* Initialization is the same as for the non-reentrant scanner. - * This function is called from yylex_destroy(), so don't allocate here. - */ - - (yy_buffer_stack) = NULL; - (yy_buffer_stack_top) = 0; - (yy_buffer_stack_max) = 0; - (yy_c_buf_p) = NULL; - (yy_init) = 0; - (yy_start) = 0; - -/* Defined in main.c */ -#ifdef YY_STDINIT - yyin = stdin; - yyout = stdout; -#else - yyin = NULL; - yyout = NULL; -#endif - - /* For future reference: Set errno on error, since we are called by - * yylex_init() - */ - return 0; -} - -/* yylex_destroy is for both reentrant and non-reentrant scanners. */ -int yylex_destroy (void) -{ - - /* Pop the buffer stack, destroying each element. */ - while(YY_CURRENT_BUFFER){ - yy_delete_buffer( YY_CURRENT_BUFFER ); - YY_CURRENT_BUFFER_LVALUE = NULL; - yypop_buffer_state(); - } - - /* Destroy the stack itself. */ - yyfree((yy_buffer_stack) ); - (yy_buffer_stack) = NULL; - - /* Reset the globals. This is important in a non-reentrant scanner so the next time - * yylex() is called, initialization will occur. */ - yy_init_globals( ); - - return 0; -} - -/* - * Internal utility routines. - */ - -#ifndef yytext_ptr -static void yy_flex_strncpy (char* s1, const char * s2, int n ) -{ - - int i; - for ( i = 0; i < n; ++i ) - s1[i] = s2[i]; -} -#endif - -#ifdef YY_NEED_STRLEN -static int yy_flex_strlen (const char * s ) -{ - int n; - for ( n = 0; s[n]; ++n ) - ; - - return n; -} -#endif - -void *yyalloc (yy_size_t size ) -{ - return malloc(size); -} - -void *yyrealloc (void * ptr, yy_size_t size ) -{ - - /* The cast to (char *) in the following accommodates both - * implementations that use char* generic pointers, and those - * that use void* generic pointers. It works with the latter - * because both ANSI C and C++ allow castless assignment from - * any pointer type to void*, and deal with argument conversions - * as though doing an assignment. - */ - return realloc(ptr, size); -} - -void yyfree (void * ptr ) -{ - free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ -} - -#define YYTABLES_NAME "yytables" - -#line 70 "lex.l" - - - // SI >> SC - diff --git a/lex.yy.o b/lex.yy.o deleted file mode 100644 index c56851d..0000000 Binary files a/lex.yy.o and /dev/null differ diff --git a/linkedList.c b/linkedList.c deleted file mode 100644 index 6933363..0000000 --- a/linkedList.c +++ /dev/null @@ -1,109 +0,0 @@ - -#include "LinkedList.h" -#include "table.h" - -/*Add element in linked lis*/ -llist addElementLinkedList(char *label, int numLine){ - element* newElement = malloc(sizeof(element)); - strcpy(newElement->val, label); - newElement->numLine = numLine; - newElement->nxt = NULL; - - if (list == NULL) { - return newElement; - } - else { - element* temp=list; - while (temp->nxt != NULL) { - temp = temp->nxt; - } - temp->nxt = newElement; - return list; - } -} - -/* Find the numero of the lines with a specific label*/ -int findLineElement(char *label){ - element *tmp=list; - while (tmp != NULL){ - if (strcmp(tmp->val, label)){ - return tmp->numLine; - } - tmp = tmp->nxt; - } - error("Label doesn't exist"); - return NULL; -} -// TODO : ne pas incrementer les lignes avec LABEL - -/* Count Lines and suppress Label */ -void countLines(char *s){ - FILE *fptr; - char * line = NULL; - size_t len = 0; - ssize_t read; - fptr = fopen(s, "r"); - FILE* fOut; - fOut = fopen("asm2", "a"); - - if(fptr == NULL) { - error("Empty file."); - } - - while ((read = getline(&line, &len, fptr)) != -1) { - if (IsInt(line[0])){ - char label[LABEL_SIZE]; - sprintf(label, "%d_LABEL", numberLines); - addElementLinkedList(label, numberLines); - } - else { - fputs(line, fOut); - numberLines ++; - } - printf("%s", line); - } - fclose(fptr); - fclose(fOut); -} - -/* Replace label */ - -bool IsInt(char c){ - for(int i = 0; i < 10; i ++){ - if (c == i){ - return true; - } - } - return false; -} - -void detectLabel(char* s){ - char label[LABEL_SIZE]; - char numLabel[2]; - if (s[0] == 'J'){ - if (s[1] == 'M'){ - int i = 4; - while (s[i] != '_'){ - sprintf(numLabel, "%d", s[i]); - strcat(label, numLabel); - fputs(line, fp); // ajout de ce qu'il y a avant - i++; - } - } - else { - int i = 4 ; - while (s[i] != ' '){ - NULL; - i ++; - } i ++; - while (s[i] != '_'){ - sprintf(numLabel, "%d", s[i]); - strcat(label, numLabel); - fputs(line, fp); // ajout de ce qu'il y a avant - i++; - } - } - // ajout dans le table - } -} //JMP 12_LABEL -//JMF @cdcjdjk 12_LABEL \ No newline at end of file diff --git a/operations.c b/operations.c deleted file mode 100644 index 0a2de43..0000000 --- a/operations.c +++ /dev/null @@ -1,168 +0,0 @@ -// -// Created by chepycou on 4/14/23. -// - -#include -#include "table.h" -#include "operations.h" -#include "asmTable.h" - -/*prints to the stdout and the out asm file*/ -void printOp(char* s){ - //printf("%s",s); - addLine(s); - - /*FILE* fp; - fp = fopen("asm", "a"); - fputs(s, fp); - fclose(fp);*/ -} - -/*clears the out asm file*/ -void clearOp(){ - FILE* fp; - fp = fopen("asm", "w"); - fclose(fp); -} - -/*prints the ASM instruction for the addition computation - * and returns the address of the temporary variable*/ -int operation_add(int addr1, int addr2){ - int addr = addTempINTAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "ADD %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the subtraction computation - * and returns the address of the temporary variable*/ -int operation_sub(int addr1, int addr2){ - int addr = addTempINTAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "SUB %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the multiplication computation - * and returns the address of the temporary variable*/ -int operation_mul(int addr1, int addr2){ - int addr = addTempINTAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "MUL %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the integer division computation - * and returns the address of the temporary variable*/ -int operation_divInt(int addr1, int addr2){ - int addr = addTempINTAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "DIV_INT %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the remainder computation - * and returns the address of the temporary variable*/ -int operation_divRem(int addr1, int addr2){ - int addr = addTempINTAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "DIV_REM %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the affection of a variable - * EX : - * a = 2; - */ -void operation_afc_nb(int addr, int value){ - char s[ASM_TEXT_LEN]; - sprintf(s, "AFC %d %d", addr, value); - printOp(s); -} - -/*prints the ASM instruction for the affection of a temporary variable - * EX : - * "1_TEMP = 2" - * and returns the address of the temp variable*/ -int operation_afc_nb_tmp(int value){ - int addr = addTempINTAndGetAddress(); - operation_afc_nb(addr, value); - return addr; -} - - -/*prints the ASM instruction for the affection of a temporary variable - * EX : - * a = b; - */ -void operation_copy(int addr1, int addr2){ - char s[ASM_TEXT_LEN]; - sprintf(s, "COP %d %d", addr1, addr2); - printOp(s); -} - -/*prints the ASM instruction for the inferior condition - * and returns the address of the temporary variable*/ -int cond_inf(int addr1, int addr2){ - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "INF %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the superior condition - * and returns the address of the temporary variable*/ -int cond_sup(int addr1, int addr2){ - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "SUP %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the equality condition - * and returns the address of the temporary variable*/ -int cond_eq(int addr1, int addr2) { - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "EQ %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the negation condition - * and returns the address of the temporary variable*/ -int cond_not(int addr1){ - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "NOT %d %d", addr, addr1); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the and condition - * and returns the address of the temporary variable*/ -int cond_and(int addr1, int addr2){ - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "AND %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - -/*prints the ASM instruction for the or condition - * and returns the address of the temporary variable*/ -int cond_or(int addr1, int addr2){ - int addr = addTempCONDAndGetAddress(); - char s[ASM_TEXT_LEN]; - sprintf(s, "OR %d %d %d", addr, addr1, addr2); - printOp(s); - return addr; -} - diff --git a/operations.h b/operations.h deleted file mode 100644 index c525bc2..0000000 --- a/operations.h +++ /dev/null @@ -1,78 +0,0 @@ -// -// Created by chepycou on 4/14/23. -// - -#ifndef PROJET_SYSTEMES_INFORMATIQUES_OPERATIONS_H -#define PROJET_SYSTEMES_INFORMATIQUES_OPERATIONS_H - -#define ASM_TEXT_LEN 40 - -/*clears the out asm file*/ -void clearOp(); - -/*prints to the stdout and the out asm file*/ -void printOp(char* s); - -/*prints the ASM instruction for the addition computation - * and returns the address of the temporary variable*/ -int operation_add(int addr1, int addr2); - -/*prints the ASM instruction for the subtraction computation - * and returns the address of the temporary variable*/ -int operation_sub(int addr1, int addr2); - -/*prints the ASM instruction for the multiplication computation - * and returns the address of the temporary variable*/ -int operation_mul(int addr1, int addr2); - -/*prints the ASM instruction for the integer division computation - * and returns the address of the temporary variable*/ -int operation_divInt(int addr1, int addr2); - -/*prints the ASM instruction for the remainder computation - * and returns the address of the temporary variable*/ -int operation_divRem(int addr1, int addr2); - -/*prints the ASM instruction for the affection of a variable - * EX : - * a = 2; - */ -void operation_afc_nb(int addr, int value); - -/*prints the ASM instruction for the affection of a temporary variable - * EX : - * "1_TEMP = 2" - * and returns the address of the temp variable*/ -int operation_afc_nb_tmp(int value); - -/*prints the ASM instruction for the affection of a temporary variable - * EX : - * a = b; - */ -void operation_copy(int addr1, int addr2); - -/*prints the ASM instruction for the inferior condition - * and returns the address of the temporary variable*/ -int cond_inf(int addr1, int addr2); - -/*prints the ASM instruction for the superior condition - * and returns the address of the temporary variable*/ -int cond_sup(int addr1, int addr2); - -/*prints the ASM instruction for the equality condition - * and returns the address of the temporary variable*/ -int cond_eq(int addr1, int addr2); - -/*prints the ASM instruction for the negation condition - * and returns the address of the temporary variable*/ -int cond_not(int addr1); - -/*prints the ASM instruction for the and condition - * and returns the address of the temporary variable*/ -int cond_and(int addr1, int addr2); - -/*prints the ASM instruction for the or condition - * and returns the address of the temporary variable*/ -int cond_or(int addr1, int addr2); - -#endif //PROJET_SYSTEMES_INFORMATIQUES_OPERATIONS_H diff --git a/operations.o b/operations.o deleted file mode 100644 index 78ea436..0000000 Binary files a/operations.o and /dev/null differ diff --git a/post-process.py b/post-process.py deleted file mode 100644 index d724fa1..0000000 --- a/post-process.py +++ /dev/null @@ -1,182 +0,0 @@ -import re - -opToBinOP = { - "ADD": "01", - "MUL": "02", - "SUB": "03", - "DIV": "04", - "COP": "05", - "AFC": "06", - "LOAD": "07", - "STORE": "08", - "INF": "09", - "SUP": "0A", - "EQ": "0B", - "NOT": "0C", - "AND": "0D", - "OR": "0E", - "JMP": "0F", - "JMF": "10", - "CAL": "11", - "RET": "12", - "PRI": "13", - "NOP": "FF" -} - - -def output(s, num, oneline=False): - fileOutput = open(f'asm{num}', 'w') - if oneline: - fileOutput.write(s) - else : - fileOutput.write("\n".join(s)) - fileOutput.close() - - -def convertToRegister(s): - l = [] - - if not re.match(r"\d_LABEL", s[0]): - optionalFlag = "" - incr = 0 - op = s[0] - else: - optionalFlag = s[0] + " " - incr = 1 - op = s[1] - - match op: - case "ADD": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("ADD 0 0 1") - l.append("STORE " + s[1 + incr] + " 0") - case "MUL": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("MUL 0 0 1") - l.append("STORE " + s[1 + incr] + " 0") - case "SUB": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("SUB 0 0 1") - l.append("STORE " + s[1 + incr] + " 0") - case "DIV_INT": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("DIV 0 0 1") - l.append("STORE " + s[1 + incr] + " 0") - case "COP": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("STORE " + s[1 + incr] + " 0") - case "AFC": - l.append(optionalFlag + "AFC 0 " + s[2 + incr]) - l.append("STORE " + s[1 + incr] + " 0") - case "JMP": - l.append(" ".join(s)) - case "JMF": - if len(s) == 3: - l.append(" ".join(s)) - else : - l.append(s[0]+ " 0 " + s[1]) - case "INF": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("INF 2 0 1") - l.append("STORE " + s[1 + incr] + " 2") - case "SUP": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("SUP 2 1 0") - l.append("STORE " + s[1 + incr] + " 2") - case "EQ": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("EQ 2 1 0") - l.append("STORE " + s[1 + incr] + " 2") - case "PRI": - l.append(optionalFlag + "PRI " + s[2 + incr]) - case "AND": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("AND 2 0 1") - l.append("STORE " + s[1 + incr] + " 2") - case "OR": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("LOAD 1 " + s[3 + incr]) - l.append("OR 2 0 1") - l.append("STORE " + s[1 + incr] + " 2") - case "NOT": - l.append(optionalFlag + "LOAD 0 " + s[2 + incr]) - l.append("NOT 2 0") - l.append("STORE " + s[1 + incr] + " 2") - case default: - l.append(" ".join(s)) - - """ R2 will contain the information whether to jump or not""" - - return l - - -totalLine = 0 -labelCount = 0 # used to create a new label each time - -fileInput = open("asm", "r") -ASMLines = list(map(lambda e: e.rstrip("\n"), fileInput.readlines())) -fileInput.close() - -# added to prevent problems when cross compiling some code representing a jump to after the last line -ASMLines.append("NOP") - -ASMLinesLabel = ASMLines[:] # will contain at the end of the first loop the code with labels inserted -ASMLinesRegister = [] # will contain at the end of the 2nd loop the registry-based code with labels -ASMLinesFinal = [] # will contain the output, register-based, code - -for i, l in enumerate(ASMLines): - items = l.split(" ") - if items[0] in ["JMP", "JMF"]: - lineToJumpTo = int(items[-1]) - if re.match(r"\d_LABEL .*", ASMLinesLabel[lineToJumpTo]): - ASMLinesLabel[i] = " ".join(ASMLines[i].split()[:-1] + [ASMLinesLabel[lineToJumpTo].split()[0]]) - else: - ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo] - ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"]) - labelCount += 1 -print("labels : ", ASMLinesLabel) - -for i, l in enumerate(ASMLinesLabel): - ASMLinesRegister.extend(convertToRegister(l.split())) -print("regs : ", ASMLinesRegister) - -labels = {} -for i, l in enumerate(ASMLinesRegister): - if re.match(r"\d_LABEL .*", l): - labels[l.split()[0]] = i - ASMLinesRegister[i] = " ".join(ASMLinesRegister[i].split()[1:]) -print(ASMLinesRegister) - -for i, l in enumerate(ASMLinesRegister): - label = re.match(r"\d_LABEL", l.split()[-1]) - if label: - ASMLinesFinal.append(" ".join(l.split()[:-1] + [str(labels[label[0]])])) - else: - ASMLinesFinal.append(l) - -print(ASMLinesFinal) -output(ASMLinesFinal, 2) - -lines = [] -for i, l in enumerate(ASMLinesFinal): - arr = l.split() - while len(arr) < 4: - arr.append(0) - lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")") -ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\"))" -print("converted to VHDL-friendly format : " + ASMLinesConverted) -output(ASMLinesConverted, 3, True) - - -""" Used to generate the beautiful table in the report -for i in range(10): - print(f"{ASMLines[i]} & {ASMLinesFinal[i]} & {ASMLinesConverted.split(',')[i]} \\\\") -""" diff --git a/style.css b/style.css deleted file mode 100644 index 0eb8a07..0000000 --- a/style.css +++ /dev/null @@ -1,7 +0,0 @@ - -#code { - overflow: auto scroll; - text-align: center; - padding-top: 3; - width: 100%; -} \ No newline at end of file diff --git a/table.c b/table.c deleted file mode 100644 index 1358d85..0000000 --- a/table.c +++ /dev/null @@ -1,308 +0,0 @@ -#include -#include -#include "table.h" - -#define VERBOSITY 0 // 1 -> displays the table, 0 no display - -int memorySizes[2] = {1,1}; -int tempCounter = 0; -int condCounter = 0; // to store whether there is a conditional variable - -/*At the start of the execution : the whole array is empty*/ -static Symbol* symbolTable; - -/*indexes in the array*/ -static int currentIndex = 0; // the next to index to be used -static int maxIndex = START_TABLE_SIZE; - -// stack pointers -static int esp = 0; -static int ebp = 0; - -static int currentDepth = 0; - -/* /!\ To be called at the beginning - * Initializes the array of Symbols*/ -void initSymbolTable(){ - symbolTable = malloc(sizeof(Symbol) * START_TABLE_SIZE); -} - -/*resets the symbol table*/ -void resetSymboltable(){ - currentIndex = 0; - maxIndex = START_TABLE_SIZE; - -// stack pointers - esp = 0; - ebp = 0; - - currentDepth = 0; -} - - -/* Error display */ -void error(char* mess){ - printf("ERROR : %s\n", mess); - exit(-1); -} - -/* Returns the offset from EBP to the symbol in the stack */ -int getOffset(char* name){ - return (ebp + getStruct(name).offset); -} - -/* Returns the structure with this name */ -Symbol getStruct(char* name){ - for(int i=0; i < currentIndex; i++){ - if (strcmp(symbolTable[i].name, name) == 0){ - return symbolTable[i]; - } - } - if (VERBOSITY) { - printf("\n\n%s not found \n\n", name); - displayTable(); - } - error("No structure found"); - return (createNewStructure("error", 0)); -} - -/* Returns the index with this name*/ -int getIndex(char* name){ - for(int i=0; i < currentIndex; i++){ - if (strcmp(symbolTable[i].name, name) == 0){ - return i; - } - } - printf("%s",name); - error("No index found"); - return (0); -} - -/* removes all symbols associated with the current Depth*/ -void clearOutOfScopeVariable(){ - int i = 0; - int memoryFreed = 0; - - // we get to the first symbol that we need to remove - while(i < currentIndex) { - if (symbolTable[i].depth == currentDepth) { - break; - } - i++; - } - - int futureCurrentIndex = i; - - while(i < currentIndex) { - memoryFreed += memorySizes[symbolTable[i].varType]; - i++; - } - - // now we remove all the symbols - currentIndex = futureCurrentIndex; - checkArraySanity(); - - // and we free their memory (i.e. decrease esp) - esp -= memoryFreed; - - if (VERBOSITY) { - printf("\n\nclearOutOfScopeVariable::After"); - displayTable(); - } -} - - -/* sets the init state of the symbol to true */ -void setInit(char *name){ - symbolTable[getIndex(name)].init = true; - - if (VERBOSITY) { - printf("\n\nsetInit %s", name); - displayTable(); - } -} - -/*creates a new structure and updates variables*/ -Symbol createNewStructure(char* name, enumVarType type){ - Symbol s; - strcpy(s.name,name); - s.init = false; - s.varType = type; - s.offset = esp; // the offset is the current esp - s.depth = currentDepth; - return s; -} - - -/* Adds an element */ -void addElement(char* name, enumVarType type){ - - Symbol element = createNewStructure(name, type); - - //checks for overflow - checkArraySanity(); - - symbolTable[currentIndex] = element; - currentIndex ++; - - esp += memorySizes[type]; - - if (VERBOSITY) { - printf("\n\nAddElement %s", name); - displayTable(); - } -} - -/* Adds an element and returns the offset of it */ -int addElementAndGetAddress(char* name, enumVarType type){ - addElement(name,type); - return getOffset(name); -} - -/* Adds a temporary Int element and returns the offset of it */ -int addTempINTAndGetAddress(){ - char name[NAME_MAX_LENGTH]; - if (tempCounter == 0){ - // we create the first temporary variable and use it - addElement("0_TEMP_INT",INT); - strcpy(name, "0_TEMP_INT"); - } else if (tempCounter == 1) { - // we create the second temporary variable and use it - addElement("1_TEMP_INT",INT); - strcpy(name, "1_TEMP_INT"); - } else { - // we use the right temporary variable - sprintf(name, "%d_TEMP_INT", tempCounter % 2); - } - tempCounter++; - return getOffset(name); -} - -/* removes all symbols */ -void flushSymbolTable(){ - currentIndex = 0; - checkArraySanity(); - if (VERBOSITY) { - printf("\n\nflushSymbolTable::After"); - displayTable(); - } -} - - -/*Checks for the length of the array and reallocates if necessary*/ -void checkArraySanity(){ - if (currentIndex == maxIndex){ - reallocateArray(maxIndex * 2); - } else { - if (currentIndex < maxIndex / 2 && maxIndex / 2 > START_TABLE_SIZE){ - reallocateArray(maxIndex / 2); - } - } -} - -/*reallocates the array with the specified size*/ -void reallocateArray(int size){ - Symbol *temp = (Symbol *)realloc(symbolTable, (sizeof(Symbol) * size)); - - if (temp != NULL){ - symbolTable = temp; - } - else { - error("Cannot allocate more memory.\n"); - } -} - - -/*increases the depth (i.e. when entering a block)*/ -void increaseDepth(){ - currentDepth++; -} - -/*decreases the depth (i.e. when leaving a block)*/ -void decreaseDepth(){ - clearOutOfScopeVariable(); - currentDepth--; -} - -/*displays the entire table at this moment including all information - * regarding the symbols and the current depth*/ -void displayTable(){ - printf("\n"); - doubleLine(); - printf("Table of Symbols, depth = %d, length = %d, ESP = %d, EBP = %d\n", currentDepth, currentIndex, esp ,ebp); - printf("Name | init?, varType, offset, depth\n"); - doubleLine(); - for (int i = 0; i < currentIndex; ++i) { - Symbol a = symbolTable[i]; - printf("%s | %d, %d, %d, %d\n", a.name, a.init, a.varType, a.offset, a.depth); - if (i != currentIndex -1) { - line(); - } - } - doubleLine(); -} - -/*removes all temporary variables used for INTs*/ -void suppressTempINTElements(){ - if (tempCounter == 1){ - suppressElement("0_TEMP_INT"); - esp--; - } else { - if (tempCounter > 1){ - suppressElement("0_TEMP_INT"); - suppressElement("1_TEMP_INT"); - esp-= 2; - } - } - tempCounter = 0; -} - -/*removes one element*/ -void suppressElement(char* name){ - for(int i = getIndex(name); i < (currentIndex - 1); i ++){ - symbolTable[i] = symbolTable[i+1]; - } - currentIndex--; - checkArraySanity(); -} - -void line(){ - printf("---------------------------------\n"); -} -void doubleLine(){ - printf("============================================================\n"); -} - -/*removes all temporary variables used for CONDITIONS*/ -void suppressCONDElements(){ - if (condCounter == 1){ - suppressElement("0_TEMP_COND"); - esp--; - } else { - if (condCounter > 1){ - suppressElement("0_TEMP_COND"); - suppressElement("1_TEMP_COND"); - esp-= 2; - } - } - condCounter = 0; -} - -/* Adds a temporary Conditional element and returns the offset of it */ -int addTempCONDAndGetAddress(){ - char name[NAME_MAX_LENGTH]; - if (condCounter == 0){ - // we create the first temporary variable and use it - addElement("0_TEMP_COND",INT); - strcpy(name, "0_TEMP_COND"); - } else if (condCounter == 1) { - // we create the second temporary variable and use it - addElement("1_TEMP_COND",INT); - strcpy(name, "1_TEMP_COND"); - } else { - // we use the right temporary variable - sprintf(name, "%d_TEMP_COND", condCounter % 2); - } - condCounter++; - return getOffset(name); -} diff --git a/table.h b/table.h deleted file mode 100644 index 6bc27c6..0000000 --- a/table.h +++ /dev/null @@ -1,125 +0,0 @@ -#ifndef TABLE_H -#define TABLE_H - -#include -#include - -/*defined constants*/ -#define START_TABLE_SIZE 128 -#define NAME_MAX_LENGTH 30 - -// a list of all type -typedef enum enumVarType {INT, FLOAT} enumVarType; - -// a list of all type's sizes -extern int memorySizes[2]; - -typedef struct { - char name[NAME_MAX_LENGTH]; - bool init; - enumVarType varType; - int offset; - int depth; -} Symbol; - -/*============================ - Array and Reallocation - ============================*/ - -/*reallocates the array with the specified size*/ -void reallocateArray(int size); - -/*Checks for the length of the array and reallocates if necessary*/ -void checkArraySanity(); - -/* /!\ To be called at the beginning - * Initializes the array of Symbols*/ -void initSymbolTable(); - -/*resets the symbol table*/ -void resetSymboltable(); - -/*inserts an asm code line at the current index*/ -void addLine(char* s); - -/*returns the current line (i.e. next one to insert)*/ -int getCurrentLineNumber(); - -/*============================ - Element Management - ============================*/ - -/* removes all symbols associated with the current Depth*/ -void clearOutOfScopeVariable(); - -/* removes all symbols */ -void flushSymbolTable(); - -/* Adds an element */ -void addElement(char* name, enumVarType type); - -/* Adds an element and returns the offset of it */ -int addElementAndGetAddress(char* name, enumVarType type); - -/* Adds a temporary Int element and returns the offset of it */ -int addTempINTAndGetAddress(); - -/* Adds a temporary Conditional element and returns the offset of it */ -int addTempCONDAndGetAddress(); - -/*creates a new structure and updates variables*/ -Symbol createNewStructure(char* name, enumVarType type); - -/*============================ - Element Edition - ============================*/ - -/* sets the init state of the symbol to true */ -void setInit(char *name); - -/*removes one element*/ -void suppressElement(char* name); - -/*removes all temporary variables used for INTs*/ -void suppressTempINTElements(); - -/*removes all temporary variables used for CONDITIONS*/ -void suppressCONDElements(); - -/*============================ - Element Access - ============================*/ - -/* Returns the index with this name*/ -int getIndex(char* name); - -/* Returns the structure with this name */ -Symbol getStruct(char* name); - -/* Returns the offset from EBP to the symbol in the stack */ -int getOffset(char* name); - - -/*========================== - Flow/Block control - =========================*/ - -/*increases the depth (i.e. when entering a block)*/ -void increaseDepth(); - -/*decreases the depth (i.e. when leaving a block)*/ -void decreaseDepth(); - -/*============================================ - Display, Todo : put in another .h file - ============================================*/ - -void error(char* mess); -void line(); -void doubleLine(); - -/*displays the entire table at this moment including all information - * regarding the symbols and the current depth*/ -void displayTable(); - -#endif diff --git a/table.o b/table.o deleted file mode 100644 index d3ec6b8..0000000 Binary files a/table.o and /dev/null differ diff --git a/testFile_fibo b/testFile_fibo deleted file mode 100644 index b79b1bd..0000000 --- a/testFile_fibo +++ /dev/null @@ -1,20 +0,0 @@ -int main() { - int i, n, nextTerm, t1, t2; - - i = 0; - n = 20; // put here the number you want ! - - t1 = 0; - t2 = 1; - - nextTerm = t1 + t2; - - n = n - 3; // cause nextTerm already contains the 3rd term - while (i <= n){ - t1 = t2; - t2 = nextTerm; - nextTerm = t1 + t2; - i = i+1; - } -} - diff --git a/testFile_no_jmp b/testFile_no_jmp deleted file mode 100644 index d572de9..0000000 --- a/testFile_no_jmp +++ /dev/null @@ -1,9 +0,0 @@ -int main(){ - int a, d; - int b, c = 2; - b = a; - a = b +2; - a = c; - a = 5; - c = 19 + 2 - (5 * a + 8) * 2; -} diff --git a/yacc.tab.o b/yacc.tab.o deleted file mode 100644 index f3969e9..0000000 Binary files a/yacc.tab.o and /dev/null differ diff --git a/yacc.y b/yacc.y deleted file mode 100644 index 626d227..0000000 --- a/yacc.y +++ /dev/null @@ -1,209 +0,0 @@ -%define parse.error detailed - -%{ -#include -#include -#include "table.h" -#include "operations.h" -#include "blocs.h" -#include "asmTable.h" - -int t; -int labelWhileStart; -int labelWhileEnd; -int whileJumpAddr; -%} - -%code provides{ -int yylex (void); -void yyerror (const char *); -} - -%union {char str[NAME_MAX_LENGTH]; int nbInt; int addr; enumVarType type; } - /*loops keywords*/ -%token /*tWHILE tIF declared below*/ tELSE - /*reserved keywords*/ -%token tRETURN tPRINT - /*types : integers, floats or void*/ -%token tFLOAT tINT tVOID - /*operations, mul and div are precedent to sub and add*/ -%left tSUB tADD -%left tMUL tDIV - /*Assignment*/ -%left tASSIGN - /*comparisons*/ -%left tLT tGT tNE tEQ tGE tLE - /*boolean operators*/ -%left tAND tOR tNOT - /*syntaxic symbols*/ -%token tLBRACE tRBRACE tLPAR tRPAR tSEMI tCOMMA - - /*nametags and values*/ -%token tID -%token tNB - - - /* represents types with the values used in the table, see table.h */ -%type Type -%type Expression -%type ConditionalExpression -%type Declaration -%type NbOrVariable -%type IfStatement1 -%type Condition -%type InnerBlock - -%token tIF -%token tWHILE - -%start Program -%% - -Program : FunctionDef - | FunctionDef Program; - - /* Lines = Any line in the code that is not within an if/while statement*/ - Lines : Line - | Line Lines; - -Line : IfStatement - | WhileStatement - | Assignment - | Declarations - | FunctionCall - | Return - | Print; - -/*Innerblock = the inside of an if/else/while statement = { ... } or function = f(){...}*/ -InnerBlock : tLBRACE tRBRACE // a function or while loop can be empty cf GCC - | tLBRACE {increaseDepth();} Lines tRBRACE {decreaseDepth();}; - - -/*Condition = the evaluated boolean expression for an if or while = ( ... ) */ -Condition : tLPAR ConditionalExpression tRPAR {$$ = $2;}; - -/*ConditionalExpression = expression that evaluates to a boolean*/ -ConditionalExpression : tID { $$ = getOffset($1);} - | tNB {$$ = operation_afc_nb_tmp($1);} - | tLPAR ConditionalExpression tRPAR {$$ = $2;}// for cases like if((a or b) and (a or c)) where there are parenthesis inside - | NbOrVariable tLE NbOrVariable {$$ = cond_not(cond_sup($1, $3));} - | NbOrVariable tGE NbOrVariable {$$ = cond_not(cond_inf($1, $3));} - | NbOrVariable tEQ NbOrVariable {$$ = cond_eq($1, $3);} - | NbOrVariable tNE NbOrVariable {$$ = cond_not(cond_eq($1, $3));} - | NbOrVariable tLT NbOrVariable {$$ = cond_inf($1, $3);} - | NbOrVariable tGT NbOrVariable {$$ = cond_sup($1, $3);} - | tNOT ConditionalExpression {$$ = cond_not($2);} - | ConditionalExpression tOR ConditionalExpression {$$ = cond_or($1, $3);} - | ConditionalExpression tAND ConditionalExpression {$$ = cond_and($1, $3);}; - /*end of added bloat*/ - - -/*NbOrVariable is either a number or a variable of type int*/ -NbOrVariable : tID { $$ = getOffset($1);} - | tNB {$$ = operation_afc_nb_tmp($1);}; - - /*List of all numerical operators*/ - /* -NumericalOperator : tLE | tGE | tEQ | tNE | tLT | tGT; -*/ - - /*any arithmetic operation -Operation: tADD | tMUL | tSUB | tDIV; -*/ - -IfStatement1 : %empty { - int ligne =getCurrentLineNumber(); addLine("JMF"); $$ = ligne ; - }; - -IfStatement : tIF Condition IfStatement1 InnerBlock tELSE { - setConditionAddr($3,$2); int current = getCurrentLineNumber(); printf("current Line %d", current); addLine("JMP"); $1 = current; setJumpLine($3, current+1); -} InnerBlock { - int current = getCurrentLineNumber() ; printf("%d, %d",$1, current);setJumpLine($1, current); -} - | tIF Condition IfStatement1 InnerBlock { - setConditionAddr($3,$2); int current = getCurrentLineNumber(); printf("current Line %d", current); setJumpLine($3, current); -}; - -WhileStatement : tWHILE { - $1 = getCurrentLineNumber(); -} Condition { - int current = getCurrentLineNumber(); - addLine("JMF"); - setConditionAddr(current,$3); - whileJumpAddr = current; - suppressCONDElements(); -} InnerBlock { - addLine("JMP"); - int current = getCurrentLineNumber(); - setJumpLine(whileJumpAddr, current); - setJumpLine(current-1, $1); -}; - -Assignment : tID tASSIGN Expression tSEMI { - setInit($1); operation_copy(getOffset($1),$3); suppressTempINTElements(); - }; - - /*Expression operation applied on variables or values*/ -Expression : NbOrVariable {$$ = $1;} - | FunctionCall{$$ = 0;} // TODO : wait untile functions are implemented - | tLPAR Expression tRPAR {$$ = $2;} - /* replaced by the four following lines - //| Expression Operation Expression - */ - | Expression tADD Expression {$$ = operation_add($1, $3);} - | Expression tSUB Expression {$$ = operation_sub($1, $3);} - | Expression tMUL Expression {$$ = operation_mul($1, $3);} - | Expression tDIV Expression {$$ = operation_divInt($1, $3);}; - /*end of added bloat*/ - -Expressions : Expression - | Expression tCOMMA Expressions; - -FunctionCall : tID tLPAR Expressions tRPAR; - -FunctionDef : Type tID FunctionParams InnerBlock {resetSymboltable();} - | tVOID tID FunctionParams InnerBlock {resetSymboltable();}; - - /*FunctionParams = the parameters of a function*/ -FunctionParams : tLPAR tRPAR - | tLPAR tVOID tRPAR - | tLPAR VarsWithType tRPAR - -VarsWithType : VarWithType - | VarWithType tCOMMA VarsWithType; - - /*VarWithType = a variable associated to its type = int a*/ -VarWithType : Type tID {addElement($2,$1);setInit($2);}; - - /*the return type or argument type*/ -Type : tINT {$$ = INT;} - | tFLOAT {$$ = FLOAT;}; - - -Declarations : Type { t = $1; } Declaration Declarations1 tSEMI ; - -Declaration : tID {addElement($1, (enumVarType) t);} - | tID {addElement($1, (enumVarType) t); setInit($1);} tASSIGN Expression {operation_copy(getOffset($1),$4); suppressTempINTElements();} ; - -Declarations1 : tCOMMA Declaration Declarations1 | %empty ; - - -Return : tRETURN Expression tSEMI {}; - -Print : tPRINT tLPAR Expression tRPAR tSEMI; - -%% - -void yyerror(const char *msg) { - fprintf(stderr, "\033[1m\033[31m[/!\\]\033[0m Error : %s\n", msg); - exit(1); -} - -int main(void) { - clearOp(); - initSymbolTable(); - initASMTable(); - yyparse(); - exportASMTable(); -} - // SI >> SC