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EyeXion 2020-10-12 09:03:43 +02:00
parent 2a9161007a
commit 501145e0f0
100 changed files with 16956 additions and 762 deletions
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57
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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx
* @{
*/
#ifndef __STM32F1XX_H
#define __STM32F1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F1)
#define STM32F1
#endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.1
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F100xB)
#include "stm32f100xb.h"
#elif defined(STM32F100xE)
#include "stm32f100xe.h"
#elif defined(STM32F101x6)
#include "stm32f101x6.h"
#elif defined(STM32F101xB)
#include "stm32f101xb.h"
#elif defined(STM32F101xE)
#include "stm32f101xe.h"
#elif defined(STM32F101xG)
#include "stm32f101xg.h"
#elif defined(STM32F102x6)
#include "stm32f102x6.h"
#elif defined(STM32F102xB)
#include "stm32f102xb.h"
#elif defined(STM32F103x6)
#include "stm32f103x6.h"
#elif defined(STM32F103xB)
#include "stm32f103xb.h"
#elif defined(STM32F103xE)
#include "stm32f103xe.h"
#elif defined(STM32F103xG)
#include "stm32f103xg.h"
#elif defined(STM32F105xC)
#include "stm32f105xc.h"
#elif defined(STM32F107xC)
#include "stm32f107xc.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_SYSTEM_H
#define __STM32F1xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (DBGMCU)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#if defined(FLASH_ACR_LATENCY)
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
#else
#endif /* FLASH_ACR_LATENCY */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @note For Low Density devices, the device ID is 0x412
* @note For Medium Density devices, the device ID is 0x410
* @note For High Density devices, the device ID is 0x414
* @note For XL Density devices, the device ID is 0x430
* @note For Connectivity Line devices, the device ID is 0x418
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
For example, it is read as revA -> 0x1000,for Low Density devices
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @}
*/
#if defined(FLASH_ACR_LATENCY)
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Disable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Check if Prefetch buffer is enabled
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Enable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Disable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Check if Flash Half Cycle Access is enabled or not
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FLASH) || defined (DBGMCU) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_SYSTEM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_UTILS_H
#define __STM32F1xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_UTILS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_rcc.c
* @author MCD Application Team
* @brief RCC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCC_LL_Private_Macros
* @{
*/
#if defined(RCC_PLLI2S_SUPPORT)
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(USB) || defined(USB_OTG_FS)
#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#endif /* USB */
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
uint32_t RCC_GetSystemClockFreq(void);
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
#if defined(RCC_PLLI2S_SUPPORT)
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(RCC_PLL2_SUPPORT)
uint32_t RCC_PLL2_GetFreqClockFreq(void);
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_LL_Exported_Functions
* @{
*/
/** @addtogroup RCC_LL_EF_Init
* @{
*/
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE PLL, PLL2 & PLL3 are OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Wait for HSI READY bit */
while (LL_RCC_HSI_IsReady() != 1U)
{}
/* Configure HSI as system clock source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
/* Wait till clock switch is ready */
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{}
/* Reset PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Wait for PLL READY bit to be reset */
while (LL_RCC_PLL_IsReady() != 0U)
{}
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Reset HSEON, HSEBYP & CSSON bits */
CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
#if defined(RCC_CR_PLL2ON)
/* Reset PLL2ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
#endif /* RCC_CR_PLL2ON */
#if defined(RCC_CR_PLL3ON)
/* Reset PLL3ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
#endif /* RCC_CR_PLL3ON */
/* Set HSITRIM bits to the reset value */
LL_RCC_HSI_SetCalibTrimming(0x10U);
#if defined(RCC_CFGR2_PREDIV1)
/* Reset CFGR2 register */
LL_RCC_WriteReg(CFGR2, 0x00000000U);
#endif /* RCC_CFGR2_PREDIV1 */
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
/* Clear reset flags */
LL_RCC_ClearResetFlags();
return SUCCESS;
}
/**
* @}
*/
/** @addtogroup RCC_LL_EF_Get_Freq
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* and different peripheral clocks available on the device.
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
* @note If SYSCLK source is PLL, function returns values based on
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
* @note (**) HSI_VALUE is a defined constant but the real value may vary
* depending on the variations in voltage and temperature.
* @note (***) HSE_VALUE is a defined constant, user has to ensure that
* HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
* @note The result of this function could be incorrect when using fractional
* value for HSE crystal.
* @note This function can be used by the user application to compute the
* baud-rate for the communication peripherals or configure other parameters.
* @{
*/
/**
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
* must be called to update structure fields. Otherwise, any
* configuration based on this function will be incorrect.
* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
* @retval None
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
{
/* Get SYSCLK frequency */
RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
/* HCLK clock frequency */
RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
/* PCLK1 clock frequency */
RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
/* PCLK2 clock frequency */
RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
}
#if defined(RCC_CFGR2_I2S2SRC)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S2_CLKSOURCE
* @arg @ref LL_RCC_I2S3_CLKSOURCE
* @retval I2S clock frequency (in Hz)
*/
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
{
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
/* I2S1CLK clock frequency */
switch (LL_RCC_GetI2SClockSource(I2SxSource))
{
case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
i2s_frequency = RCC_GetSystemClockFreq();
break;
case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
default:
i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
break;
}
return i2s_frequency;
}
#endif /* RCC_CFGR2_I2S2SRC */
#if defined(USB) || defined(USB_OTG_FS)
/**
* @brief Return USBx clock frequency
* @param USBxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE
* @retval USB clock frequency (in Hz)
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
*/
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
{
uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
/* USBCLK clock frequency */
switch (LL_RCC_GetUSBClockSource(USBxSource))
{
#if defined(RCC_CFGR_USBPRE)
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
}
break;
#endif /* RCC_CFGR_USBPRE */
#if defined(RCC_CFGR_OTGFSPRE)
/* USBCLK = PLLVCO/2
= (2 x PLLCLK) / 2
= PLLCLK */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
/* USBCLK = PLLVCO/3
= (2 x PLLCLK) / 3 */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
}
break;
#endif /* RCC_CFGR_OTGFSPRE */
}
return usb_frequency;
}
#endif /* USB */
/**
* @brief Return ADCx clock frequency
* @param ADCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC_CLKSOURCE
* @retval ADC clock frequency (in Hz)
*/
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
{
uint32_t adc_prescaler = 0U;
uint32_t adc_frequency = 0U;
/* Check parameter */
assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
/* Get ADC prescaler */
adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
return adc_frequency;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RCC_LL_Private_Functions
* @{
*/
/**
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
switch (LL_RCC_GetSysClkSource())
{
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
frequency = HSI_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
frequency = HSE_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
frequency = RCC_PLL_GetFreqDomain_SYS();
break;
default:
frequency = HSI_VALUE;
break;
}
return frequency;
}
/**
* @brief Return HCLK clock frequency
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
}
/**
* @brief Return PCLK1 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
}
/**
* @brief Return PCLK2 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
}
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE / 2U;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#if defined(RCC_PLL2_SUPPORT)
case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#endif /* RCC_PLL2_SUPPORT */
default:
pllinputfreq = HSI_VALUE / 2U;
break;
}
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
}
#if defined(RCC_PLL2_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL2_GetFreqClockFreq(void)
{
return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
{
return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLLI2S_SUPPORT */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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LLDrivers/src/stm32f1xx_ll_utils.c Normal file
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@ -0,0 +1,606 @@
/**
******************************************************************************
* @file stm32f1xx_ll_utils.c
* @author MCD Application Team
* @brief UTILS LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_system.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @addtogroup UTILS_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
/* Defines used for PLL range */
#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
/* Defines used for HSE range */
#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
#if defined(FLASH_ACR_LATENCY)
#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
#else
/*!< No Latency Configuration in this device */
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Macros
* @{
*/
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
#if defined(RCC_CFGR_PLLMULL6_5)
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
#else
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_16))
#endif /* RCC_CFGR_PLLMULL6_5 */
#if defined(RCC_CFGR2_PREDIV1)
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
#else
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UTILS_LL_Exported_Functions
* @{
*/
/** @addtogroup UTILS_LL_EF_DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
* @note When a RTOS is used, it is recommended to avoid changing the Systick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* on SysTick counter flag
* @note When a RTOS is used, it is recommended to avoid using blocking delay
* and use rather osDelay service.
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
/* Add this code to indicate that local variable is not used */
((void)tmp);
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
{
Delay++;
}
while (Delay)
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
{
Delay--;
}
}
}
/**
* @}
*/
/** @addtogroup UTILS_EF_SYSTEM
* @brief System Configuration functions
*
@verbatim
===============================================================================
##### System Configuration functions #####
===============================================================================
[..]
System, AHB and APB buses clocks configuration
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
@endverbatim
@internal
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
(++) +-----------------------------------------------+
(++) | Latency | SYSCLK clock frequency (MHz) |
(++) |---------------|-------------------------------|
(++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
(++) |---------------|-------------------------------|
(++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
(++) |---------------|-------------------------------|
(++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
(++) +-----------------------------------------------+
@endinternal
* @{
*/
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
}
/**
* @brief This function configures system clock with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed 72MHz
* @note FLASH latency can be modified through this function.
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
{
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1U)
{
/* Wait for HSI ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @brief This function configures system clock with HSE as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed @ref UTILS_PLL_OUTPUT_MAX
* @note FLASH latency can be modified through this function.
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
{
LL_RCC_HSE_EnableBypass();
}
else
{
LL_RCC_HSE_DisableBypass();
}
/* Enable HSE */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1U)
{
/* Wait for HSE ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param Frequency SYSCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
ErrorStatus status = SUCCESS;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
{
status = ERROR;
}
else
{
if (Frequency > UTILS_LATENCY2_FREQ)
{
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
}
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
{
status = ERROR;
}
}
return status;
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Function to check that PLL can be modified
* @param PLL_InputFrequency PLL input frequency (in Hz)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
/* Check different PLL parameters according to RM */
#if defined (RCC_CFGR2_PREDIV1)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
#endif /*RCC_CFGR2_PREDIV1SRC*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
}
/**
* @brief Function to check that PLL can be modified
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
ErrorStatus status = SUCCESS;
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
{
/* PLL configuration cannot be modified */
status = ERROR;
}
#if defined(RCC_PLL2_SUPPORT)
/* Check if PLL2 is busy*/
if (LL_RCC_PLL2_IsReady() != 0U)
{
/* PLL2 configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/* Check if PLLI2S is busy*/
if (LL_RCC_PLLI2S_IsReady() != 0U)
{
/* PLLI2S configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLLI2S_SUPPORT */
return status;
}
/**
* @brief Function to enable PLL and switch system clock to PLL
* @param SYSCLK_Frequency SYSCLK frequency
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
#if defined(FLASH_ACR_LATENCY)
uint32_t sysclk_frequency_current = 0U;
#endif /* FLASH_ACR_LATENCY */
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
#if defined(FLASH_ACR_LATENCY)
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
#endif /* FLASH_ACR_LATENCY */
/* Increasing the number of wait states because of higher CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current < SYSCLK_Frequency)
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update system clock configuration */
if (status == SUCCESS)
{
#if defined(RCC_PLL2_SUPPORT)
if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
{
/* Enable PLL2 */
LL_RCC_PLL2_Enable();
while (LL_RCC_PLL2_IsReady() != 1U)
{
/* Wait for PLL2 ready */
}
}
#endif /* RCC_PLL2_SUPPORT */
/* Enable PLL */
LL_RCC_PLL_Enable();
while (LL_RCC_PLL_IsReady() != 1U)
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
}
/* Decreasing the number of wait states because of lower CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current > SYSCLK_Frequency)
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update SystemCoreClock variable */
if (status == SUCCESS)
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

0
NUCLEO-F103RB/ExtDll.iex → MDK-ARM/NUCLEO-F103RB/ExtDll.iex
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BIN
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.axf Normal file
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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.29.0.0
Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Toto Lala, INSA Toulouse, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.29.0.0
Toolchain Path: F:\Keil\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.29.0.0
Dialog DLL: DARMSTM.DLL V1.68.0.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.7.0
Dialog DLL: TARMSTM.DLL V1.66.0.0
<h2>Project:</h2>
C:\Users\elies\Desktop\Cours\4A\Info Mat\Projet_Voilier_4IR\MDK-ARM\Project.uvprojx
Project File Date: 10/12/2020
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'F:\Keil\ARM\ARMCC\Bin'
Rebuild target 'NUCLEO-F103RB'
compiling Allure.c...
compiling Voilier.c...
..\Src\Voilier.c(3): warning: #1-D: last line of file ends without a newline
}
..\Src\Voilier.c: 1 warning, 0 errors
compiling AntiCharvirement.c...
compiling Batterie.c...
compiling Gouvernail.c...
compiling Heure.c...
compiling Transmission.c...
compiling Voile.c...
compiling MyTimer.c...
compiling stm32f1xx_ll_rcc.c...
compiling stm32f1xx_ll_utils.c...
assembling startup_stm32f103xb.s...
compiling system_stm32f1xx.c...
linking...
Program Size: Code=296 RO-data=268 RW-data=16 ZI-data=1024
"NUCLEO-F103RB\NUCLEO-F103RB.axf" - 0 Error(s), 1 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
Keil.STM32F1xx_DFP.2.3.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_NUCLEO-F103RB
C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:04
</pre>
</body>
</html>

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [NUCLEO-F103RB\NUCLEO-F103RB.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image NUCLEO-F103RB\NUCLEO-F103RB.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060750: Last Updated: Mon Oct 12 09:03:11 2020
<BR><P>
<H3>Maximum Stack Usage = 8 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
TIM1_UP_IRQHandler
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
<LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
<LI><a href="#[3]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">MemManage_Handler</a><BR>
<LI><a href="#[4]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">BusFault_Handler</a><BR>
<LI><a href="#[5]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">UsageFault_Handler</a><BR>
<LI><a href="#[6]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[6]">SVC_Handler</a><BR>
<LI><a href="#[7]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[7]">DebugMon_Handler</a><BR>
<LI><a href="#[8]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[8]">PendSV_Handler</a><BR>
<LI><a href="#[9]">SysTick_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[9]">SysTick_Handler</a><BR>
<LI><a href="#[1c]">ADC1_2_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC1_2_IRQHandler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[1c]">ADC1_2_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[4]">BusFault_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[15]">DMA1_Channel1_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[16]">DMA1_Channel2_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[17]">DMA1_Channel3_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[18]">DMA1_Channel4_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[19]">DMA1_Channel5_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1a]">DMA1_Channel6_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1b]">DMA1_Channel7_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[7]">DebugMon_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[e]">FLASH_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2]">HardFault_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[3]">MemManage_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1]">NMI_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[b]">PVD_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[8]">PendSV_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[f]">RCC_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[d]">RTC_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[0]">Reset_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[6]">SVC_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[9]">SysTick_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[36]">SystemInit</a> from system_stm32f1xx.o(i.SystemInit) referenced from startup_stm32f103xb.o(.text)
<LI><a href="#[c]">TAMPER_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[22]">TIM1_BRK_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[25]">TIM1_CC_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[24]">TIM1_TRG_COM_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[23]">TIM1_UP_IRQHandler</a> from mytimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[26]">TIM2_IRQHandler</a> from mytimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[27]">TIM3_IRQHandler</a> from mytimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[28]">TIM4_IRQHandler</a> from mytimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[2f]">USART1_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[30]">USART2_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[31]">USART3_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[34]">USBWakeUp_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1d]">USB_HP_CAN1_TX_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[1e]">USB_LP_CAN1_RX0_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[5]">UsageFault_Handler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[a]">WWDG_IRQHandler</a> from startup_stm32f103xb.o(.text) referenced from startup_stm32f103xb.o(RESET)
<LI><a href="#[37]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f103xb.o(.text)
<LI><a href="#[35]">main</a> from voilier.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[37]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(.text)
</UL>
<P><STRONG><a name="[3b]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
<P><STRONG><a name="[38]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[39]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[3a]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Called By]<UL><LI><a href="#[39]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[3c]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
<P><STRONG><a name="[3d]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
<P><STRONG><a name="[3e]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
<P><STRONG><a name="[3f]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
<P><STRONG><a name="[40]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>ADC1_2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>DMA1_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>DMA1_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>DMA1_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>DMA1_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>DMA1_Channel7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>TAMPER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>TIM1_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>TIM1_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>USBWakeUp_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>USB_HP_CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>USB_LP_CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f103xb.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[3a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
</UL>
<P><STRONG><a name="[41]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
<P><STRONG><a name="[36]"></a>SystemInit</STRONG> (Thumb, 56 bytes, Stack size 0 bytes, system_stm32f1xx.o(i.SystemInit))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(.text)
</UL>
<P><STRONG><a name="[23]"></a>TIM1_UP_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, mytimer.o(i.TIM1_UP_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM1_UP_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, mytimer.o(i.TIM2_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM2_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, mytimer.o(i.TIM3_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM3_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, mytimer.o(i.TIM4_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM4_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f103xb.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
<P><STRONG><a name="[43]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
<P><STRONG><a name="[44]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
<P><STRONG><a name="[35]"></a>main</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, voilier.o(i.main))
<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
</UL><P>
<H3>
Local Symbols
</H3><P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>

18
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.lnp Normal file
View file

@ -0,0 +1,18 @@
--cpu Cortex-M3
"nucleo-f103rb\voilier.o"
"nucleo-f103rb\mytimer.o"
"nucleo-f103rb\allure.o"
"nucleo-f103rb\anticharvirement.o"
"nucleo-f103rb\batterie.o"
"nucleo-f103rb\gouvernail.o"
"nucleo-f103rb\heure.o"
"nucleo-f103rb\transmission.o"
"nucleo-f103rb\voile.o"
"nucleo-f103rb\stm32f1xx_ll_rcc.o"
"nucleo-f103rb\stm32f1xx_ll_utils.o"
"nucleo-f103rb\system_stm32f1xx.o"
"nucleo-f103rb\startup_stm32f103xb.o"
--library_type=microlib --strict --scatter "NUCLEO-F103RB\NUCLEO-F103RB.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list "NUCLEO-F103RB.map" -o NUCLEO-F103RB\NUCLEO-F103RB.axf

378
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.map Normal file
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@ -0,0 +1,378 @@
Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]
==============================================================================
Section Cross References
mytimer.o(i.MyTimer_IT_Conf) refers to mytimer.o(.data) for .data
mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for .data
mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for .data
mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for .data
mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for .data
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) for RCC_GetPCLK1ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency) for UTILS_SetFlashLatency
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.data) for SystemCoreClock
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.data) for .data
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.constdata) for .constdata
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(STACK) for __initial_sp
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(.text) for Reset_Handler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
startup_stm32f103xb.o(.text) refers to system_stm32f1xx.o(i.SystemInit) for SystemInit
startup_stm32f103xb.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
entry9a.o(.ARM.Collect$$$$0000000B) refers to voilier.o(i.main) for main
entry9b.o(.ARM.Collect$$$$0000000C) refers to voilier.o(i.main) for main
init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
==============================================================================
Removing Unused input sections from the image.
Removing mytimer.o(.rev16_text), (4 bytes).
Removing mytimer.o(.revsh_text), (4 bytes).
Removing mytimer.o(.rrx_text), (6 bytes).
Removing mytimer.o(i.MyTimer_Conf), (76 bytes).
Removing mytimer.o(i.MyTimer_IT_Conf), (152 bytes).
Removing mytimer.o(i.MyTimer_IT_Disable), (68 bytes).
Removing mytimer.o(i.MyTimer_Start), (10 bytes).
Removing mytimer.o(i.MyTimer_Stop), (10 bytes).
Removing stm32f1xx_ll_rcc.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit), (96 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq), (48 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq), (32 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq), (56 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq), (28 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq), (28 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq), (28 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS), (60 bytes).
Removing stm32f1xx_ll_utils.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_Init1msTick), (26 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE), (108 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI), (88 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS), (24 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock), (12 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_mDelay), (30 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem), (172 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency), (24 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy), (24 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency), (68 bytes).
Removing system_stm32f1xx.o(.rev16_text), (4 bytes).
Removing system_stm32f1xx.o(.revsh_text), (4 bytes).
Removing system_stm32f1xx.o(.rrx_text), (6 bytes).
Removing system_stm32f1xx.o(i.SystemCoreClockUpdate), (104 bytes).
Removing system_stm32f1xx.o(.constdata), (16 bytes).
Removing system_stm32f1xx.o(.constdata), (8 bytes).
Removing system_stm32f1xx.o(.data), (4 bytes).
Removing startup_stm32f103xb.o(HEAP), (512 bytes).
41 unused section(s) (total 2004 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../Src/system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\MyDrivers\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
..\Src\Allure.c 0x00000000 Number 0 allure.o ABSOLUTE
..\Src\AntiCharvirement.c 0x00000000 Number 0 anticharvirement.o ABSOLUTE
..\Src\Batterie.c 0x00000000 Number 0 batterie.o ABSOLUTE
..\Src\Gouvernail.c 0x00000000 Number 0 gouvernail.o ABSOLUTE
..\Src\Heure.c 0x00000000 Number 0 heure.o ABSOLUTE
..\Src\Transmission.c 0x00000000 Number 0 transmission.o ABSOLUTE
..\Src\Voile.c 0x00000000 Number 0 voile.o ABSOLUTE
..\Src\Voilier.c 0x00000000 Number 0 voilier.o ABSOLUTE
..\Src\system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\\MyDrivers\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
init.s 0x00000000 Number 0 init.o ABSOLUTE
startup_stm32f103xb.s 0x00000000 Number 0 startup_stm32f103xb.o ABSOLUTE
RESET 0x08000000 Section 236 startup_stm32f103xb.o(RESET)
.ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
.ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
.ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
.ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
.ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
.ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
.ARM.Collect$$$$0000000D 0x080000fc Section 0 entry10a.o(.ARM.Collect$$$$0000000D)
.ARM.Collect$$$$0000000F 0x080000fc Section 0 entry11a.o(.ARM.Collect$$$$0000000F)
.ARM.Collect$$$$00002712 0x080000fc Section 4 entry2.o(.ARM.Collect$$$$00002712)
__lit__00000000 0x080000fc Data 4 entry2.o(.ARM.Collect$$$$00002712)
.text 0x08000100 Section 36 startup_stm32f103xb.o(.text)
.text 0x08000124 Section 36 init.o(.text)
i.SystemInit 0x08000148 Section 0 system_stm32f1xx.o(i.SystemInit)
i.TIM1_UP_IRQHandler 0x08000190 Section 0 mytimer.o(i.TIM1_UP_IRQHandler)
i.TIM2_IRQHandler 0x080001a8 Section 0 mytimer.o(i.TIM2_IRQHandler)
i.TIM3_IRQHandler 0x080001c0 Section 0 mytimer.o(i.TIM3_IRQHandler)
i.TIM4_IRQHandler 0x080001d8 Section 0 mytimer.o(i.TIM4_IRQHandler)
i.__scatterload_copy 0x080001f0 Section 14 handlers.o(i.__scatterload_copy)
i.__scatterload_null 0x080001fe Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x08000200 Section 14 handlers.o(i.__scatterload_zeroinit)
i.main 0x0800020e Section 0 voilier.o(i.main)
.data 0x20000000 Section 16 mytimer.o(.data)
STACK 0x20000010 Section 1024 startup_stm32f103xb.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_use_no_argv 0x00000000 Number 0 voilier.o ABSOLUTE
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__decompress - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_microlib_exit - Undefined Weak Reference
__Vectors_Size 0x000000ec Number 0 startup_stm32f103xb.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_stm32f103xb.o(RESET)
__Vectors_End 0x080000ec Data 0 startup_stm32f103xb.o(RESET)
__main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
_main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
_main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
__main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
_main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
_main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
_main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
__rt_final_cpp 0x080000fd Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D)
__rt_final_exit 0x080000fd Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F)
Reset_Handler 0x08000101 Thumb Code 8 startup_stm32f103xb.o(.text)
NMI_Handler 0x08000109 Thumb Code 2 startup_stm32f103xb.o(.text)
HardFault_Handler 0x0800010b Thumb Code 2 startup_stm32f103xb.o(.text)
MemManage_Handler 0x0800010d Thumb Code 2 startup_stm32f103xb.o(.text)
BusFault_Handler 0x0800010f Thumb Code 2 startup_stm32f103xb.o(.text)
UsageFault_Handler 0x08000111 Thumb Code 2 startup_stm32f103xb.o(.text)
SVC_Handler 0x08000113 Thumb Code 2 startup_stm32f103xb.o(.text)
DebugMon_Handler 0x08000115 Thumb Code 2 startup_stm32f103xb.o(.text)
PendSV_Handler 0x08000117 Thumb Code 2 startup_stm32f103xb.o(.text)
SysTick_Handler 0x08000119 Thumb Code 2 startup_stm32f103xb.o(.text)
ADC1_2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_RX1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_SCE_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel6_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel7_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI15_10_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI9_5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
PVD_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RCC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_Alarm_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TAMPER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_BRK_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USBWakeUp_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_HP_CAN1_TX_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_LP_CAN1_RX0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
WWDG_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
__scatterload 0x08000125 Thumb Code 28 init.o(.text)
__scatterload_rt2 0x08000125 Thumb Code 0 init.o(.text)
SystemInit 0x08000149 Thumb Code 56 system_stm32f1xx.o(i.SystemInit)
TIM1_UP_IRQHandler 0x08000191 Thumb Code 16 mytimer.o(i.TIM1_UP_IRQHandler)
TIM2_IRQHandler 0x080001a9 Thumb Code 18 mytimer.o(i.TIM2_IRQHandler)
TIM3_IRQHandler 0x080001c1 Thumb Code 16 mytimer.o(i.TIM3_IRQHandler)
TIM4_IRQHandler 0x080001d9 Thumb Code 16 mytimer.o(i.TIM4_IRQHandler)
__scatterload_copy 0x080001f1 Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x080001ff Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x08000201 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
main 0x0800020f Thumb Code 4 voilier.o(i.main)
Region$$Table$$Base 0x08000214 Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x08000234 Number 0 anon$$obj.o(Region$$Table)
pTIM1_Overflow 0x20000000 Data 4 mytimer.o(.data)
pTIM2_Overflow 0x20000004 Data 4 mytimer.o(.data)
pTIM3_Overflow 0x20000008 Data 4 mytimer.o(.data)
pTIM4_Overflow 0x2000000c Data 4 mytimer.o(.data)
__initial_sp 0x20000410 Data 0 startup_stm32f103xb.o(STACK)
==============================================================================
Memory Map of the image
Image Entry point : 0x080000ed
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000244, Max: 0x00020000, ABSOLUTE)
Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000234, Max: 0x00020000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x08000000 0x08000000 0x000000ec Data RO 329 RESET startup_stm32f103xb.o
0x080000ec 0x080000ec 0x00000000 Code RO 334 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
0x080000ec 0x080000ec 0x00000004 Code RO 337 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
0x080000f0 0x080000f0 0x00000004 Code RO 340 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
0x080000f4 0x080000f4 0x00000000 Code RO 342 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
0x080000f4 0x080000f4 0x00000000 Code RO 344 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
0x080000f4 0x080000f4 0x00000008 Code RO 345 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
0x080000fc 0x080000fc 0x00000000 Code RO 347 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o)
0x080000fc 0x080000fc 0x00000000 Code RO 349 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o)
0x080000fc 0x080000fc 0x00000004 Code RO 338 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
0x08000100 0x08000100 0x00000024 Code RO 330 .text startup_stm32f103xb.o
0x08000124 0x08000124 0x00000024 Code RO 351 .text mc_w.l(init.o)
0x08000148 0x08000148 0x00000048 Code RO 293 i.SystemInit system_stm32f1xx.o
0x08000190 0x08000190 0x00000018 Code RO 20 i.TIM1_UP_IRQHandler mytimer.o
0x080001a8 0x080001a8 0x00000018 Code RO 21 i.TIM2_IRQHandler mytimer.o
0x080001c0 0x080001c0 0x00000018 Code RO 22 i.TIM3_IRQHandler mytimer.o
0x080001d8 0x080001d8 0x00000018 Code RO 23 i.TIM4_IRQHandler mytimer.o
0x080001f0 0x080001f0 0x0000000e Code RO 355 i.__scatterload_copy mc_w.l(handlers.o)
0x080001fe 0x080001fe 0x00000002 Code RO 356 i.__scatterload_null mc_w.l(handlers.o)
0x08000200 0x08000200 0x0000000e Code RO 357 i.__scatterload_zeroinit mc_w.l(handlers.o)
0x0800020e 0x0800020e 0x00000004 Code RO 1 i.main voilier.o
0x08000212 0x08000212 0x00000002 PAD
0x08000214 0x08000214 0x00000020 Data RO 353 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000234, Size: 0x00000410, Max: 0x00005000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x20000000 0x08000234 0x00000010 Data RW 24 .data mytimer.o
0x20000010 - 0x00000400 Zero RW 327 STACK startup_stm32f103xb.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
96 30 0 16 0 342549 mytimer.o
36 8 236 0 1024 780 startup_stm32f103xb.o
72 16 0 0 0 465 system_stm32f1xx.o
4 0 0 0 0 1863 voilier.o
----------------------------------------------------------------------
210 54 268 16 1024 345657 Object Totals
0 0 32 0 0 0 (incl. Generated)
2 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
0 0 0 0 0 0 entry.o
0 0 0 0 0 0 entry10a.o
0 0 0 0 0 0 entry11a.o
8 4 0 0 0 0 entry2.o
4 0 0 0 0 0 entry5.o
0 0 0 0 0 0 entry7b.o
0 0 0 0 0 0 entry8b.o
8 4 0 0 0 0 entry9a.o
30 0 0 0 0 0 handlers.o
36 8 0 0 0 68 init.o
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
86 16 0 0 0 68 mc_w.l
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
296 70 268 16 1024 345721 Grand Totals
296 70 268 16 1024 345721 ELF Image Totals
296 70 268 16 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 564 ( 0.55kB)
Total RW Size (RW Data + ZI Data) 1040 ( 1.02kB)
Total ROM Size (Code + RO Data + RW Data) 580 ( 0.57kB)
==============================================================================

16
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.sct Normal file
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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00005000 { ; RW data
.ANY (+RW +ZI)
}
}

0
NUCLEO-F103RB/NUCLEO-F103RB.sct → MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB_sct.Bak
View file

50
MDK-ARM/NUCLEO-F103RB/Project_NUCLEO-F103RB.dep Normal file
View file

@ -0,0 +1,50 @@
Dependencies for Project 'Project', Target 'NUCLEO-F103RB': (DO NOT MODIFY !)
CompilerVersion: 5060750::V5.06 update 6 (build 750)::ARMCC
F (..\Src\Voilier.c)(0x5F83FFA9)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\voilier.o --omf_browse nucleo-f103rb\voilier.crf --depend nucleo-f103rb\voilier.d)
F (..\MyDrivers\MyTimer.c)(0x5F64ABA2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\mytimer.o --omf_browse nucleo-f103rb\mytimer.crf --depend nucleo-f103rb\mytimer.d)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (..\Src\Allure.c)(0x5F83F90A)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\allure.o --omf_browse nucleo-f103rb\allure.crf --depend nucleo-f103rb\allure.d)
F (..\Src\AntiCharvirement.c)(0x5F83F91C)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\anticharvirement.o --omf_browse nucleo-f103rb\anticharvirement.crf --depend nucleo-f103rb\anticharvirement.d)
F (..\Src\Batterie.c)(0x5F83F929)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\batterie.o --omf_browse nucleo-f103rb\batterie.crf --depend nucleo-f103rb\batterie.d)
F (..\Src\Gouvernail.c)(0x5F83F934)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\gouvernail.o --omf_browse nucleo-f103rb\gouvernail.crf --depend nucleo-f103rb\gouvernail.d)
F (..\Src\Heure.c)(0x5F83F943)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\heure.o --omf_browse nucleo-f103rb\heure.crf --depend nucleo-f103rb\heure.d)
F (..\Src\Transmission.c)(0x5F83F94E)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\transmission.o --omf_browse nucleo-f103rb\transmission.crf --depend nucleo-f103rb\transmission.d)
F (..\Src\Voile.c)(0x5F83F958)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\voile.o --omf_browse nucleo-f103rb\voile.crf --depend nucleo-f103rb\voile.d)
F (..\LLDrivers\src\stm32f1xx_ll_rcc.c)(0x5D10A076)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\stm32f1xx_ll_rcc.o --omf_browse nucleo-f103rb\stm32f1xx_ll_rcc.crf --depend nucleo-f103rb\stm32f1xx_ll_rcc.d)
I (..\LLDrivers\inc\stm32f1xx_ll_rcc.h)(0x5D10A076)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (..\LLDrivers\src\stm32f1xx_ll_utils.c)(0x5D10A088)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\stm32f1xx_ll_utils.o --omf_browse nucleo-f103rb\stm32f1xx_ll_utils.crf --depend nucleo-f103rb\stm32f1xx_ll_utils.d)
I (..\LLDrivers\inc\stm32f1xx_ll_rcc.h)(0x5D10A076)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
I (..\LLDrivers\inc\stm32f1xx_ll_utils.h)(0x5D10A088)
I (..\LLDrivers\inc\stm32f1xx_ll_system.h)(0x5D10A06A)
F (../Src/system_stm32f1xx.c)(0x5D0B5E70)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\system_stm32f1xx.o --omf_browse nucleo-f103rb\system_stm32f1xx.crf --depend nucleo-f103rb\system_stm32f1xx.d)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (startup_stm32f103xb.s)(0x5CFE6264)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\_NUCLEO-F103RB -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 529" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list startup_stm32f103xb.lst --xref -o nucleo-f103rb\startup_stm32f103xb.o --depend nucleo-f103rb\startup_stm32f103xb.d)

67
MDK-ARM/NUCLEO-F103RB/Project_Simulateur.dep Normal file
View file

@ -0,0 +1,67 @@
Dependencies for Project 'Project', Target 'Simulateur': (DO NOT MODIFY !)
CompilerVersion: 5060750::V5.06 update 6 (build 750)::ARMCC
F (../Src/main.c)(0x5F6E0735)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\main.o --omf_browse nucleo-f103rb\main.crf --depend nucleo-f103rb\main.d)
I (..\LLDrivers\inc\stm32f1xx_ll_rcc.h)(0x5D10A076)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
I (..\LLDrivers\inc\stm32f1xx_ll_utils.h)(0x5D10A088)
I (..\LLDrivers\inc\stm32f1xx_ll_system.h)(0x5D10A06A)
I (..\Services\Chrono.h)(0x5F64A7AD)
I (..\MyDrivers\MyTimer.h)(0x5F649B45)
F (..\Services\Chrono.c)(0x5F64B102)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\chrono.o --omf_browse nucleo-f103rb\chrono.crf --depend nucleo-f103rb\chrono.d)
I (..\Services\Chrono.h)(0x5F64A7AD)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
I (..\MyDrivers\MyTimer.h)(0x5F649B45)
F (..\MyDrivers\MyTimer.c)(0x5F64ABA2)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\mytimer.o --omf_browse nucleo-f103rb\mytimer.crf --depend nucleo-f103rb\mytimer.d)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (..\LLDrivers\src\stm32f1xx_ll_rcc.c)(0x5D10A076)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\stm32f1xx_ll_rcc.o --omf_browse nucleo-f103rb\stm32f1xx_ll_rcc.crf --depend nucleo-f103rb\stm32f1xx_ll_rcc.d)
I (..\LLDrivers\inc\stm32f1xx_ll_rcc.h)(0x5D10A076)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (..\LLDrivers\src\stm32f1xx_ll_utils.c)(0x5D10A088)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\stm32f1xx_ll_utils.o --omf_browse nucleo-f103rb\stm32f1xx_ll_utils.crf --depend nucleo-f103rb\stm32f1xx_ll_utils.d)
I (..\LLDrivers\inc\stm32f1xx_ll_rcc.h)(0x5D10A076)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
I (..\LLDrivers\inc\stm32f1xx_ll_utils.h)(0x5D10A088)
I (..\LLDrivers\inc\stm32f1xx_ll_system.h)(0x5D10A06A)
F (../readme.txt)(0x5D73DDE0)()
F (../Src/system_stm32f1xx.c)(0x5D0B5E70)(-c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Inc -I ..\LLDrivers\inc -I ..\Services -I ..\MyDrivers --C99 -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="529" -D_RTE_ -DSTM32F10X_MD -DSTM32F103xB -DUSE_FULL_LL_DRIVER -DHSE_VALUE="8000000U" -o nucleo-f103rb\system_stm32f1xx.o --omf_browse nucleo-f103rb\system_stm32f1xx.crf --depend nucleo-f103rb\system_stm32f1xx.d)
I (..\Inc\stm32f1xx.h)(0x5D1623CA)
I (..\Inc\stm32f103xb.h)(0x5D1623CA)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h)(0x5D25F326)
I (F:\Keil\ARM\ARMCC\include\stdint.h)(0x5D9B3488)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25F326)
I (C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25F326)
I (..\Inc\system_stm32f1xx.h)(0x5D1623CA)
F (startup_stm32f103xb.s)(0x5CFE6264)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\_Simulateur -IC:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\elies\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 529" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list startup_stm32f103xb.lst --xref -o nucleo-f103rb\startup_stm32f103xb.o --depend nucleo-f103rb\startup_stm32f103xb.d)

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nucleo-f103rb\allure.o: ..\Src\Allure.c

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nucleo-f103rb\anticharvirement.o: ..\Src\AntiCharvirement.c

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nucleo-f103rb\batterie.o: ..\Src\Batterie.c

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nucleo-f103rb\chrono.o: ..\Services\Chrono.c
nucleo-f103rb\chrono.o: ..\Services\Chrono.h
nucleo-f103rb\chrono.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\chrono.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\chrono.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\chrono.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\chrono.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\chrono.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\chrono.o: ..\Inc\system_stm32f1xx.h
nucleo-f103rb\chrono.o: ..\MyDrivers\MyTimer.h

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nucleo-f103rb\gouvernail.o: ..\Src\Gouvernail.c

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nucleo-f103rb\heure.o: ..\Src\Heure.c

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nucleo-f103rb\main.o: ../Src/main.c
nucleo-f103rb\main.o: ..\LLDrivers\inc\stm32f1xx_ll_rcc.h
nucleo-f103rb\main.o: ..\Inc\stm32f1xx.h
nucleo-f103rb\main.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\main.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\main.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\main.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\main.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\main.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\main.o: ..\Inc\system_stm32f1xx.h
nucleo-f103rb\main.o: ..\LLDrivers\inc\stm32f1xx_ll_utils.h
nucleo-f103rb\main.o: ..\LLDrivers\inc\stm32f1xx_ll_system.h
nucleo-f103rb\main.o: ..\Services\Chrono.h
nucleo-f103rb\main.o: ..\MyDrivers\MyTimer.h

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@ -0,0 +1,8 @@
nucleo-f103rb\mytimer.o: ..\MyDrivers\MyTimer.c
nucleo-f103rb\mytimer.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\mytimer.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\mytimer.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\mytimer.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\mytimer.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\mytimer.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\mytimer.o: ..\Inc\system_stm32f1xx.h

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MDK-ARM/NUCLEO-F103RB/startup_stm32f103xb.d Normal file
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nucleo-f103rb\startup_stm32f103xb.o: startup_stm32f103xb.s

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nucleo-f103rb\stm32f1xx_it.o: ../Src/stm32f1xx_it.c
nucleo-f103rb\stm32f1xx_it.o: ../Inc/stm32f1xx_it.h
nucleo-f103rb\stm32f1xx_it.o: ../Inc/main.h
nucleo-f103rb\stm32f1xx_it.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h

0
NUCLEO-F103RB/stm32f1xx_ll_adc.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_adc.d
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0
NUCLEO-F103RB/stm32f1xx_ll_crc.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_crc.d
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0
NUCLEO-F103RB/stm32f1xx_ll_dac.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dac.d
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0
NUCLEO-F103RB/stm32f1xx_ll_dma.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dma.d
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0
NUCLEO-F103RB/stm32f1xx_ll_exti.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_exti.d
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0
NUCLEO-F103RB/stm32f1xx_ll_gpio.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_gpio.d
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0
NUCLEO-F103RB/stm32f1xx_ll_i2c.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_i2c.d
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0
NUCLEO-F103RB/stm32f1xx_ll_pwr.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_pwr.d
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@ -0,0 +1,10 @@
nucleo-f103rb\stm32f1xx_ll_rcc.o: ..\LLDrivers\src\stm32f1xx_ll_rcc.c
nucleo-f103rb\stm32f1xx_ll_rcc.o: ..\LLDrivers\inc\stm32f1xx_ll_rcc.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: ..\Inc\stm32f1xx.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\stm32f1xx_ll_rcc.o: ..\Inc\system_stm32f1xx.h

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NUCLEO-F103RB/stm32f1xx_ll_rtc.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_rtc.d
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0
NUCLEO-F103RB/stm32f1xx_ll_spi.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_spi.d
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2
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@ -0,0 +1,2 @@
nucleo-f103rb\stm32f1xx_ll_tim.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
nucleo-f103rb\stm32f1xx_ll_tim.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h

0
NUCLEO-F103RB/stm32f1xx_ll_usart.d → MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_usart.d
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nucleo-f103rb\stm32f1xx_ll_utils.o: ..\LLDrivers\src\stm32f1xx_ll_utils.c
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\LLDrivers\inc\stm32f1xx_ll_rcc.h
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\Inc\stm32f1xx.h
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\stm32f1xx_ll_utils.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\stm32f1xx_ll_utils.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\stm32f1xx_ll_utils.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\stm32f1xx_ll_utils.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\stm32f1xx_ll_utils.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\Inc\system_stm32f1xx.h
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\LLDrivers\inc\stm32f1xx_ll_utils.h
nucleo-f103rb\stm32f1xx_ll_utils.o: ..\LLDrivers\inc\stm32f1xx_ll_system.h

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nucleo-f103rb\system_stm32f1xx.o: ../Src/system_stm32f1xx.c
nucleo-f103rb\system_stm32f1xx.o: ..\Inc\stm32f1xx.h
nucleo-f103rb\system_stm32f1xx.o: ..\Inc\stm32f103xb.h
nucleo-f103rb\system_stm32f1xx.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm3.h
nucleo-f103rb\system_stm32f1xx.o: F:\Keil\ARM\ARMCC\Bin\..\include\stdint.h
nucleo-f103rb\system_stm32f1xx.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
nucleo-f103rb\system_stm32f1xx.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
nucleo-f103rb\system_stm32f1xx.o: C:\Users\elies\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
nucleo-f103rb\system_stm32f1xx.o: ..\Inc\system_stm32f1xx.h

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nucleo-f103rb\transmission.o: ..\Src\Transmission.c

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nucleo-f103rb\voile.o: ..\Src\Voile.c

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nucleo-f103rb\voilier.o: ..\Src\Voilier.c

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Project.uvoptx → MDK-ARM/Project.uvoptx
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@ -75,7 +75,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>5</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>6</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -128,7 +130,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=100,127,658,622,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=100,127,658,622,0)(121=-1,-1,-1,-1,0)(122=348,235,769,640,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -148,50 +150,10 @@
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U-O142 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
<Name>-U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>47</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219058</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\47</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>44</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219052</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\44</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>Main_Time</ItemText>
</Ww>
</WatchWindow1>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
@ -230,8 +192,13 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>0</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
@ -293,7 +260,7 @@
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
@ -319,6 +286,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -336,7 +305,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=120,153,415,450,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=896,89,1317,516,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=248,17,842,768,0)(131=521,17,1115,768,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=251,288,699,702,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -373,20 +342,32 @@
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>46</LineNumber>
<LineNumber>99</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219406</Address>
<Address>134218304</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<Filename>..\MyDrivers\MyTimer.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\46</Expression>
<Expression>\\NUCLEO_F103RB\../MyDrivers/MyTimer.c\99</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>Chrono_Time</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>USART1</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
@ -425,8 +406,20 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<LogicAnalyzers>
<Wi>
<IntNumber>0</IntNumber>
<FirstString>((TIM_TypeDef *)(0x40000000UL + 0x00000000UL))-&gt;CNT</FirstString>
<SecondString>FF0000000000000000000000000000000000594000000000000000000000000000000000282854494D5F54797065446566202A292830783430303030303030554C202B2030783030303030303030554C29292D3E434E5400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500000001000000000000000000F03F1000000000000000000000000000000000000000B6020008</SecondString>
</Wi>
</LogicAnalyzers>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>0</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
@ -435,7 +428,7 @@
</Target>
<Group>
<GroupName>User Application</GroupName>
<GroupName>User Services</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
@ -447,28 +440,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Src/main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User Services</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Services\Chrono.c</PathWithFileName>
<FilenameWithoutPath>Chrono.c</FilenameWithoutPath>
<PathWithFileName>..\Src\Voilier.c</PathWithFileName>
<FilenameWithoutPath>Voilier.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@ -481,8 +454,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>3</FileNumber>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -492,6 +465,90 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Allure.c</PathWithFileName>
<FilenameWithoutPath>Allure.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\AntiCharvirement.c</PathWithFileName>
<FilenameWithoutPath>AntiCharvirement.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Batterie.c</PathWithFileName>
<FilenameWithoutPath>Batterie.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Gouvernail.c</PathWithFileName>
<FilenameWithoutPath>Gouvernail.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Heure.c</PathWithFileName>
<FilenameWithoutPath>Heure.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Transmission.c</PathWithFileName>
<FilenameWithoutPath>Transmission.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Src\Voile.c</PathWithFileName>
<FilenameWithoutPath>Voile.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@ -501,8 +558,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>4</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -513,8 +570,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>5</FileNumber>
<GroupNumber>3</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -524,18 +581,6 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\LLDrivers\src\stm32f1xx_ll_tim.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_tim.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@ -544,29 +589,17 @@
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../readme.txt</PathWithFileName>
<FilenameWithoutPath>readme.txt</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers/CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>8</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -585,8 +618,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>9</FileNumber>
<GroupNumber>6</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

144
Project.uvprojx → MDK-ARM/Project.uvprojx
View file

@ -10,12 +10,13 @@
<TargetName>NUCLEO-F103RB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>8</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32F103RB</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F1xx_DFP.2.2.0</PackID>
<PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -183,6 +184,7 @@
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -310,7 +312,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@ -323,6 +325,7 @@
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
@ -333,7 +336,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--C99</MiscControls>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U,USE_FULL_ASSERT</Define>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U</Define>
<Undefine></Undefine>
<IncludePath>..\Inc;..\LLDrivers\inc;..\Services;..\MyDrivers</IncludePath>
</VariousControls>
@ -376,23 +379,13 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>User Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>../Src/main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>User Services</GroupName>
<Files>
<File>
<FileName>Chrono.c</FileName>
<FileName>Voilier.c</FileName>
<FileType>1</FileType>
<FilePath>..\Services\Chrono.c</FilePath>
<FilePath>..\Src\Voilier.c</FilePath>
</File>
</Files>
</Group>
@ -404,6 +397,41 @@
<FileType>1</FileType>
<FilePath>..\MyDrivers\MyTimer.c</FilePath>
</File>
<File>
<FileName>Allure.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Allure.c</FilePath>
</File>
<File>
<FileName>AntiCharvirement.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\AntiCharvirement.c</FilePath>
</File>
<File>
<FileName>Batterie.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Batterie.c</FilePath>
</File>
<File>
<FileName>Gouvernail.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Gouvernail.c</FilePath>
</File>
<File>
<FileName>Heure.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Heure.c</FilePath>
</File>
<File>
<FileName>Transmission.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Transmission.c</FilePath>
</File>
<File>
<FileName>Voile.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Voile.c</FilePath>
</File>
</Files>
</Group>
<Group>
@ -419,22 +447,10 @@
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_utils.c</FilePath>
</File>
<File>
<FileName>stm32f1xx_ll_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_tim.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Doc</GroupName>
<Files>
<File>
<FileName>readme.txt</FileName>
<FileType>5</FileType>
<FilePath>../readme.txt</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers/CMSIS</GroupName>
@ -465,12 +481,13 @@
<TargetName>Simulateur</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32F103RB</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F1xx_DFP.2.2.0</PackID>
<PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -638,6 +655,7 @@
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -765,7 +783,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@ -778,6 +796,7 @@
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
@ -788,7 +807,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--C99</MiscControls>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U,USE_FULL_ASSERT</Define>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U</Define>
<Undefine></Undefine>
<IncludePath>..\Inc;..\LLDrivers\inc;..\Services;..\MyDrivers</IncludePath>
</VariousControls>
@ -831,23 +850,13 @@
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>User Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>../Src/main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>User Services</GroupName>
<Files>
<File>
<FileName>Chrono.c</FileName>
<FileName>Voilier.c</FileName>
<FileType>1</FileType>
<FilePath>..\Services\Chrono.c</FilePath>
<FilePath>..\Src\Voilier.c</FilePath>
</File>
</Files>
</Group>
@ -859,6 +868,41 @@
<FileType>1</FileType>
<FilePath>..\MyDrivers\MyTimer.c</FilePath>
</File>
<File>
<FileName>Allure.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Allure.c</FilePath>
</File>
<File>
<FileName>AntiCharvirement.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\AntiCharvirement.c</FilePath>
</File>
<File>
<FileName>Batterie.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Batterie.c</FilePath>
</File>
<File>
<FileName>Gouvernail.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Gouvernail.c</FilePath>
</File>
<File>
<FileName>Heure.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Heure.c</FilePath>
</File>
<File>
<FileName>Transmission.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Transmission.c</FilePath>
</File>
<File>
<FileName>Voile.c</FileName>
<FileType>1</FileType>
<FilePath>..\Src\Voile.c</FilePath>
</File>
</Files>
</Group>
<Group>
@ -874,22 +918,10 @@
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_utils.c</FilePath>
</File>
<File>
<FileName>stm32f1xx_ll_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_tim.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Doc</GroupName>
<Files>
<File>
<FileName>readme.txt</FileName>
<FileType>5</FileType>
<FilePath>../readme.txt</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers/CMSIS</GroupName>

3
RTE/_NUCLEO-F103RB/RTE_Components.h → MDK-ARM/RTE/_NUCLEO-F103RB/RTE_Components.h
View file

@ -1,6 +1,6 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Project'
@ -17,4 +17,5 @@
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

0
RTE/_Simulateur/RTE_Components.h → MDK-ARM/RTE/_Simulateur/RTE_Components.h
View file

0
startup_stm32f103xb.s → MDK-ARM/startup_stm32f103xb.s
View file

109
MyDrivers/MyTimer.c Normal file
View file

@ -0,0 +1,109 @@
// TOUT A FAIRE !! //
/*
indispensable pour pouvoir adresser les registres des périphériques.
Rem : OBLIGATION d'utiliser les définitions utiles contenues dans ce fichier (ex : TIM_CR1_CEN, RCC_APB1ENR_TIM2EN ...)
pour une meilleure lisibilité du code.
Pour les masques, utiliser également les définitions proposée
Rappel : pour mettre à 1 , reg = reg | Mask (ou Mask est le représente le ou les bits à positionner à 1)
pour mettre à 0 , reg = reg&~ Mask (ou Mask est le représente le ou les bits à positionner à 0)
*/
#include "stm32f103xb.h"
void (* pTIM1_Overflow) (void); //Pointeurs de fonctions que l'on appelle dans le handler et définis dans IT_Conf
void (* pTIM2_Overflow) (void);
void (* pTIM3_Overflow) (void);
void (* pTIM4_Overflow) (void);
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc){
//Activation horloge selon timer utilisé
if (Timer == TIM1){
RCC->APB2ENR = RCC->APB2ENR | RCC_APB2ENR_TIM1EN;
}
if (Timer == TIM2){
RCC->APB1ENR = RCC->APB1ENR | RCC_APB1ENR_TIM2EN;
}
else if (Timer == TIM3){
RCC->APB1ENR = RCC->APB1ENR | RCC_APB1ENR_TIM3EN;
}
else{
RCC->APB1ENR = RCC->APB1ENR | RCC_APB1ENR_TIM4EN;
}
Timer->ARR = Arr;
Timer->PSC = Psc;
}
void MyTimer_Start(TIM_TypeDef * Timer){
//Mise à 1 du bit CEN de CR1 = activation timer
Timer->CR1 |= 0x1;
}
void MyTimer_Stop(TIM_TypeDef * Timer){
//Mise à 0 du bit CEN de CR1 = stop timer
Timer->CR1 &= ~0x1;
}
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio){
Timer->DIER |= 0x1; //Enable Update IT (débordement du timer)
if (Timer == TIM1){
NVIC->IP[TIM1_UP_IRQn] = Prio<<4;
NVIC->ISER[0] |= 0x1<<TIM1_UP_IRQn;
pTIM1_Overflow = IT_function;
}
if (Timer == TIM2){
NVIC->IP[TIM2_IRQn] = Prio<<4;
NVIC->ISER[0] |= 0x1<<TIM2_IRQn;
pTIM2_Overflow = IT_function;
}
if (Timer == TIM3){
NVIC->IP[TIM3_IRQn] = Prio<<4;
NVIC->ISER[0] |= 0x1<<TIM3_IRQn;
pTIM3_Overflow = IT_function;
}
if (Timer == TIM4){
NVIC->IP[TIM4_IRQn] = Prio<<4;
NVIC->ISER[0] |= 0x1<<TIM4_IRQn;
pTIM4_Overflow = IT_function;
}
}
void MyTimer_IT_Disable(TIM_TypeDef * Timer){
Timer->DIER |= 0x0; //Disable Update IT (débordement du timer)
if (Timer == TIM1){
NVIC->ISER[0] |= 0x0<<TIM1_UP_IRQn;
}
if (Timer == TIM2){
NVIC->ISER[0] |= 0x0<<TIM2_IRQn;
}
if (Timer == TIM3){
NVIC->ISER[0] |= 0x0<<TIM3_IRQn;
}
if (Timer == TIM4){
NVIC->ISER[0] |= 0x0<<TIM4_IRQn;
}
}
void TIM1_UP_IRQHandler(void){ //Fonctions qui sont les handler appelée par le NVIC lors des interruptions
(*pTIM1_Overflow)(); //Contien le faux "handler" qui lui contient des instructions
TIM1->SR = 0x0;
}
void TIM2_IRQHandler(void){
(*pTIM2_Overflow)();
TIM2->SR = 0x0;
}
void TIM3_IRQHandler(void){
(*pTIM3_Overflow)();
TIM3->SR = 0x0;
}
void TIM4_IRQHandler(void){
(*pTIM4_Overflow)();
TIM4->SR = 0x0;
}

70
MyDrivers/MyTimer.h Normal file
View file

@ -0,0 +1,70 @@
// RIEN A MODIFIER //
#ifndef MY_TIMER_H
#define MY_TIMER_H
/*
Driver pour Timer 1 à 4 du STM32F103RB
*/
#include "stm32f103xb.h"
/**
* @brief Active l'horloge et règle l'ARR et le PSC du timer visé
* @note Fonction à lancer avant toute autre. Le timer n'est pas encore lancé (voir MyTimerStart)
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur à placer dans ARR
* int Psc : valeur à placer dans PSC
* @retval None
*/
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc);
/**
* @brief Démarre le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Start(TIM_TypeDef * Timer);
/**
* @brief Arrêt le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Stop(TIM_TypeDef * Timer);
/**
* @brief Configure le Timer considéré en interruption sur débordement.
* @note A ce stade, les interruptions ne sont pas validés (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction à lancer sur interruption
* int Prio : priorité associée à l'interruption
* @retval None
*/
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio);
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Enable(TIM_TypeDef * Timer); //On fait tt dans IT_Conf
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Disable(TIM_TypeDef * Timer);
#endif

61
NUCLEO-F103RB/NUCLEO-F103RB.build_log.htm
View file

@ -1,61 +0,0 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.23.0.0
Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Thierry Thierry, INSA, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.23
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 4 (build 422)
Assembler: Armasm.exe V5.06 update 4 (build 422)
Linker/Locator: ArmLink.exe V5.06 update 4 (build 422)
Library Manager: ArmAr.exe V5.06 update 4 (build 422)
Hex Converter: FromElf.exe V5.06 update 4 (build 422)
CPU DLL: SARMCM3.DLL V5.23
Dialog DLL: DARMSTM.DLL V1.68.0.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V2.0.18.0
Dialog DLL: TARMSTM.DLL V1.66.0.0
<h2>Project:</h2>
D:\Thierry\2019_2020\Periph\PrepaPeriph\ProjetsKEIL\Nouveau dossier\DerLL\ProjKEIL_Chrono_TIM_IT_LL\MDK-ARM\Project.uvprojx
Project File Date: 09/20/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 4 (build 422)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'Simulateur'
compiling Chrono.c...
compiling MyTimer.c...
compiling main.c...
compiling stm32f1xx_ll_rcc.c...
compiling stm32f1xx_ll_utils.c...
assembling startup_stm32f103xb.s...
compiling stm32f1xx_ll_tim.c...
compiling system_stm32f1xx.c...
linking...
Program Size: Code=1456 RO-data=268 RW-data=28 ZI-data=1028
"NUCLEO-F103RB\NUCLEO-F103RB.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.0.1.pack
ARM::CMSIS:CORE:5.0.1
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.0.1
<h2>Collection of Component include folders:</h2>
.\RTE\_Simulateur
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.0.1
Build Time Elapsed: 00:00:04
</pre>
</body>
</html>

535
NUCLEO-F103RB/NUCLEO-F103RB.map
View file

@ -1,535 +0,0 @@
Component: ARM Compiler 5.06 update 4 (build 422) Tool: armlink [4d35d2]
==============================================================================
Section Cross References
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_Init1msTick) for LL_Init1msTick
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
main.o(i.main) refers to main.o(i.SystemClock_Config) for SystemClock_Config
main.o(i.main) refers to chrono.o(i.Chrono_Conf) for Chrono_Conf
main.o(i.main) refers to chrono.o(i.Chrono_Start) for Chrono_Start
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_Conf) for MyTimer_Conf
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_IT_Conf) for MyTimer_IT_Conf
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_IT_Enable) for MyTimer_IT_Enable
chrono.o(i.Chrono_Conf) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Conf) refers to chrono.o(i.Chrono_Task_10ms) for Chrono_Task_10ms
chrono.o(i.Chrono_Read) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Reset) refers to mytimer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Reset) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Start) refers to mytimer.o(i.MyTimer_Start) for MyTimer_Start
chrono.o(i.Chrono_Start) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Stop) refers to mytimer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Stop) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Task_10ms) refers to chrono.o(.data) for Chrono_Time
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_APB1_GRP1_EnableClock) for LL_APB1_GRP1_EnableClock
mytimer.o(i.MyTimer_Conf) refers to stm32f1xx_ll_tim.o(i.LL_TIM_Init) for LL_TIM_Init
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
mytimer.o(i.MyTimer_IT_Conf) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_IT_Conf) refers to mytimer.o(.data) for Ptr_ItFct_TIM1
mytimer.o(i.MyTimer_IT_Disable) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_Stop) refers to mytimer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM1
mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM2
mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM3
mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM4
stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) for RCC_GetPCLK1ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady) for LL_RCC_HSE_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady) for LL_RCC_HSI_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency) for UTILS_SetFlashLatency
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_tim.o(i.IC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC4Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset) for LL_APB1_GRP1_ForceReset
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset) for LL_APB1_GRP1_ReleaseReset
stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC1Config) for IC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC2Config) for IC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC3Config) for IC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC4Config) for IC4Config
stm32f1xx_ll_tim.o(i.LL_TIM_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC1Config) for OC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC2Config) for OC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC3Config) for OC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC4Config) for OC4Config
stm32f1xx_ll_tim.o(i.OC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.OC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC4Config) refers to main.o(i.assert_failed) for assert_failed
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.data) for SystemCoreClock
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(STACK) for __initial_sp
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(.text) for Reset_Handler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
startup_stm32f103xb.o(.text) refers to system_stm32f1xx.o(i.SystemInit) for SystemInit
startup_stm32f103xb.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main
entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main
init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
==============================================================================
Removing Unused input sections from the image.
Removing main.o(.rev16_text), (4 bytes).
Removing main.o(.revsh_text), (4 bytes).
Removing main.o(.rrx_text), (6 bytes).
Removing chrono.o(.rev16_text), (4 bytes).
Removing chrono.o(.revsh_text), (4 bytes).
Removing chrono.o(.rrx_text), (6 bytes).
Removing chrono.o(i.Chrono_Read), (8 bytes).
Removing chrono.o(i.Chrono_Reset), (32 bytes).
Removing chrono.o(i.Chrono_Stop), (16 bytes).
Removing mytimer.o(.rev16_text), (4 bytes).
Removing mytimer.o(.revsh_text), (4 bytes).
Removing mytimer.o(.rrx_text), (6 bytes).
Removing mytimer.o(i.MyTimer_IT_Disable), (12 bytes).
Removing mytimer.o(i.MyTimer_Stop), (12 bytes).
Removing mytimer.o(.constdata), (35 bytes).
Removing stm32f1xx_ll_rcc.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit), (152 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq), (124 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq), (120 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq), (32 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq), (60 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS), (88 bytes).
Removing stm32f1xx_ll_utils.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE), (260 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI), (104 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS), (28 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_mDelay), (40 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem), (416 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency), (228 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency), (80 bytes).
Removing stm32f1xx_ll_tim.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_tim.o(i.IC1Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC2Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC3Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.IC4Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init), (312 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_DeInit), (192 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init), (688 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_StructInit), (36 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init), (396 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_StructInit), (12 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2), (4 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_StructInit), (20 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.OC1Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC2Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC3Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC4Config), (372 bytes).
Removing stm32f1xx_ll_tim.o(.constdata), (35 bytes).
Removing system_stm32f1xx.o(.rev16_text), (4 bytes).
Removing system_stm32f1xx.o(.revsh_text), (4 bytes).
Removing system_stm32f1xx.o(.rrx_text), (6 bytes).
Removing system_stm32f1xx.o(i.SystemCoreClockUpdate), (164 bytes).
Removing system_stm32f1xx.o(.constdata), (24 bytes).
Removing startup_stm32f103xb.o(HEAP), (512 bytes).
75 unused section(s) (total 7894 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../Src/main.c 0x00000000 Number 0 main.o ABSOLUTE
../Src/system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\MyDrivers\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
..\Services\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
..\Src\main.c 0x00000000 Number 0 main.o ABSOLUTE
..\Src\system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\\MyDrivers\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
..\\Services\\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
init.s 0x00000000 Number 0 init.o ABSOLUTE
startup_stm32f103xb.s 0x00000000 Number 0 startup_stm32f103xb.o ABSOLUTE
RESET 0x08000000 Section 236 startup_stm32f103xb.o(RESET)
.ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
.ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
.ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
.ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
.ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
.ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
.ARM.Collect$$$$0000000D 0x080000fc Section 0 entry10a.o(.ARM.Collect$$$$0000000D)
.ARM.Collect$$$$0000000F 0x080000fc Section 0 entry11a.o(.ARM.Collect$$$$0000000F)
.ARM.Collect$$$$00002712 0x080000fc Section 4 entry2.o(.ARM.Collect$$$$00002712)
__lit__00000000 0x080000fc Data 4 entry2.o(.ARM.Collect$$$$00002712)
.text 0x08000100 Section 36 startup_stm32f103xb.o(.text)
.text 0x08000124 Section 36 init.o(.text)
i.Chrono_Conf 0x08000148 Section 0 chrono.o(i.Chrono_Conf)
i.Chrono_Start 0x0800018c Section 0 chrono.o(i.Chrono_Start)
i.Chrono_Task_10ms 0x0800019c Section 0 chrono.o(i.Chrono_Task_10ms)
i.LL_APB1_GRP1_EnableClock 0x080001e4 Section 0 mytimer.o(i.LL_APB1_GRP1_EnableClock)
LL_APB1_GRP1_EnableClock 0x080001e5 Thumb Code 24 mytimer.o(i.LL_APB1_GRP1_EnableClock)
i.LL_Init1msTick 0x08000200 Section 0 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
i.LL_SetSystemCoreClock 0x0800021c Section 0 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
i.LL_TIM_ClearFlag_UPDATE 0x08000228 Section 0 mytimer.o(i.LL_TIM_ClearFlag_UPDATE)
LL_TIM_ClearFlag_UPDATE 0x08000229 Thumb Code 8 mytimer.o(i.LL_TIM_ClearFlag_UPDATE)
i.LL_TIM_DisableCounter 0x08000230 Section 0 mytimer.o(i.LL_TIM_DisableCounter)
LL_TIM_DisableCounter 0x08000231 Thumb Code 10 mytimer.o(i.LL_TIM_DisableCounter)
i.LL_TIM_DisableIT_UPDATE 0x0800023a Section 0 mytimer.o(i.LL_TIM_DisableIT_UPDATE)
LL_TIM_DisableIT_UPDATE 0x0800023b Thumb Code 10 mytimer.o(i.LL_TIM_DisableIT_UPDATE)
i.LL_TIM_Init 0x08000244 Section 0 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
i.MyTimer_Conf 0x08000358 Section 0 mytimer.o(i.MyTimer_Conf)
i.MyTimer_IT_Conf 0x080003dc Section 0 mytimer.o(i.MyTimer_IT_Conf)
i.MyTimer_IT_Enable 0x0800049c Section 0 mytimer.o(i.MyTimer_IT_Enable)
i.MyTimer_Start 0x080004aa Section 0 mytimer.o(i.MyTimer_Start)
i.SystemClock_Config 0x080004b8 Section 0 main.o(i.SystemClock_Config)
i.SystemInit 0x080005a8 Section 0 system_stm32f1xx.o(i.SystemInit)
i.TIM1_UP_IRQHandler 0x08000600 Section 0 mytimer.o(i.TIM1_UP_IRQHandler)
i.TIM2_IRQHandler 0x08000618 Section 0 mytimer.o(i.TIM2_IRQHandler)
i.TIM3_IRQHandler 0x08000630 Section 0 mytimer.o(i.TIM3_IRQHandler)
i.TIM4_IRQHandler 0x08000648 Section 0 mytimer.o(i.TIM4_IRQHandler)
i.__scatterload_copy 0x08000660 Section 14 handlers.o(i.__scatterload_copy)
i.__scatterload_null 0x0800066e Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x08000670 Section 14 handlers.o(i.__scatterload_zeroinit)
i.assert_failed 0x0800067e Section 0 main.o(i.assert_failed)
i.main 0x08000684 Section 0 main.o(i.main)
.data 0x20000000 Section 8 chrono.o(.data)
Chrono_Time 0x20000000 Data 3 chrono.o(.data)
Chrono_Timer 0x20000004 Data 4 chrono.o(.data)
.data 0x20000008 Section 16 mytimer.o(.data)
.data 0x20000018 Section 4 system_stm32f1xx.o(.data)
STACK 0x20000020 Section 1024 startup_stm32f103xb.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__decompress - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_microlib_exit - Undefined Weak Reference
__Vectors_Size 0x000000ec Number 0 startup_stm32f103xb.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_stm32f103xb.o(RESET)
__Vectors_End 0x080000ec Data 0 startup_stm32f103xb.o(RESET)
__main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
_main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
_main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
__main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
_main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
_main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
_main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
__rt_final_cpp 0x080000fd Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D)
__rt_final_exit 0x080000fd Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F)
Reset_Handler 0x08000101 Thumb Code 8 startup_stm32f103xb.o(.text)
NMI_Handler 0x08000109 Thumb Code 2 startup_stm32f103xb.o(.text)
HardFault_Handler 0x0800010b Thumb Code 2 startup_stm32f103xb.o(.text)
MemManage_Handler 0x0800010d Thumb Code 2 startup_stm32f103xb.o(.text)
BusFault_Handler 0x0800010f Thumb Code 2 startup_stm32f103xb.o(.text)
UsageFault_Handler 0x08000111 Thumb Code 2 startup_stm32f103xb.o(.text)
SVC_Handler 0x08000113 Thumb Code 2 startup_stm32f103xb.o(.text)
DebugMon_Handler 0x08000115 Thumb Code 2 startup_stm32f103xb.o(.text)
PendSV_Handler 0x08000117 Thumb Code 2 startup_stm32f103xb.o(.text)
SysTick_Handler 0x08000119 Thumb Code 2 startup_stm32f103xb.o(.text)
ADC1_2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_RX1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_SCE_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel6_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel7_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI15_10_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI9_5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
PVD_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RCC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_Alarm_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TAMPER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_BRK_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USBWakeUp_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_HP_CAN1_TX_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_LP_CAN1_RX0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
WWDG_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
__scatterload 0x08000125 Thumb Code 28 init.o(.text)
__scatterload_rt2 0x08000125 Thumb Code 0 init.o(.text)
Chrono_Conf 0x08000149 Thumb Code 54 chrono.o(i.Chrono_Conf)
Chrono_Start 0x0800018d Thumb Code 12 chrono.o(i.Chrono_Start)
Chrono_Task_10ms 0x0800019d Thumb Code 68 chrono.o(i.Chrono_Task_10ms)
LL_Init1msTick 0x08000201 Thumb Code 28 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
LL_SetSystemCoreClock 0x0800021d Thumb Code 6 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
LL_TIM_Init 0x08000245 Thumb Code 228 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
MyTimer_Conf 0x08000359 Thumb Code 118 mytimer.o(i.MyTimer_Conf)
MyTimer_IT_Conf 0x080003dd Thumb Code 158 mytimer.o(i.MyTimer_IT_Conf)
MyTimer_IT_Enable 0x0800049d Thumb Code 14 mytimer.o(i.MyTimer_IT_Enable)
MyTimer_Start 0x080004ab Thumb Code 14 mytimer.o(i.MyTimer_Start)
SystemClock_Config 0x080004b9 Thumb Code 226 main.o(i.SystemClock_Config)
SystemInit 0x080005a9 Thumb Code 70 system_stm32f1xx.o(i.SystemInit)
TIM1_UP_IRQHandler 0x08000601 Thumb Code 16 mytimer.o(i.TIM1_UP_IRQHandler)
TIM2_IRQHandler 0x08000619 Thumb Code 18 mytimer.o(i.TIM2_IRQHandler)
TIM3_IRQHandler 0x08000631 Thumb Code 16 mytimer.o(i.TIM3_IRQHandler)
TIM4_IRQHandler 0x08000649 Thumb Code 16 mytimer.o(i.TIM4_IRQHandler)
__scatterload_copy 0x08000661 Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x0800066f Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x08000671 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
assert_failed 0x0800067f Thumb Code 4 main.o(i.assert_failed)
main 0x08000685 Thumb Code 18 main.o(i.main)
Region$$Table$$Base 0x0800069c Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x080006bc Number 0 anon$$obj.o(Region$$Table)
Ptr_ItFct_TIM1 0x20000008 Data 4 mytimer.o(.data)
Ptr_ItFct_TIM2 0x2000000c Data 4 mytimer.o(.data)
Ptr_ItFct_TIM3 0x20000010 Data 4 mytimer.o(.data)
Ptr_ItFct_TIM4 0x20000014 Data 4 mytimer.o(.data)
SystemCoreClock 0x20000018 Data 4 system_stm32f1xx.o(.data)
__initial_sp 0x20000420 Data 0 startup_stm32f103xb.o(STACK)
==============================================================================
Memory Map of the image
Image Entry point : 0x080000ed
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000006d8, Max: 0x00020000, ABSOLUTE)
Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x000006bc, Max: 0x00020000, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x08000000 0x000000ec Data RO 624 RESET startup_stm32f103xb.o
0x080000ec 0x00000000 Code RO 629 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
0x080000ec 0x00000004 Code RO 632 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
0x080000f0 0x00000004 Code RO 635 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
0x080000f4 0x00000000 Code RO 637 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
0x080000f4 0x00000000 Code RO 639 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
0x080000f4 0x00000008 Code RO 640 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
0x080000fc 0x00000000 Code RO 642 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o)
0x080000fc 0x00000000 Code RO 644 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o)
0x080000fc 0x00000004 Code RO 633 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
0x08000100 0x00000024 Code RO 625 .text startup_stm32f103xb.o
0x08000124 0x00000024 Code RO 646 .text mc_w.l(init.o)
0x08000148 0x00000044 Code RO 78 i.Chrono_Conf chrono.o
0x0800018c 0x00000010 Code RO 81 i.Chrono_Start chrono.o
0x0800019c 0x00000048 Code RO 83 i.Chrono_Task_10ms chrono.o
0x080001e4 0x0000001c Code RO 137 i.LL_APB1_GRP1_EnableClock mytimer.o
0x08000200 0x0000001c Code RO 332 i.LL_Init1msTick stm32f1xx_ll_utils.o
0x0800021c 0x0000000c Code RO 339 i.LL_SetSystemCoreClock stm32f1xx_ll_utils.o
0x08000228 0x00000008 Code RO 138 i.LL_TIM_ClearFlag_UPDATE mytimer.o
0x08000230 0x0000000a Code RO 139 i.LL_TIM_DisableCounter mytimer.o
0x0800023a 0x0000000a Code RO 140 i.LL_TIM_DisableIT_UPDATE mytimer.o
0x08000244 0x00000114 Code RO 444 i.LL_TIM_Init stm32f1xx_ll_tim.o
0x08000358 0x00000084 Code RO 141 i.MyTimer_Conf mytimer.o
0x080003dc 0x000000c0 Code RO 142 i.MyTimer_IT_Conf mytimer.o
0x0800049c 0x0000000e Code RO 144 i.MyTimer_IT_Enable mytimer.o
0x080004aa 0x0000000e Code RO 145 i.MyTimer_Start mytimer.o
0x080004b8 0x000000f0 Code RO 4 i.SystemClock_Config main.o
0x080005a8 0x00000058 Code RO 589 i.SystemInit system_stm32f1xx.o
0x08000600 0x00000018 Code RO 147 i.TIM1_UP_IRQHandler mytimer.o
0x08000618 0x00000018 Code RO 148 i.TIM2_IRQHandler mytimer.o
0x08000630 0x00000018 Code RO 149 i.TIM3_IRQHandler mytimer.o
0x08000648 0x00000018 Code RO 150 i.TIM4_IRQHandler mytimer.o
0x08000660 0x0000000e Code RO 650 i.__scatterload_copy mc_w.l(handlers.o)
0x0800066e 0x00000002 Code RO 651 i.__scatterload_null mc_w.l(handlers.o)
0x08000670 0x0000000e Code RO 652 i.__scatterload_zeroinit mc_w.l(handlers.o)
0x0800067e 0x00000004 Code RO 5 i.assert_failed main.o
0x08000682 0x00000002 PAD
0x08000684 0x00000018 Code RO 6 i.main main.o
0x0800069c 0x00000020 Data RO 648 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000420, Max: 0x00005000, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x20000000 0x00000008 Data RW 84 .data chrono.o
0x20000008 0x00000010 Data RW 152 .data mytimer.o
0x20000018 0x00000004 Data RW 591 .data system_stm32f1xx.o
0x2000001c 0x00000004 PAD
0x20000020 0x00000400 Zero RW 622 STACK startup_stm32f103xb.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
156 22 0 8 0 2192 chrono.o
268 20 0 0 0 357020 main.o
504 82 0 16 0 59517 mytimer.o
36 8 236 0 1024 820 startup_stm32f103xb.o
276 48 0 0 0 29110 stm32f1xx_ll_tim.o
40 6 0 0 0 2213 stm32f1xx_ll_utils.o
88 18 0 4 0 1287 system_stm32f1xx.o
----------------------------------------------------------------------
1370 204 268 28 1028 452159 Object Totals
0 0 32 0 0 0 (incl. Generated)
2 0 0 0 4 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
0 0 0 0 0 0 entry.o
0 0 0 0 0 0 entry10a.o
0 0 0 0 0 0 entry11a.o
8 4 0 0 0 0 entry2.o
4 0 0 0 0 0 entry5.o
0 0 0 0 0 0 entry7b.o
0 0 0 0 0 0 entry8b.o
8 4 0 0 0 0 entry9a.o
30 0 0 0 0 0 handlers.o
36 8 0 0 0 68 init.o
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
86 16 0 0 0 68 mc_w.l
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
1456 220 268 28 1028 451339 Grand Totals
1456 220 268 28 1028 451339 ELF Image Totals
1456 220 268 28 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 1724 ( 1.68kB)
Total RW Size (RW Data + ZI Data) 1056 ( 1.03kB)
Total ROM Size (Code + RO Data + RW Data) 1752 ( 1.71kB)
==============================================================================

BIN
NUCLEO-F103RB/mytimer.crf
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BIN
NUCLEO-F103RB/stm32f1xx_it.crf
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BIN
NUCLEO-F103RB/stm32f1xx_ll_tim.crf
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0
Headers/Allure.h → Src/Allure.h
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0
Headers/AntiChavirement.h → Src/AntiChavirement.h
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0
Headers/Batterie.h → Src/Batterie.h
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0
Headers/Gouvernail.h → Src/Gouvernail.h
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0
Headers/Heure.h → Src/Heure.h
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182
Src/MyTimer.c Normal file
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// TOUT A FAIRE !! //
/*
indispensable pour pouvoir adresser les registres des périphériques.
Rem : OBLIGATION d'utiliser les définitions utiles contenues dans ce fichier (ex : TIM_CR1_CEN, RCC_APB1ENR_TIM2EN ...)
pour une meilleure lisibilité du code.
Pour les masques, utiliser également les définitions proposée
Rappel : pour mettre à 1 , reg = reg | Mask (ou Mask est le représente le ou les bits à positionner à 1)
pour mettre à 0 , reg = reg&~ Mask (ou Mask est le représente le ou les bits à positionner à 0)
*/
#include "MyTimer.h"
#include "stm32f1xx_ll_bus.h" // Pour l'activation des horloges
#include "stm32f1xx_ll_tim.h"
// variable pointeur de fonction permettant de mémoriser le callback à appeler depuis
// le handler d'IT
void (*Ptr_ItFct_TIM1)(void);
void (*Ptr_ItFct_TIM2)(void);
void (*Ptr_ItFct_TIM3)(void);
void (*Ptr_ItFct_TIM4)(void);
/**
* @brief Active l'horloge et règle l'ARR et le PSC du timer visé
* @note Fonction à lancer avant toute autre. Le timer n'est pas encore lancé (voir MyTimerStart)
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur à placer dans ARR
* int Psc : valeur à placer dans PSC
* @retval None
*/
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc)
{
LL_TIM_InitTypeDef My_LL_Tim_Init_Struct;
// Validation horloge locale
if (Timer==TIM1) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
else if (Timer==TIM2) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
else if (Timer==TIM3) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
else LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4);
// chargement structure Arr, Psc, Up Count
My_LL_Tim_Init_Struct.Autoreload=Arr;
My_LL_Tim_Init_Struct.Prescaler=Psc;
My_LL_Tim_Init_Struct.ClockDivision=LL_TIM_CLOCKDIVISION_DIV1;
My_LL_Tim_Init_Struct.CounterMode=LL_TIM_COUNTERMODE_UP;
My_LL_Tim_Init_Struct.RepetitionCounter=0;
LL_TIM_Init(Timer,&My_LL_Tim_Init_Struct);
// Blocage IT
LL_TIM_DisableIT_UPDATE(Timer);
// Blocage Timer
LL_TIM_DisableCounter(Timer);
}
/**
* @brief Démarre le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Start(TIM_TypeDef * Timer)
{
LL_TIM_EnableCounter(Timer);
}
/**
* @brief Arrêt le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Stop(TIM_TypeDef * Timer)
{
LL_TIM_DisableCounter(Timer);
}
/**
* @brief Configure le Timer considéré en interruption sur débordement.
* @note A ce stade, les interruptions ne sont pas validés (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction à lancer sur interruption
* int Prio : priorité associée à l'interruption
* @retval None
*/
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio)
{
// affectation de la fonction
if (Timer==TIM1) Ptr_ItFct_TIM1=IT_function;
else if (Timer==TIM2) Ptr_ItFct_TIM2=IT_function;
else if (Timer==TIM3) Ptr_ItFct_TIM3=IT_function;
else Ptr_ItFct_TIM4=IT_function;
// Blocage IT (il faudra la débloquer voir fct suivante)
LL_TIM_DisableIT_UPDATE(Timer);
// validation du canal NVIC
IRQn_Type TIM_irq;
if (Timer==TIM1) TIM_irq=TIM1_UP_IRQn;
else if (Timer==TIM2) TIM_irq=TIM2_IRQn;
else if (Timer==TIM3) TIM_irq=TIM3_IRQn;
else TIM_irq=TIM4_IRQn;
NVIC_SetPriority(TIM_irq, Prio);
NVIC_EnableIRQ(TIM_irq);
}
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Enable(TIM_TypeDef * Timer)
{
LL_TIM_EnableIT_UPDATE(Timer);
}
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Disable(TIM_TypeDef * Timer)
{
LL_TIM_DisableIT_UPDATE(Timer);
}
/*
============ LES INTERRUPTIONS =================================
*/
void TIM1_UP_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM1);
(*Ptr_ItFct_TIM1)();
}
void TIM2_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM2);
(*Ptr_ItFct_TIM2)();
}
void TIM3_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM3);
(*Ptr_ItFct_TIM3)();
}
void TIM4_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM4);
(*Ptr_ItFct_TIM4)();
}

70
Src/MyTimer.h Normal file
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// RIEN A MODIFIER //
#ifndef MY_TIMER_H
#define MY_TIMER_H
/*
Driver pour Timer 1 à 4 du STM32F103RB
*/
#include "stm32f103xb.h"
/**
* @brief Active l'horloge et règle l'ARR et le PSC du timer visé
* @note Fonction à lancer avant toute autre. Le timer n'est pas encore lancé (voir MyTimerStart)
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur à placer dans ARR
* int Psc : valeur à placer dans PSC
* @retval None
*/
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc);
/**
* @brief Démarre le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Start(TIM_TypeDef * Timer);
/**
* @brief Arrêt le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Stop(TIM_TypeDef * Timer);
/**
* @brief Configure le Timer considéré en interruption sur débordement.
* @note A ce stade, les interruptions ne sont pas validés (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction à lancer sur interruption
* int Prio : priorité associée à l'interruption
* @retval None
*/
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio);
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Enable(TIM_TypeDef * Timer);
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Disable(TIM_TypeDef * Timer);
#endif

0
Headers/Transmission.h → Src/Transmission.h
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0
Headers/Voile.h → Src/Voile.h
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Src/Voilier.c Normal file
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int main(){
return 0;
}

419
Src/system_stm32f1xx.c Normal file
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/**
******************************************************************************
* @file system_stm32f1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f1xx_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
* the product used), refer to "HSE_VALUE".
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx_system
* @{
*/
/** @addtogroup STM32F1xx_System_Private_Includes
* @{
*/
#include "stm32f1xx.h"
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t prediv1factor = 0;
#endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
#if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18;
if (pllmull != 0x0D)
{
pllmull += 2;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13 / 2;
}
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
if (prediv1source == 0)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F105xC */
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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User_Services/Voilier.c
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