90 lines
2.7 KiB
VHDL
90 lines
2.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13.07.2021 09:30:08
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-- Design Name:
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-- Module Name: KeyboardDriver - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity KeyboardDriver is
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Generic (Nb_Bits : Natural);
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Port (CLK : in STD_LOGIC;
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Data_read : out STD_LOGIC;
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Data_av : in STD_LOGIC;
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Data : in STD_LOGIC_VECTOR (0 to 6);
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STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_IN_Av : out STD_LOGIC;
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STD_IN_Request : in STD_LOGIC;
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STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_OUT_Av : out STD_LOGIC);
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end KeyboardDriver;
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architecture Behavioral of KeyboardDriver is
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signal intern_value : Natural := 0;
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signal work_in_progress : BOOLEAN := false;
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signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0');
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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STD_IN_Av <= '0';
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STD_OUT_Av <= '0';
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if not(work_in_progress) then
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intern_value <= 0;
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end if;
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if STD_IN_Request = '1' then
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work_in_progress <= true;
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if Data_av = '1' then
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if (Data = "1111111") then
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intern_value <= intern_value / 10;
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STD_OUT <= Zeros & Data;
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STD_OUT_Av <= '1';
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elsif (Data = "0001010") then
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STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits));
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STD_IN_Av <= '1';
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work_in_progress <= false;
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STD_OUT <= Zeros & Data;
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STD_OUT_Av <= '1';
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elsif (Data >= "0110000" and Data <= "0111001") then
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intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6)));
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STD_OUT <= Zeros & Data;
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STD_OUT_Av <= '1';
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end if;
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end if;
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end if;
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end process;
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Data_read <= '0' when STD_IN_Request = '0' else Data_av;
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end Behavioral;
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