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System.vhd 2.5KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 13.04.2021 10:19:15
  6. -- Design Name:
  7. -- Module Name: System - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity System is
  30. Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
  31. sw : in STD_LOGIC_VECTOR (7 downto 0);
  32. btnC : in STD_LOGIC;
  33. CLK : STD_LOGIC);
  34. end System;
  35. architecture Structural of System is
  36. component Pipeline is
  37. Generic (Nb_bits : Natural := 8;
  38. Instruction_En_Memoire_Size : Natural := 29;
  39. Addr_Memoire_Instruction_Size : Natural := 3;
  40. Memoire_Instruction_Size : Natural := 8;
  41. Instruction_Bus_Size : Natural := 5;
  42. Nb_Instructions : Natural := 32;
  43. Nb_Registres : Natural := 16;
  44. Memoire_Size : Natural := 32;
  45. Memoire_Adresses_Retour_Size : Natural := 16;
  46. Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
  47. Port (CLK : STD_LOGIC;
  48. RST : STD_LOGIC;
  49. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  50. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
  51. end component;
  52. component Clock_Divider is
  53. Port ( CLK_IN : in STD_LOGIC;
  54. CLK_OUT : out STD_LOGIC);
  55. end component;
  56. signal my_RST : STD_LOGIC;
  57. signal my_CLK : STD_LOGIC;
  58. signal buff_CLK : STD_LOGIC;
  59. begin
  60. clk_div : Clock_Divider
  61. port map (CLK_IN => CLK,
  62. CLK_OUT => buff_CLK);
  63. clk_div_2 : Clock_Divider
  64. port map (CLK_IN => buff_CLK,
  65. CLK_OUT => my_CLK);
  66. instance : Pipeline
  67. generic map (Addr_Memoire_Instruction_Size => 8,
  68. Memoire_Instruction_Size => 256)
  69. port map (CLK => my_CLK,
  70. RST => my_RST,
  71. STD_IN => sw,
  72. STD_OUT => led);
  73. my_RST <= '0' when btnC = '1' else
  74. '1';
  75. end Structural;