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Ps2Interface.vhd 31KB

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  1. ------------------------------------------------------------------------
  2. -- ps2interface.vhd
  3. ------------------------------------------------------------------------
  4. -- Author : Ulrich Zoltán
  5. -- Copyright 2006 Digilent, Inc.
  6. ------------------------------------------------------------------------
  7. -- This file contains the implementation of a generic bidirectional
  8. -- ps/2 interface.
  9. ------------------------------------------------------------------------
  10. -- Behavioral description
  11. ------------------------------------------------------------------------
  12. -- Please read the following article on the web for understanding how
  13. -- the ps/2 protocol works.
  14. -- http://www.computer-engineering.org/ps2protocol/
  15. -- This module implements a generic bidirectional ps/2 interface. It can
  16. -- be used with any ps/2 compatible device. It offers its clients a
  17. -- convenient way to exchange data with the device. The interface
  18. -- transparently wraps the byte to be sent into a ps/2 frame, generates
  19. -- parity for byte and sends the frame one bit at a time to the device.
  20. -- Similarly, when receiving data from the ps2 device, the interface
  21. -- receives the frame, checks for parity, and extract the usefull data
  22. -- and forwards it to the client. If an error occurs during receiving
  23. -- or sending a byte, the client is informed by settings the err output
  24. -- line high. This way, the client can resend the data or can issue
  25. -- a resend command to the device.
  26. -- The physical ps/2 interface uses 4 lines
  27. -- For the 6-pin connector pins are assigned as follows:
  28. -- 1 - Data
  29. -- 2 - Not Implemented
  30. -- 3 - Ground
  31. -- 4 - Vcc (+5V)
  32. -- 5 - Clock
  33. -- 6 - Not Implemented
  34. -- The clock line carries the device generated clock which has a
  35. -- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
  36. -- it is placed in high impedance. The clock is only generated when
  37. -- device is sending or receiving data.
  38. -- The Data and Clock lines are both open-collector with pullup
  39. -- resistors to Vcc. An "open-collector" interface has two possible
  40. -- states: low('0') or high impedance('Z').
  41. -- When device wants to send a byte, it pulls the clock line low and the
  42. -- host(i.e. this interfaces) recognizes that the device is sending data
  43. -- When the host wants to send data, it maeks a request to send. This
  44. -- is done by holding the clock line low for at least 100us, then with
  45. -- the clock line low, the data line is brought low. Next the clock line
  46. -- is released (placed in high impedance). The devices begins generating
  47. -- clock signal on clock line.
  48. -- When receiving data, bits are read from the data line (ps2_data) on
  49. -- the falling edge of the clock (ps2_clk). When sending data, the
  50. -- device reads the bits from the data line on the rising edge of the
  51. -- clock.
  52. -- A frame for sending a byte is comprised of 11 bits as shown bellow:
  53. -- bits 10 9 8 7 6 5 4 3 2 1 0
  54. -- -------------------------------------------------------------
  55. -- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
  56. -- -------------------------------------------------------------
  57. -- STOP - stop bit, always '1'
  58. -- PAR - parity bit, odd parity for the 8 data bits.
  59. -- - select in such way that the number of bits of '1' in the data
  60. -- - bits together with parity bit is odd.
  61. -- D0-7 - data bits.
  62. -- START - start bit, always '0'
  63. --
  64. -- Frame is sent bit by bit starting with the least significant bit
  65. -- (starting bit) and is received the same way. This is done, when
  66. -- receiving, by shifting the frame register to the left when a bit
  67. -- is available and placing the bit on data line on the most significant
  68. -- bit. This way the first bit sent will reach the least significant bit
  69. -- of the frame when all the bits have been received. When sending data
  70. -- the least significant bit of the frame is placed on the data line
  71. -- and the frame is shifted to the right when another bit needs to be
  72. -- sent. During the request to send, when releasing the clock line,
  73. -- the device reads the data line and interprets the data on it as the
  74. -- first bit of the frame. Data line is low at that time, at this is the
  75. -- way the start bit('0') is sent. Because of this, when sending, only
  76. -- 10 shifts of the frame will be made.
  77. -- While the interface is sending or receiving data, the busy output
  78. -- signal goes high. When interface is idle, busy is low.
  79. -- After sending all the bits in the frame, the device must acknowledge
  80. -- the data sent. This is done by the host releasing and data line
  81. -- (clock line is already released) after the last bit is sent. The
  82. -- devices brings the data line and the clock line low, in this order,
  83. -- to acknowledge the data. If data line is high when clock line goes
  84. -- low after last bit, the device did not acknowledge the data and
  85. -- err output is set.
  86. -- A FSM is used to manage the transitions the set all the command
  87. -- signals. States that begin with "rx_" are used to receive data
  88. -- from device and states begining with "tx_" are used to send data
  89. -- to the device.
  90. -- For the parity bit, a ROM holds the parity bit for all possible
  91. -- data (256 possible values, since 8 bits of data). The ROM has
  92. -- dimensions 256x1bit. For obtaining the parity bit of a value,
  93. -- the bit at the data value address is read. Ex: to find the parity
  94. -- bit of 174, the bit at address 174 is read.
  95. -- For generating the necessary delay, counters are used. For example,
  96. -- to generate the 100us delay a 14 bit counter is used that has the
  97. -- upper limit for counting 10000. The interface is designed to run
  98. -- at 100MHz. Thus, 10000x10ns = 100us.
  99. -----------------------------------------------------------------------
  100. -- If using the interface at different frequency than 100MHz, adjusting
  101. -- the delay counters is necessary!!!
  102. -----------------------------------------------------------------------
  103. -- Clock line(ps2_clk) and data line(ps2_data) are passed through a
  104. -- debouncer for the transitions of the clock and data to be clean.
  105. -- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
  106. -- value of the clock and data line to the system clock(clk).
  107. ------------------------------------------------------------------------
  108. -- Port definitions
  109. ------------------------------------------------------------------------
  110. -- ps2_clk - inout pin, clock line of the ps/2 interface
  111. -- ps2_data - inout pin, data line of the ps/2 interface
  112. -- clk - input pin, system clock signal
  113. -- rst - input pin, system reset signal
  114. -- tx_data - input pin, 8 bits, from client
  115. -- - data to be sent to the device
  116. -- write_data - input pin, from client
  117. -- - should be active for one clock period when then
  118. -- - client wants to send data to the device and
  119. -- - data to be sent is valid on tx_data
  120. -- rx_data - output pin, 8 bits, to client
  121. -- - data received from device
  122. -- read - output pin, to client
  123. -- - active for one clock period when new data is
  124. -- - available from device
  125. -- busy - output pin, to client
  126. -- - active while sending or receiving data.
  127. -- err - output pin, to client
  128. -- - active for one clock period when an error occurred
  129. -- - during sending or receiving.
  130. ------------------------------------------------------------------------
  131. -- Revision History:
  132. -- 09/18/2006(UlrichZ): created
  133. ------------------------------------------------------------------------
  134. library IEEE;
  135. use IEEE.STD_LOGIC_1164.ALL;
  136. use IEEE.STD_LOGIC_ARITH.ALL;
  137. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  138. -- simulation library
  139. library UNISIM;
  140. use UNISIM.VComponents.all;
  141. -- the ps2interface entity declaration
  142. -- read above for behavioral description and port definitions.
  143. entity Ps2Interface is
  144. port(
  145. ps2_clk : inout std_logic;
  146. ps2_data : inout std_logic;
  147. clk : in std_logic;
  148. rst : in std_logic;
  149. tx_data : in std_logic_vector(7 downto 0);
  150. write_data : in std_logic;
  151. rx_data : out std_logic_vector(7 downto 0);
  152. read_data : out std_logic;
  153. busy : out std_logic;
  154. err : out std_logic
  155. );
  156. -- forces the extraction of distributed ram for
  157. -- the parity rom memory.
  158. -- please remove if block ram is preffered.
  159. attribute rom_extract : string;
  160. attribute rom_extract of Ps2Interface: entity is "yes";
  161. attribute rom_style : string;
  162. attribute rom_style of Ps2Interface: entity is "distributed";
  163. end Ps2Interface;
  164. architecture Behavioral of Ps2Interface is
  165. ------------------------------------------------------------------------
  166. -- CONSTANTS
  167. ------------------------------------------------------------------------
  168. -- Values are valid for a 100MHz clk. Please adjust for other
  169. -- frequencies if necessary!
  170. -- upper limit for 100us delay counter.
  171. -- 10000 * 10ns = 100us
  172. constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
  173. -- 10000 clock periods
  174. -- upper limit for 20us delay counter.
  175. -- 2000 * 10ns = 20us
  176. constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
  177. -- 2000 clock periods
  178. -- upper limit for 63clk delay counter.
  179. constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
  180. -- 63 clock periods
  181. -- delay from debouncing ps2_clk and ps2_data signals
  182. constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
  183. -- number of bits in a frame
  184. constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
  185. -- parity bit position in frame
  186. constant PARITY_BIT: positive := 9;
  187. -- (odd) parity bit ROM
  188. -- Used instead of logic because this way speed is far greater
  189. -- 256x1bit rom
  190. -- If the odd parity bit for a 8 bits number, x, is needed
  191. -- the bit at address x is the parity bit.
  192. type ROM is array(0 to 255) of std_logic;
  193. constant parityrom : ROM := (
  194. '1','0','0','1','0','1','1','0',
  195. '0','1','1','0','1','0','0','1',
  196. '0','1','1','0','1','0','0','1',
  197. '1','0','0','1','0','1','1','0',
  198. '0','1','1','0','1','0','0','1',
  199. '1','0','0','1','0','1','1','0',
  200. '1','0','0','1','0','1','1','0',
  201. '0','1','1','0','1','0','0','1',
  202. '0','1','1','0','1','0','0','1',
  203. '1','0','0','1','0','1','1','0',
  204. '1','0','0','1','0','1','1','0',
  205. '0','1','1','0','1','0','0','1',
  206. '1','0','0','1','0','1','1','0',
  207. '0','1','1','0','1','0','0','1',
  208. '0','1','1','0','1','0','0','1',
  209. '1','0','0','1','0','1','1','0',
  210. '0','1','1','0','1','0','0','1',
  211. '1','0','0','1','0','1','1','0',
  212. '1','0','0','1','0','1','1','0',
  213. '0','1','1','0','1','0','0','1',
  214. '1','0','0','1','0','1','1','0',
  215. '0','1','1','0','1','0','0','1',
  216. '0','1','1','0','1','0','0','1',
  217. '1','0','0','1','0','1','1','0',
  218. '1','0','0','1','0','1','1','0',
  219. '0','1','1','0','1','0','0','1',
  220. '0','1','1','0','1','0','0','1',
  221. '1','0','0','1','0','1','1','0',
  222. '0','1','1','0','1','0','0','1',
  223. '1','0','0','1','0','1','1','0',
  224. '1','0','0','1','0','1','1','0',
  225. '0','1','1','0','1','0','0','1'
  226. );
  227. ------------------------------------------------------------------------
  228. -- SIGNALS
  229. ------------------------------------------------------------------------
  230. -- 14 bits counter
  231. -- max value DELAY_100US
  232. -- used to wait 100us
  233. signal delay_100us_count: std_logic_vector(13 downto 0) :=
  234. (others => '0');
  235. -- 11 bits counter
  236. -- max value DELAY_20US
  237. -- used to wait 20us
  238. signal delay_20us_count: std_logic_vector(10 downto 0) :=
  239. (others => '0');
  240. -- 11 bits counter
  241. -- max value DELAY_63CLK
  242. -- used to wait 63 clock periods
  243. signal delay_63clk_count: std_logic_vector(6 downto 0) :=
  244. (others => '0');
  245. -- done signal for the couters above
  246. -- when a counter reaches max value,the corresponding done signal is set
  247. signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
  248. -- enable signal for 100us delay counter
  249. signal delay_100us_counter_enable: std_logic := '0';
  250. -- enable signal for 20us delay counter
  251. signal delay_20us_counter_enable : std_logic := '0';
  252. -- enable signal for 63clk delay counter
  253. signal delay_63clk_counter_enable: std_logic := '0';
  254. -- synchronzed input for ps2_clk and ps2_data
  255. signal ps2_clk_s,ps2_data_s: std_logic := '1';
  256. -- control the output of ps2_clk and ps2_data
  257. -- if 1 then corresponding signal (ps2_clk or ps2_data) is
  258. -- put in high impedance ('Z').
  259. signal ps2_clk_h,ps2_data_h: std_logic := '1';
  260. -- states of the FSM for controlling the communcation with the device
  261. -- states that begin with "rx_" are used when receiving data
  262. -- states that begin with "tx_" are used when transmiting data
  263. type fsm_state is
  264. (
  265. idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
  266. tx_force_clk_l,tx_bring_data_down,tx_release_clk,
  267. tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
  268. tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
  269. tx_error_no_ack
  270. );
  271. -- the signal that holds the current state of the FSM
  272. -- implicitly state is idle.
  273. signal state: fsm_state := idle;
  274. -- register that holds the frame received or the one to be sent.
  275. -- Its contents are shifted in from the bus one bit at a time
  276. -- from left to right when receiving data and are shifted on the
  277. -- bus (ps2_data) one bit at a time to the right when sending data
  278. signal frame: std_logic_vector(10 downto 0) := (others => '0');
  279. -- how many bits have been sent or received.
  280. signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
  281. -- when active the bit counter is reset.
  282. signal reset_bit_count: std_logic := '0';
  283. -- when active the contents of the frame is shifted to the right
  284. -- and the most significant bit of frame is loaded with ps2_data.
  285. signal shift_frame: std_logic := '0';
  286. -- parity of the byte that was received from the device.
  287. -- must match the parity bit received, else error occurred.
  288. signal rx_parity: std_logic := '0';
  289. -- parity bit that is sent with the frame, representing the
  290. -- odd parity of the byte currently being sent
  291. signal tx_parity: std_logic := '0';
  292. -- when active, frame is loaded with the start bit, data on
  293. -- tx_data, parity bit (tx_parity) and stop bit
  294. -- this frame will be sent to the device.
  295. signal load_tx_data: std_logic := '0';
  296. -- when active bits 8 downto 1 from frame are loaded into
  297. -- rx_data register. This is the byte received from the device.
  298. signal load_rx_data: std_logic := '0';
  299. -- intermediary signals used to debounce the inputs ps2_clk and ps2_data
  300. signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
  301. -- debounce counter for the ps2_clk input and the ps2_data input.
  302. signal clk_count,data_count: std_logic_vector(3 downto 0);
  303. -- last value on ps2_clk and ps2_data.
  304. signal clk_inter,data_inter: std_logic := '1';
  305. begin
  306. ---------------------------------------------------------------------
  307. -- FLAGS and PS2 CLOCK AND DATA LINES
  308. ---------------------------------------------------------------------
  309. -- clean ps2_clk signal (debounce)
  310. -- note that this introduces a delay in ps2_clk of
  311. -- DEBOUNCE_DELAY clocks
  312. process(clk)
  313. begin
  314. if(rising_edge(clk)) then
  315. -- if the current bit on ps2_clk is different
  316. -- from the last value, then reset counter
  317. -- and retain value
  318. if(ps2_clk /= clk_inter) then
  319. clk_inter <= ps2_clk;
  320. clk_count <= (others => '0');
  321. -- if counter reached upper limit, then
  322. -- the signal is clean
  323. elsif(clk_count = DEBOUNCE_DELAY) then
  324. ps2_clk_clean <= clk_inter;
  325. -- ps2_clk did not change, but counter did not
  326. -- reach limit. Increment counter
  327. else
  328. clk_count <= clk_count + 1;
  329. end if;
  330. end if;
  331. end process;
  332. -- clean ps2_data signal (debounce)
  333. -- note that this introduces a delay in ps2_data of
  334. -- DEBOUNCE_DELAY clocks
  335. process(clk)
  336. begin
  337. if(rising_edge(clk)) then
  338. -- if the current bit on ps2_data is different
  339. -- from the last value, then reset counter
  340. -- and retain value
  341. if(ps2_data /= data_inter) then
  342. data_inter <= ps2_data;
  343. data_count <= (others => '0');
  344. -- if counter reached upper limit, then
  345. -- the signal is clean
  346. elsif(data_count = DEBOUNCE_DELAY) then
  347. ps2_data_clean <= data_inter;
  348. -- ps2_data did not change, but counter did not
  349. -- reach limit. Increment counter
  350. else
  351. data_count <= data_count + 1;
  352. end if;
  353. end if;
  354. end process;
  355. -- Synchronize ps2 entries
  356. ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
  357. ps2_data_s <= ps2_data_clean when rising_edge(clk);
  358. -- Assign parity from frame bits 8 downto 1, this is the parity
  359. -- that should be received inside the frame on PARITY_BIT position
  360. rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
  361. when rising_edge(clk);
  362. -- The parity for the data to be sent
  363. tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
  364. -- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
  365. -- ('Z' = +5Vcc because of pull-ups)
  366. ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
  367. -- Force ps2_data to '0' if ps2_data_h = '0', else release the line
  368. -- ('Z' = +5Vcc because of pull-ups)
  369. ps2_data <= 'Z' when ps2_data_h = '1' else '0';
  370. -- Control busy flag. Interface is not busy while in idle state.
  371. busy <= '0' when state = idle else '1';
  372. -- reset the bit counter when in idle state.
  373. reset_bit_count <= '1' when state = idle else '0';
  374. -- Control shifting of the frame
  375. -- When receiving from device, data is read
  376. -- on the falling edge of ps2_clk
  377. -- When sending to device, data is read by device
  378. -- on the rising edge of ps2_clk
  379. shift_frame <= '1' when state = rx_down_edge or
  380. state = tx_clk_l else
  381. '0';
  382. ---------------------------------------------------------------------
  383. -- FINITE STATE MACHINE
  384. ---------------------------------------------------------------------
  385. -- For the current state establish next state
  386. -- and give necessary commands
  387. manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
  388. bit_count,rx_parity,frame,delay_100us_done,
  389. delay_20us_done,delay_63clk_done)
  390. begin
  391. -- if reset occurs, go to idle state.
  392. if(rst = '1') then
  393. state <= idle;
  394. elsif(rising_edge(clk)) then
  395. -- default values for these signals
  396. -- ensures signals are reset to default value
  397. -- when coditions for their activation are no
  398. -- longer applied (transition to other state,
  399. -- where signal should not be active)
  400. -- Idle value for ps2_clk and ps2_data is 'Z'
  401. ps2_clk_h <= '1';
  402. ps2_data_h <= '1';
  403. load_tx_data <= '0';
  404. load_rx_data <= '0';
  405. read_data <= '0';
  406. err <= '0';
  407. case state is
  408. -- wait for the device to begin a transmission
  409. -- by pulling the clock line low and go to state
  410. -- rx_down_edge or, if write is high, the
  411. -- client of this interface wants to send a byte
  412. -- to the device and a transition is made to state
  413. -- tx_force_clk_l
  414. when idle =>
  415. if(ps2_clk_s = '0') then
  416. state <= rx_down_edge;
  417. elsif(write_data = '1') then
  418. state <= tx_force_clk_l;
  419. else
  420. state <= idle;
  421. end if;
  422. -- ps2_clk is high, check if all the bits have been read
  423. -- if, last bit read, check parity, and if parity ok
  424. -- load received data into rx_data.
  425. -- else if more bits left, then wait for the ps2_clk to
  426. -- go low
  427. when rx_clk_h =>
  428. if(bit_count = NUMBITS) then
  429. if(not (rx_parity = frame(PARITY_BIT))) then
  430. state <= rx_error_parity;
  431. else
  432. load_rx_data <= '1';
  433. state <= rx_data_ready;
  434. end if;
  435. elsif(ps2_clk_s = '0') then
  436. state <= rx_down_edge;
  437. else
  438. state <= rx_clk_h;
  439. end if;
  440. -- data must be read into frame in this state
  441. -- the ps2_clk just transitioned from high to low
  442. when rx_down_edge =>
  443. state <= rx_clk_l;
  444. -- ps2_clk line is low, wait for it to go high
  445. when rx_clk_l =>
  446. if(ps2_clk_s = '1') then
  447. state <= rx_clk_h;
  448. else
  449. state <= rx_clk_l;
  450. end if;
  451. -- parity bit received is invalid
  452. -- signal error and go back to idle.
  453. when rx_error_parity =>
  454. err <= '1';
  455. state <= idle;
  456. -- parity bit received was good
  457. -- set read signal for the client to know
  458. -- a new byte was received and is available on rx_data
  459. when rx_data_ready =>
  460. read_data <= '1';
  461. state <= idle;
  462. -- the client wishes to transmit a byte to the device
  463. -- this is done by holding ps2_clk down for at least 100us
  464. -- bringing down ps2_data, wait 20us and then releasing
  465. -- the ps2_clk.
  466. -- This constitutes a request to send command.
  467. -- In this state, the ps2_clk line is held down and
  468. -- the counter for waiting 100us is eanbled.
  469. -- when the counter reached upper limit, transition
  470. -- to tx_bring_data_down
  471. when tx_force_clk_l =>
  472. load_tx_data <= '1';
  473. ps2_clk_h <= '0';
  474. if(delay_100us_done = '1') then
  475. state <= tx_bring_data_down;
  476. else
  477. state <= tx_force_clk_l;
  478. end if;
  479. -- with the ps2_clk line low bring ps2_data low
  480. -- wait for 20us and then go to tx_release_clk
  481. when tx_bring_data_down =>
  482. -- keep clock line low
  483. ps2_clk_h <= '0';
  484. -- set data line low
  485. -- when clock is released in the next state
  486. -- the device will read bit 0 on data line
  487. -- and this bit represents the start bit.
  488. ps2_data_h <= '0'; -- start bit = '0'
  489. if(delay_20us_done = '1') then
  490. state <= tx_release_clk;
  491. else
  492. state <= tx_bring_data_down;
  493. end if;
  494. -- release the ps2_clk line
  495. -- keep holding data line low
  496. when tx_release_clk =>
  497. ps2_clk_h <= '1';
  498. -- must maintain data low,
  499. -- otherwise will be released by default value
  500. ps2_data_h <= '0';
  501. state <= tx_first_wait_down_edge;
  502. -- state is necessary because the clock signal
  503. -- is not released instantaneously and, because of debounce,
  504. -- delay is even greater.
  505. -- Wait 63 clock periods for the clock line to release
  506. -- then if clock is low then go to tx_clk_l
  507. -- else wait until ps2_clk goes low.
  508. when tx_first_wait_down_edge =>
  509. ps2_data_h <= '0';
  510. if(delay_63clk_done = '1') then
  511. if(ps2_clk_s = '0') then
  512. state <= tx_clk_l;
  513. else
  514. state <= tx_first_wait_down_edge;
  515. end if;
  516. else
  517. state <= tx_first_wait_down_edge;
  518. end if;
  519. -- place the least significant bit from frame
  520. -- on the data line
  521. -- During this state the frame is shifted one
  522. -- bit to the right
  523. when tx_clk_l =>
  524. ps2_data_h <= frame(0);
  525. state <= tx_wait_up_edge;
  526. -- wait for the clock to go high
  527. -- this is the edge on which the device reads the data
  528. -- on ps2_data.
  529. -- keep holding ps2_data on frame(0) because else
  530. -- will be released by default value.
  531. -- Check if sent the last bit and if so, release data line
  532. -- and go to state that wait for acknowledge
  533. when tx_wait_up_edge =>
  534. ps2_data_h <= frame(0);
  535. -- NUMBITS - 1 because first (start bit = 0) bit was read
  536. -- when the clock line was released in the request to
  537. -- send command (see tx_bring_data_down state).
  538. if(bit_count = NUMBITS-1) then
  539. ps2_data_h <= '1';
  540. state <= tx_wait_up_edge_before_ack;
  541. -- if more bits to send, wait for the up edge
  542. -- of ps2_clk
  543. elsif(ps2_clk_s = '1') then
  544. state <= tx_clk_h;
  545. else
  546. state <= tx_wait_up_edge;
  547. end if;
  548. -- ps2_clk is released, wait for down edge
  549. -- and go to tx_clk_l when arrived
  550. when tx_clk_h =>
  551. ps2_data_h <= frame(0);
  552. if(ps2_clk_s = '0') then
  553. state <= tx_clk_l;
  554. else
  555. state <= tx_clk_h;
  556. end if;
  557. -- release ps2_data and wait for rising edge of ps2_clk
  558. -- once this occurs, transition to tx_wait_ack
  559. when tx_wait_up_edge_before_ack =>
  560. ps2_data_h <= '1';
  561. if(ps2_clk_s = '1') then
  562. state <= tx_wait_ack;
  563. else
  564. state <= tx_wait_up_edge_before_ack;
  565. end if;
  566. -- wait for the falling edge of the clock line
  567. -- if data line is low when this occurs, the
  568. -- ack is received
  569. -- else if data line is high, the device did not
  570. -- acknowledge the transimission
  571. when tx_wait_ack =>
  572. if(ps2_clk_s = '0') then
  573. if(ps2_data_s = '0') then
  574. -- acknowledge received
  575. state <= tx_received_ack;
  576. else
  577. -- acknowledge not received
  578. state <= tx_error_no_ack;
  579. end if;
  580. else
  581. state <= tx_wait_ack;
  582. end if;
  583. -- wait for ps2_clk to be released together with ps2_data
  584. -- (bus to be idle) and go back to idle state
  585. when tx_received_ack =>
  586. if(ps2_clk_s = '1' and ps2_data_s = '1') then
  587. state <= idle;
  588. else
  589. state <= tx_received_ack;
  590. end if;
  591. -- wait for ps2_clk to be released together with ps2_data
  592. -- (bus to be idle) and go back to idle state
  593. -- signal error for not receiving ack
  594. when tx_error_no_ack =>
  595. if(ps2_clk_s = '1' and ps2_data_s = '1') then
  596. err <= '1';
  597. state <= idle;
  598. else
  599. state <= tx_error_no_ack;
  600. end if;
  601. -- if invalid transition occurred, signal error and
  602. -- go back to idle state
  603. when others =>
  604. err <= '1';
  605. state <= idle;
  606. end case;
  607. end if;
  608. end process manage_fsm;
  609. ---------------------------------------------------------------------
  610. -- DELAY COUNTERS
  611. ---------------------------------------------------------------------
  612. -- Enable the 100us counter only when state is tx_force_clk_l
  613. delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
  614. -- Counter for a 100us delay
  615. -- after done counting, done signal remains active until
  616. -- enable counter is reset.
  617. delay_100us_counter: process(clk)
  618. begin
  619. if(rising_edge(clk)) then
  620. if(delay_100us_counter_enable = '1') then
  621. if(delay_100us_count = (DELAY_100US)) then
  622. delay_100us_count <= delay_100us_count;
  623. delay_100us_done <= '1';
  624. else
  625. delay_100us_count <= delay_100us_count + 1;
  626. delay_100us_done <= '0';
  627. end if;
  628. else
  629. delay_100us_count <= (others => '0');
  630. delay_100us_done <= '0';
  631. end if;
  632. end if;
  633. end process delay_100us_counter;
  634. -- Enable the 20us counter only when state is tx_bring_data_down
  635. delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
  636. -- Counter for a 20us delay
  637. -- after done counting, done signal remains active until
  638. -- enable counter is reset.
  639. delay_20us_counter: process(clk)
  640. begin
  641. if(rising_edge(clk)) then
  642. if(delay_20us_counter_enable = '1') then
  643. if(delay_20us_count = (DELAY_20US)) then
  644. delay_20us_count <= delay_20us_count;
  645. delay_20us_done <= '1';
  646. else
  647. delay_20us_count <= delay_20us_count + 1;
  648. delay_20us_done <= '0';
  649. end if;
  650. else
  651. delay_20us_count <= (others => '0');
  652. delay_20us_done <= '0';
  653. end if;
  654. end if;
  655. end process delay_20us_counter;
  656. -- Enable the 63clk counter only when state is tx_first_wait_down_edge
  657. delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
  658. -- Counter for a 63 clock periods delay
  659. -- after done counting, done signal remains active until
  660. -- enable counter is reset.
  661. delay_63clk_counter: process(clk)
  662. begin
  663. if(rising_edge(clk)) then
  664. if(delay_63clk_counter_enable = '1') then
  665. if(delay_63clk_count = (DELAY_63CLK)) then
  666. delay_63clk_count <= delay_63clk_count;
  667. delay_63clk_done <= '1';
  668. else
  669. delay_63clk_count <= delay_63clk_count + 1;
  670. delay_63clk_done <= '0';
  671. end if;
  672. else
  673. delay_63clk_count <= (others => '0');
  674. delay_63clk_done <= '0';
  675. end if;
  676. end if;
  677. end process delay_63clk_counter;
  678. ---------------------------------------------------------------------
  679. -- BIT COUNTER AND FRAME SHIFTING LOGIC
  680. ---------------------------------------------------------------------
  681. -- counts the number of bits shifted into the frame
  682. -- or out of the frame.
  683. bit_counter: process(clk)
  684. begin
  685. if(rising_edge(clk)) then
  686. if(reset_bit_count = '1') then
  687. bit_count <= (others => '0');
  688. elsif(shift_frame = '1') then
  689. bit_count <= bit_count + 1;
  690. end if;
  691. end if;
  692. end process bit_counter;
  693. -- shifts frame with one bit to right when shift_frame is acitve
  694. -- and loads data into frame from tx_data then load_tx_data is high
  695. load_tx_data_into_frame: process(clk)
  696. begin
  697. if(rising_edge(clk)) then
  698. if(load_tx_data = '1') then
  699. frame(8 downto 1) <= tx_data; -- byte to send
  700. frame(0) <= '0'; -- start bit
  701. frame(10) <= '1'; -- stop bit
  702. frame(9) <= tx_parity; -- parity bit
  703. elsif(shift_frame = '1') then
  704. -- shift right 1 bit
  705. frame(9 downto 0) <= frame(10 downto 1);
  706. -- shift in from the ps2_data line
  707. frame(10) <= ps2_data_s;
  708. end if;
  709. end if;
  710. end process load_tx_data_into_frame;
  711. -- Loads data from frame into rx_data output when data is ready
  712. do_load_rx_data: process(clk)
  713. begin
  714. if(rising_edge(clk)) then
  715. if(load_rx_data = '1') then
  716. rx_data <= frame(8 downto 1);
  717. end if;
  718. end if;
  719. end process do_load_rx_data;
  720. end Behavioral;