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- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
- ---------------------------------------------------------------------------------------
- | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
- | Date : Fri Apr 09 23:16:39 2021
- | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
- | Command : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
- | Design : GPIO_demo
- | Device : 7a35t-cpg236
- | Speed File : -1 PRODUCTION 1.16 2016-11-09
- ---------------------------------------------------------------------------------------
-
- Clock Utilization Report
-
- Table of Contents
- -----------------
- 1. Clock Primitive Utilization
- 2. Global Clock Resources
- 3. Global Clock Source Details
- 4. Clock Regions: Key Resource Utilization
- 5. Clock Regions : Global Clock Summary
- 6. Cell Type Counts per Global Clock: Region X0Y0
- 7. Cell Type Counts per Global Clock: Region X1Y0
- 8. Cell Type Counts per Global Clock: Region X0Y1
- 9. Load Cell Placement Summary for Global Clock g0
- 10. Load Cell Placement Summary for Global Clock g1
- 11. Load Cell Placement Summary for Global Clock g2
-
- 1. Clock Primitive Utilization
- ------------------------------
-
- +----------+------+-----------+-----+--------------+--------+
- | Type | Used | Available | LOC | Clock Region | Pblock |
- +----------+------+-----------+-----+--------------+--------+
- | BUFGCTRL | 3 | 32 | 0 | 0 | 0 |
- | BUFH | 0 | 72 | 0 | 0 | 0 |
- | BUFIO | 0 | 20 | 0 | 0 | 0 |
- | BUFMR | 0 | 10 | 0 | 0 | 0 |
- | BUFR | 0 | 20 | 0 | 0 | 0 |
- | MMCM | 1 | 5 | 0 | 0 | 0 |
- | PLL | 0 | 5 | 0 | 0 | 0 |
- +----------+------+-----------+-----+--------------+--------+
-
-
- 2. Global Clock Resources
- -------------------------
-
- +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
- | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
- +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
- | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | | | 2 | 336 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
- | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | | | 2 | 243 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_BUFG_inst/O | CLK_IBUF_BUFG |
- | g2 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | | | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
- +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
- * Clock Loads column represents the clock pin loads (pin count)
- ** Non-Clock Loads column represents the non-clock pin loads (pin count)
-
-
- 3. Global Clock Source Details
- ------------------------------
-
- +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
- | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
- +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
- | src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
- | src0 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
- | src1 | g1 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_inst/O | CLK_IBUF |
- +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
- * Clock Loads column represents the clock pin loads (pin count)
- ** Non-Clock Loads column represents the non-clock pin loads (pin count)
-
-
- 4. Clock Regions: Key Resource Utilization
- ------------------------------------------
-
- +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
- | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
- +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
- | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
- +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
- | X0Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 484 | 1200 | 206 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
- | X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 31 | 1500 | 2 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
- | X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 63 | 1200 | 21 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
- | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
- | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
- | X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
- +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
- * Global Clock column represents track count; while other columns represents cell counts
-
-
- 5. Clock Regions : Global Clock Summary
- ---------------------------------------
-
- +----+----+----+
- | | X0 | X1 |
- +----+----+----+
- | Y2 | 0 | 0 |
- | Y1 | 1 | 0 |
- | Y0 | 2 | 2 |
- +----+----+----+
-
-
- 6. Cell Type Counts per Global Clock: Region X0Y0
- -------------------------------------------------
-
- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- | g0 | n/a | BUFG/O | None | 273 | 0 | 273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
- | g1 | n/a | BUFG/O | None | 211 | 0 | 211 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLK_IBUF_BUFG |
- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- * Clock Loads column represents the clock pin loads (pin count)
- ** Non-Clock Loads column represents the non-clock pin loads (pin count)
- *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
- 7. Cell Type Counts per Global Clock: Region X1Y0
- -------------------------------------------------
-
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
- | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
- | g1 | n/a | BUFG/O | None | 32 | 0 | 31 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLK_IBUF_BUFG |
- | g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
- * Clock Loads column represents the clock pin loads (pin count)
- ** Non-Clock Loads column represents the non-clock pin loads (pin count)
- *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
- 8. Cell Type Counts per Global Clock: Region X0Y1
- -------------------------------------------------
-
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- | g0 | n/a | BUFG/O | None | 63 | 0 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
- * Clock Loads column represents the clock pin loads (pin count)
- ** Non-Clock Loads column represents the non-clock pin loads (pin count)
- *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
- 9. Load Cell Placement Summary for Global Clock g0
- --------------------------------------------------
-
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
- | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
- | g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 9.259 | {0.000 4.630} | | 336 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
- * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
- ** IO Loads column represents load cell count of IO types
- *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
- **** GT Loads column represents load cell count of GT types
-
-
- +----+------+----+
- | | X0 | X1 |
- +----+------+----+
- | Y2 | 0 | 0 |
- | Y1 | 63 | 0 |
- | Y0 | 273 | 0 |
- +----+------+----+
-
-
- 10. Load Cell Placement Summary for Global Clock g1
- ---------------------------------------------------
-
- +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
- | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
- +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
- | g1 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | | 242 | 0 | 1 | 0 | CLK_IBUF_BUFG |
- +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
- * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
- ** IO Loads column represents load cell count of IO types
- *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
- **** GT Loads column represents load cell count of GT types
-
-
- +----+------+-----+
- | | X0 | X1 |
- +----+------+-----+
- | Y2 | 0 | 0 |
- | Y1 | 0 | 0 |
- | Y0 | 211 | 32 |
- +----+------+-----+
-
-
- 11. Load Cell Placement Summary for Global Clock g2
- ---------------------------------------------------
-
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
- | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
- | g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | | 0 | 0 | 1 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
- +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
- * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
- ** IO Loads column represents load cell count of IO types
- *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
- **** GT Loads column represents load cell count of GT types
-
-
- +----+----+----+
- | | X0 | X1 |
- +----+----+----+
- | Y2 | 0 | 0 |
- | Y1 | 0 | 0 |
- | Y0 | 0 | 1 |
- +----+----+----+
-
-
-
- # Location of BUFG Primitives
- set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
- set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
- set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
-
- # Location of IO Primitives which is load of clock spine
-
- # Location of clock ports
- set_property LOC IOB_X1Y26 [get_ports CLK]
-
- # Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
- #startgroup
- create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
- add_cells_to_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
- resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
- #endgroup
-
- # Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
- #startgroup
- create_pblock {CLKAG_CLK_IBUF_BUFG}
- add_cells_to_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
- resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
- #endgroup
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