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GPIO_demo_clock_utilization_routed.rpt 20KB

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  1. Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  2. ---------------------------------------------------------------------------------------
  3. | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
  4. | Date : Fri Apr 09 23:16:39 2021
  5. | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
  6. | Command : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
  7. | Design : GPIO_demo
  8. | Device : 7a35t-cpg236
  9. | Speed File : -1 PRODUCTION 1.16 2016-11-09
  10. ---------------------------------------------------------------------------------------
  11. Clock Utilization Report
  12. Table of Contents
  13. -----------------
  14. 1. Clock Primitive Utilization
  15. 2. Global Clock Resources
  16. 3. Global Clock Source Details
  17. 4. Clock Regions: Key Resource Utilization
  18. 5. Clock Regions : Global Clock Summary
  19. 6. Cell Type Counts per Global Clock: Region X0Y0
  20. 7. Cell Type Counts per Global Clock: Region X1Y0
  21. 8. Cell Type Counts per Global Clock: Region X0Y1
  22. 9. Load Cell Placement Summary for Global Clock g0
  23. 10. Load Cell Placement Summary for Global Clock g1
  24. 11. Load Cell Placement Summary for Global Clock g2
  25. 1. Clock Primitive Utilization
  26. ------------------------------
  27. +----------+------+-----------+-----+--------------+--------+
  28. | Type | Used | Available | LOC | Clock Region | Pblock |
  29. +----------+------+-----------+-----+--------------+--------+
  30. | BUFGCTRL | 3 | 32 | 0 | 0 | 0 |
  31. | BUFH | 0 | 72 | 0 | 0 | 0 |
  32. | BUFIO | 0 | 20 | 0 | 0 | 0 |
  33. | BUFMR | 0 | 10 | 0 | 0 | 0 |
  34. | BUFR | 0 | 20 | 0 | 0 | 0 |
  35. | MMCM | 1 | 5 | 0 | 0 | 0 |
  36. | PLL | 0 | 5 | 0 | 0 | 0 |
  37. +----------+------+-----------+-----+--------------+--------+
  38. 2. Global Clock Resources
  39. -------------------------
  40. +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
  41. | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
  42. +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
  43. | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | | | 2 | 336 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
  44. | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | | | 2 | 243 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_BUFG_inst/O | CLK_IBUF_BUFG |
  45. | g2 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | | | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
  46. +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
  47. * Clock Loads column represents the clock pin loads (pin count)
  48. ** Non-Clock Loads column represents the non-clock pin loads (pin count)
  49. 3. Global Clock Source Details
  50. ------------------------------
  51. +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
  52. | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
  53. +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
  54. | src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
  55. | src0 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
  56. | src1 | g1 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | CLK_IBUF_inst/O | CLK_IBUF |
  57. +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
  58. * Clock Loads column represents the clock pin loads (pin count)
  59. ** Non-Clock Loads column represents the non-clock pin loads (pin count)
  60. 4. Clock Regions: Key Resource Utilization
  61. ------------------------------------------
  62. +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
  63. | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
  64. +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  65. | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
  66. +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  67. | X0Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 484 | 1200 | 206 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  68. | X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 31 | 1500 | 2 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
  69. | X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 63 | 1200 | 21 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  70. | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
  71. | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  72. | X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
  73. +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  74. * Global Clock column represents track count; while other columns represents cell counts
  75. 5. Clock Regions : Global Clock Summary
  76. ---------------------------------------
  77. +----+----+----+
  78. | | X0 | X1 |
  79. +----+----+----+
  80. | Y2 | 0 | 0 |
  81. | Y1 | 1 | 0 |
  82. | Y0 | 2 | 2 |
  83. +----+----+----+
  84. 6. Cell Type Counts per Global Clock: Region X0Y0
  85. -------------------------------------------------
  86. +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  87. | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
  88. +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  89. | g0 | n/a | BUFG/O | None | 273 | 0 | 273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
  90. | g1 | n/a | BUFG/O | None | 211 | 0 | 211 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLK_IBUF_BUFG |
  91. +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  92. * Clock Loads column represents the clock pin loads (pin count)
  93. ** Non-Clock Loads column represents the non-clock pin loads (pin count)
  94. *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
  95. 7. Cell Type Counts per Global Clock: Region X1Y0
  96. -------------------------------------------------
  97. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
  98. | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
  99. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
  100. | g1 | n/a | BUFG/O | None | 32 | 0 | 31 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLK_IBUF_BUFG |
  101. | g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
  102. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
  103. * Clock Loads column represents the clock pin loads (pin count)
  104. ** Non-Clock Loads column represents the non-clock pin loads (pin count)
  105. *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
  106. 8. Cell Type Counts per Global Clock: Region X0Y1
  107. -------------------------------------------------
  108. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  109. | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
  110. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  111. | g0 | n/a | BUFG/O | None | 63 | 0 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
  112. +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
  113. * Clock Loads column represents the clock pin loads (pin count)
  114. ** Non-Clock Loads column represents the non-clock pin loads (pin count)
  115. *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
  116. 9. Load Cell Placement Summary for Global Clock g0
  117. --------------------------------------------------
  118. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
  119. | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
  120. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
  121. | g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 9.259 | {0.000 4.630} | | 336 | 0 | 0 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
  122. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
  123. * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
  124. ** IO Loads column represents load cell count of IO types
  125. *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
  126. **** GT Loads column represents load cell count of GT types
  127. +----+------+----+
  128. | | X0 | X1 |
  129. +----+------+----+
  130. | Y2 | 0 | 0 |
  131. | Y1 | 63 | 0 |
  132. | Y0 | 273 | 0 |
  133. +----+------+----+
  134. 10. Load Cell Placement Summary for Global Clock g1
  135. ---------------------------------------------------
  136. +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
  137. | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
  138. +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
  139. | g1 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | | 242 | 0 | 1 | 0 | CLK_IBUF_BUFG |
  140. +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
  141. * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
  142. ** IO Loads column represents load cell count of IO types
  143. *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
  144. **** GT Loads column represents load cell count of GT types
  145. +----+------+-----+
  146. | | X0 | X1 |
  147. +----+------+-----+
  148. | Y2 | 0 | 0 |
  149. | Y1 | 0 | 0 |
  150. | Y0 | 211 | 32 |
  151. +----+------+-----+
  152. 11. Load Cell Placement Summary for Global Clock g2
  153. ---------------------------------------------------
  154. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
  155. | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
  156. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
  157. | g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | | 0 | 0 | 1 | 0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
  158. +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
  159. * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
  160. ** IO Loads column represents load cell count of IO types
  161. *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
  162. **** GT Loads column represents load cell count of GT types
  163. +----+----+----+
  164. | | X0 | X1 |
  165. +----+----+----+
  166. | Y2 | 0 | 0 |
  167. | Y1 | 0 | 0 |
  168. | Y0 | 0 | 1 |
  169. +----+----+----+
  170. # Location of BUFG Primitives
  171. set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
  172. set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
  173. set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
  174. # Location of IO Primitives which is load of clock spine
  175. # Location of clock ports
  176. set_property LOC IOB_X1Y26 [get_ports CLK]
  177. # Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
  178. #startgroup
  179. create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
  180. add_cells_to_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
  181. resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
  182. #endgroup
  183. # Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
  184. #startgroup
  185. create_pblock {CLKAG_CLK_IBUF_BUFG}
  186. add_cells_to_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
  187. resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
  188. #endgroup