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- #-----------------------------------------------------------
- # Vivado v2016.4 (64-bit)
- # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
- # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
- # Start of session at: Fri Apr 09 23:15:32 2021
- # Process ID: 960
- # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
- # Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
- # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
- # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
- #-----------------------------------------------------------
- source GPIO_demo.tcl -notrace
- Design is defaulting to srcset: sources_1
- Design is defaulting to constrset: constrs_1
- INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
- INFO: [Project 1-479] Netlist was created with Vivado 2016.4
- INFO: [Device 21-403] Loading part xc7a35tcpg236-1
- INFO: [Project 1-570] Preparing netlist for logic optimization
- Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
- Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 2 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 2 instances
-
- link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
- INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
- Command: opt_design -directive RuntimeOptimized
- INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
- Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
- Running DRC as a precondition to command opt_design
-
- Starting DRC Task
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Project 1-461] DRC finished with 0 Errors
- INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
- Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
-
- Starting Logic Optimization Task
- Implement Debug Cores | Checksum: 11fc7498c
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [Timing 38-2] Deriving generated clocks
-
- Phase 1 Retarget
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- INFO: [Opt 31-49] Retargeted 0 cell(s).
- Phase 1 Retarget | Checksum: 16f269fca
-
- Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
-
- Phase 2 Constant propagation
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- INFO: [Opt 31-10] Eliminated 6 cells.
- Phase 2 Constant propagation | Checksum: 233a26f9e
-
- Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
-
- Phase 3 Sweep
- INFO: [Opt 31-12] Eliminated 363 unconnected nets.
- INFO: [Opt 31-11] Eliminated 2 unconnected cells.
- Phase 3 Sweep | Checksum: 1bb596469
-
- Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
-
- Phase 4 BUFG optimization
- INFO: [Opt 31-12] Eliminated 0 unconnected nets.
- INFO: [Opt 31-11] Eliminated 0 unconnected cells.
- Phase 4 BUFG optimization | Checksum: 1bb596469
-
- Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
-
- Starting Connectivity Check Task
-
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
- Ending Logic Optimization Task | Checksum: 1bb596469
-
- Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
- INFO: [Common 17-83] Releasing license: Implementation
- 24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- opt_design completed successfully
- opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
- INFO: [Chipscope 16-241] No debug cores found in the current design.
- Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
- or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
- Command: place_design -directive RuntimeOptimized
- Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
- Running DRC as a precondition to command place_design
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-
- Starting Placer Task
- INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
-
- Phase 1 Placer Initialization
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
-
- Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
-
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 1.2 Build Placer Netlist Model
- Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
-
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 1.3 Constrain Clocks/Macros
- Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
-
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Phase 1 Placer Initialization | Checksum: f331096b
-
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 2 Global Placement
- Phase 2 Global Placement | Checksum: 7e244a0f
-
- Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3 Detail Placement
-
- Phase 3.1 Commit Multi Column Macros
- Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
-
- Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.2 Commit Most Macros & LUTRAMs
- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
-
- Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.3 Area Swap Optimization
- Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
-
- Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.4 Pipeline Register Optimization
- Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
-
- Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.5 Timing Path Optimizer
- Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
-
- Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.6 Small Shape Detail Placement
- Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
-
- Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.7 Re-assign LUT pins
- Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
-
- Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 3.8 Pipeline Register Optimization
- Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
-
- Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Phase 3 Detail Placement | Checksum: 1c30709cd
-
- Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 4 Post Placement Optimization and Clean-Up
-
- Phase 4.1 Post Commit Optimization
- INFO: [Timing 38-35] Done setting XDC timing constraints.
-
- Phase 4.1.1 Post Placement Optimization
- INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
- Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 4.2 Post Placement Cleanup
- Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 4.3 Placer Reporting
- Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
-
- Phase 4.4 Final Placement Cleanup
- Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Ending Placer Task | Checksum: dd20239e
-
- Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
- INFO: [Common 17-83] Releasing license: Implementation
- 41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- place_design completed successfully
- place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
- report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
- report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
- report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
- Command: route_design -directive RuntimeOptimized
- Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
- Running DRC as a precondition to command route_design
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-
-
- Starting Routing Task
- INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
- Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
-
- Phase 1 Build RT Design
- Phase 1 Build RT Design | Checksum: be9a9a9a
-
- Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 2 Router Initialization
-
- Phase 2.1 Create Timer
- Phase 2.1 Create Timer | Checksum: be9a9a9a
-
- Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 2.2 Fix Topology Constraints
- Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
-
- Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 2.3 Pre Route Cleanup
- Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
-
- Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
- Number of Nodes with overlaps = 0
-
- Phase 2.4 Update Timing
- Phase 2.4 Update Timing | Checksum: 111c71c3e
-
- Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198 | TNS=0.000 | WHS=-0.144 | THS=-6.171 |
-
- Phase 2 Router Initialization | Checksum: 1ee683561
-
- Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 3 Initial Routing
- Phase 3 Initial Routing | Checksum: 10e02a291
-
- Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 4 Rip-up And Reroute
-
- Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 107
- Number of Nodes with overlaps = 0
-
- Phase 4.1.1 Update Timing
- Phase 4.1.1 Update Timing | Checksum: da308246
-
- Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
-
- Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
-
- Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 4.2 Global Iteration 1
- Number of Nodes with overlaps = 1
- Number of Nodes with overlaps = 0
-
- Phase 4.2.1 Update Timing
- Phase 4.2.1 Update Timing | Checksum: 1185cfc05
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
-
- Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 5 Delay and Skew Optimization
-
- Phase 5.1 Delay CleanUp
- Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 5.2 Clock Skew Optimization
- Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 6 Post Hold Fix
-
- Phase 6.1 Hold Fix Iter
-
- Phase 6.1.1 Update Timing
- Phase 6.1.1 Update Timing | Checksum: 16251cbd9
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
-
- Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
- Phase 6 Post Hold Fix | Checksum: 12245b0d3
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 7 Route finalize
-
- Router Utilization Summary
- Global Vertical Routing Utilization = 0.234075 %
- Global Horizontal Routing Utilization = 0.228267 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
- Phase 7 Route finalize | Checksum: 1af3f3601
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 8 Verifying routed nets
-
- Verification completed successfully
- Phase 8 Verifying routed nets | Checksum: 1af3f3601
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 9 Depositing Routes
- Phase 9 Depositing Routes | Checksum: 15d59118d
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Phase 10 Post Router Timing
- INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
-
- INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
- Phase 10 Post Router Timing | Checksum: 15d59118d
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
- INFO: [Route 35-16] Router Completed Successfully
-
- Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
-
- Routing Is Done.
- INFO: [Common 17-83] Releasing license: Implementation
- 56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- route_design completed successfully
- route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
- INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
- INFO: [DRC 23-27] Running DRC with 2 threads
- INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [DRC 23-133] Running Methodology with 2 threads
- INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
- Running Vector-less Activity Propagation...
-
- Finished Running Vector-less Activity Propagation
- 66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- report_power completed successfully
- INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
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