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GPIO_demo.vdi 22KB

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  1. #-----------------------------------------------------------
  2. # Vivado v2016.4 (64-bit)
  3. # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
  4. # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
  5. # Start of session at: Fri Apr 09 23:15:32 2021
  6. # Process ID: 960
  7. # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
  8. # Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
  9. # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
  10. # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
  11. #-----------------------------------------------------------
  12. source GPIO_demo.tcl -notrace
  13. Design is defaulting to srcset: sources_1
  14. Design is defaulting to constrset: constrs_1
  15. INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
  16. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  17. INFO: [Project 1-479] Netlist was created with Vivado 2016.4
  18. INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  19. INFO: [Project 1-570] Preparing netlist for logic optimization
  20. Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
  21. Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
  22. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  23. INFO: [Project 1-111] Unisim Transformation Summary:
  24. A total of 2 instances were transformed.
  25. IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  26. link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
  27. INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
  28. Command: opt_design -directive RuntimeOptimized
  29. INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
  30. Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  31. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  32. Running DRC as a precondition to command opt_design
  33. Starting DRC Task
  34. INFO: [DRC 23-27] Running DRC with 2 threads
  35. INFO: [Project 1-461] DRC finished with 0 Errors
  36. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  37. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
  38. Starting Logic Optimization Task
  39. Implement Debug Cores | Checksum: 11fc7498c
  40. INFO: [Timing 38-35] Done setting XDC timing constraints.
  41. INFO: [Timing 38-2] Deriving generated clocks
  42. Phase 1 Retarget
  43. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  44. INFO: [Opt 31-49] Retargeted 0 cell(s).
  45. Phase 1 Retarget | Checksum: 16f269fca
  46. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
  47. Phase 2 Constant propagation
  48. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  49. INFO: [Opt 31-10] Eliminated 6 cells.
  50. Phase 2 Constant propagation | Checksum: 233a26f9e
  51. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
  52. Phase 3 Sweep
  53. INFO: [Opt 31-12] Eliminated 363 unconnected nets.
  54. INFO: [Opt 31-11] Eliminated 2 unconnected cells.
  55. Phase 3 Sweep | Checksum: 1bb596469
  56. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
  57. Phase 4 BUFG optimization
  58. INFO: [Opt 31-12] Eliminated 0 unconnected nets.
  59. INFO: [Opt 31-11] Eliminated 0 unconnected cells.
  60. Phase 4 BUFG optimization | Checksum: 1bb596469
  61. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
  62. Starting Connectivity Check Task
  63. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
  64. Ending Logic Optimization Task | Checksum: 1bb596469
  65. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
  66. INFO: [Common 17-83] Releasing license: Implementation
  67. 24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  68. opt_design completed successfully
  69. opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
  70. Writing placer database...
  71. Writing XDEF routing.
  72. Writing XDEF routing logical nets.
  73. Writing XDEF routing special nets.
  74. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
  75. INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
  76. INFO: [DRC 23-27] Running DRC with 2 threads
  77. INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
  78. INFO: [Chipscope 16-241] No debug cores found in the current design.
  79. Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
  80. or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
  81. Command: place_design -directive RuntimeOptimized
  82. Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  83. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  84. INFO: [DRC 23-27] Running DRC with 2 threads
  85. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  86. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  87. Running DRC as a precondition to command place_design
  88. INFO: [DRC 23-27] Running DRC with 2 threads
  89. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  90. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  91. Starting Placer Task
  92. INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
  93. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  94. Phase 1 Placer Initialization
  95. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
  96. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
  97. Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
  98. INFO: [Timing 38-35] Done setting XDC timing constraints.
  99. Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
  100. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
  101. Phase 1.2 Build Placer Netlist Model
  102. Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
  103. Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
  104. Phase 1.3 Constrain Clocks/Macros
  105. Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
  106. Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
  107. Phase 1 Placer Initialization | Checksum: f331096b
  108. Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
  109. Phase 2 Global Placement
  110. Phase 2 Global Placement | Checksum: 7e244a0f
  111. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
  112. Phase 3 Detail Placement
  113. Phase 3.1 Commit Multi Column Macros
  114. Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
  115. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
  116. Phase 3.2 Commit Most Macros & LUTRAMs
  117. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
  118. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
  119. Phase 3.3 Area Swap Optimization
  120. Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
  121. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
  122. Phase 3.4 Pipeline Register Optimization
  123. Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
  124. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
  125. Phase 3.5 Timing Path Optimizer
  126. Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
  127. Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  128. Phase 3.6 Small Shape Detail Placement
  129. Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
  130. Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  131. Phase 3.7 Re-assign LUT pins
  132. Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
  133. Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  134. Phase 3.8 Pipeline Register Optimization
  135. Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
  136. Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  137. Phase 3 Detail Placement | Checksum: 1c30709cd
  138. Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  139. Phase 4 Post Placement Optimization and Clean-Up
  140. Phase 4.1 Post Commit Optimization
  141. INFO: [Timing 38-35] Done setting XDC timing constraints.
  142. Phase 4.1.1 Post Placement Optimization
  143. INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
  144. Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
  145. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  146. Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
  147. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  148. Phase 4.2 Post Placement Cleanup
  149. Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
  150. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  151. Phase 4.3 Placer Reporting
  152. Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
  153. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  154. Phase 4.4 Final Placement Cleanup
  155. Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
  156. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  157. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
  158. Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
  159. Ending Placer Task | Checksum: dd20239e
  160. Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
  161. INFO: [Common 17-83] Releasing license: Implementation
  162. 41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  163. place_design completed successfully
  164. place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
  165. Writing placer database...
  166. Writing XDEF routing.
  167. Writing XDEF routing logical nets.
  168. Writing XDEF routing special nets.
  169. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
  170. INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
  171. report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
  172. report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
  173. report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
  174. Command: route_design -directive RuntimeOptimized
  175. Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  176. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  177. Running DRC as a precondition to command route_design
  178. INFO: [DRC 23-27] Running DRC with 2 threads
  179. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  180. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  181. Starting Routing Task
  182. INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
  183. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  184. Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
  185. Phase 1 Build RT Design
  186. Phase 1 Build RT Design | Checksum: be9a9a9a
  187. Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
  188. Phase 2 Router Initialization
  189. Phase 2.1 Create Timer
  190. Phase 2.1 Create Timer | Checksum: be9a9a9a
  191. Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
  192. Phase 2.2 Fix Topology Constraints
  193. Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
  194. Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
  195. Phase 2.3 Pre Route Cleanup
  196. Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
  197. Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
  198. Number of Nodes with overlaps = 0
  199. Phase 2.4 Update Timing
  200. Phase 2.4 Update Timing | Checksum: 111c71c3e
  201. Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  202. INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198 | TNS=0.000 | WHS=-0.144 | THS=-6.171 |
  203. Phase 2 Router Initialization | Checksum: 1ee683561
  204. Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  205. Phase 3 Initial Routing
  206. Phase 3 Initial Routing | Checksum: 10e02a291
  207. Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  208. Phase 4 Rip-up And Reroute
  209. Phase 4.1 Global Iteration 0
  210. Number of Nodes with overlaps = 107
  211. Number of Nodes with overlaps = 0
  212. Phase 4.1.1 Update Timing
  213. Phase 4.1.1 Update Timing | Checksum: da308246
  214. Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  215. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
  216. Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
  217. Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  218. Phase 4.2 Global Iteration 1
  219. Number of Nodes with overlaps = 1
  220. Number of Nodes with overlaps = 0
  221. Phase 4.2.1 Update Timing
  222. Phase 4.2.1 Update Timing | Checksum: 1185cfc05
  223. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  224. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625 | TNS=0.000 | WHS=N/A | THS=N/A |
  225. Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
  226. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  227. Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
  228. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  229. Phase 5 Delay and Skew Optimization
  230. Phase 5.1 Delay CleanUp
  231. Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
  232. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  233. Phase 5.2 Clock Skew Optimization
  234. Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
  235. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  236. Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
  237. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  238. Phase 6 Post Hold Fix
  239. Phase 6.1 Hold Fix Iter
  240. Phase 6.1.1 Update Timing
  241. Phase 6.1.1 Update Timing | Checksum: 16251cbd9
  242. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  243. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
  244. Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
  245. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  246. Phase 6 Post Hold Fix | Checksum: 12245b0d3
  247. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  248. Phase 7 Route finalize
  249. Router Utilization Summary
  250. Global Vertical Routing Utilization = 0.234075 %
  251. Global Horizontal Routing Utilization = 0.228267 %
  252. Routable Net Status*
  253. *Does not include unroutable nets such as driverless and loadless.
  254. Run report_route_status for detailed report.
  255. Number of Failed Nets = 0
  256. Number of Unrouted Nets = 0
  257. Number of Partially Routed Nets = 0
  258. Number of Node Overlaps = 0
  259. Phase 7 Route finalize | Checksum: 1af3f3601
  260. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  261. Phase 8 Verifying routed nets
  262. Verification completed successfully
  263. Phase 8 Verifying routed nets | Checksum: 1af3f3601
  264. Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
  265. Phase 9 Depositing Routes
  266. Phase 9 Depositing Routes | Checksum: 15d59118d
  267. Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
  268. Phase 10 Post Router Timing
  269. INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717 | TNS=0.000 | WHS=0.062 | THS=0.000 |
  270. INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
  271. Phase 10 Post Router Timing | Checksum: 15d59118d
  272. Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
  273. INFO: [Route 35-16] Router Completed Successfully
  274. Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
  275. Routing Is Done.
  276. INFO: [Common 17-83] Releasing license: Implementation
  277. 56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  278. route_design completed successfully
  279. route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
  280. Writing placer database...
  281. Writing XDEF routing.
  282. Writing XDEF routing logical nets.
  283. Writing XDEF routing special nets.
  284. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
  285. INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
  286. INFO: [DRC 23-27] Running DRC with 2 threads
  287. INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
  288. INFO: [Timing 38-35] Done setting XDC timing constraints.
  289. INFO: [DRC 23-133] Running Methodology with 2 threads
  290. INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
  291. INFO: [Timing 38-35] Done setting XDC timing constraints.
  292. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  293. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  294. INFO: [Timing 38-35] Done setting XDC timing constraints.
  295. Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
  296. Running Vector-less Activity Propagation...
  297. Finished Running Vector-less Activity Propagation
  298. 66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  299. report_power completed successfully
  300. INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
  301. #-----------------------------------------------------------
  302. # Vivado v2016.4 (64-bit)
  303. # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
  304. # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
  305. # Start of session at: Fri Apr 09 23:19:20 2021
  306. # Process ID: 1988
  307. # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
  308. # Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
  309. # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
  310. # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
  311. #-----------------------------------------------------------
  312. source GPIO_demo.tcl -notrace
  313. Command: open_checkpoint GPIO_demo_routed.dcp
  314. Starting open_checkpoint Task
  315. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
  316. INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
  317. INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
  318. INFO: [Project 1-479] Netlist was created with Vivado 2016.4
  319. INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  320. INFO: [Project 1-570] Preparing netlist for logic optimization
  321. Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
  322. Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
  323. Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
  324. Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
  325. Reading XDEF placement.
  326. Reading placer database...
  327. Reading XDEF routing.
  328. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
  329. Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
  330. Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
  331. INFO: [Project 1-111] Unisim Transformation Summary:
  332. A total of 2 instances were transformed.
  333. IOBUF => IOBUF (IBUF, OBUFT): 2 instances
  334. INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
  335. open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
  336. Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
  337. Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  338. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  339. Running DRC as a precondition to command write_bitstream
  340. INFO: [DRC 23-27] Running DRC with 2 threads
  341. INFO: [Vivado 12-3199] DRC finished with 0 Errors
  342. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  343. Loading data files...
  344. Loading site data...
  345. Loading route data...
  346. Processing options...
  347. Creating bitmap...
  348. Creating bitstream...
  349. Bitstream compression saved 13383552 bits.
  350. Writing bitstream ./GPIO_demo.bit...
  351. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  352. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  353. INFO: [Common 17-83] Releasing license: Implementation
  354. 14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  355. write_bitstream completed successfully
  356. write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
  357. INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
  358. INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...