No Description
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

System.vhd 8.0KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211
  1. ----------------------------------------------------------------------------------
  2. -- Company: INSA-Toulouse
  3. -- Engineer: Paul Faure
  4. --
  5. -- Create Date: 13.04.2021 10:19:15
  6. -- Module Name: System - Behavioral
  7. -- Project Name: Processeur sécurisé
  8. -- Target Devices: Basys 3 ARTIX7
  9. -- Tool Versions: Vivado 2016.4
  10. -- Description: Environnement du processeur, mapping entre le processeur et la carte
  11. --
  12. -- Dependencies:
  13. -- - Clock_Divider
  14. -- - Pipeline
  15. ----------------------------------------------------------------------------------
  16. library IEEE;
  17. use IEEE.STD_LOGIC_1164.ALL;
  18. -- Lien avec le fichier de contraintes
  19. -- Récupération des leds pour STD_OUT
  20. -- Récupération des switchs pour STD_IN
  21. -- Récupération d'un bouton pour RST
  22. -- Récupération de la clock
  23. entity System is
  24. Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
  25. vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
  26. vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
  27. Hsync : out STD_LOGIC;
  28. Vsync : out STD_LOGIC;
  29. PS2Clk : in STD_LOGIC;
  30. PS2Data : in STD_LOGIC;
  31. btnC : in STD_LOGIC;
  32. CLK : STD_LOGIC);
  33. end System;
  34. architecture Structural of System is
  35. component Pipeline is
  36. Generic (Nb_bits : Natural := 8;
  37. Instruction_En_Memoire_Size : Natural := 29;
  38. Addr_Memoire_Instruction_Size : Natural := 3;
  39. Memoire_Instruction_Size : Natural := 8;
  40. Instruction_Bus_Size : Natural := 5;
  41. Nb_Instructions : Natural := 32;
  42. Nb_Registres : Natural := 16;
  43. Addr_registres_size : Natural := 4;
  44. Memoire_Size : Natural := 32;
  45. Adresse_mem_size : Natural := 5;
  46. Memoire_Adresses_Retour_Size : Natural := 16;
  47. Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
  48. Port (CLK : in STD_LOGIC;
  49. RST : in STD_LOGIC;
  50. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  51. STD_IN_Av : in STD_LOGIC;
  52. STD_IN_Request : out STD_LOGIC;
  53. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  54. STD_OUT_Av : out STD_LOGIC;
  55. STD_OUT_Int : out STD_LOGIC);
  56. end component;
  57. component Pipeline_NS is
  58. Generic (Nb_bits : Natural := 8;
  59. Instruction_En_Memoire_Size : Natural := 29;
  60. Addr_Memoire_Instruction_Size : Natural := 3;
  61. Memoire_Instruction_Size : Natural := 8;
  62. Instruction_Bus_Size : Natural := 5;
  63. Nb_Instructions : Natural := 32;
  64. Nb_Registres : Natural := 16;
  65. Memoire_Size : Natural := 32);
  66. Port (CLK : STD_LOGIC;
  67. RST : STD_LOGIC;
  68. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  69. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
  70. end component;
  71. component PeripheriqueEcran
  72. Generic ( Nb_Bits : Natural);
  73. Port ( CLK : in STD_LOGIC;
  74. CLK_VGA : in STD_LOGIC;
  75. RST : in STD_LOGIC;
  76. vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
  77. vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
  78. vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
  79. Hsync : out STD_LOGIC;
  80. Vsync : out STD_LOGIC;
  81. STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  82. STD_OUT_Av : in STD_LOGIC;
  83. STD_OUT_Int : in STD_LOGIC);
  84. end component;
  85. component PeripheriqueClavier
  86. Generic (Nb_Bits : Natural);
  87. Port ( CLK : in STD_LOGIC;
  88. RST : in STD_LOGIC;
  89. PS2Clk : in STD_LOGIC;
  90. PS2Data : in STD_LOGIC;
  91. STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  92. STD_IN_Av : out STD_LOGIC;
  93. STD_IN_Request : in STD_LOGIC;
  94. STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  95. STD_OUT_Av : out STD_LOGIC);
  96. end component;
  97. component Clock_Divider is
  98. Port ( CLK_IN : in STD_LOGIC;
  99. CLK_OUT : out STD_LOGIC);
  100. end component;
  101. -- signaux auxiliaires
  102. signal my_RST : STD_LOGIC;
  103. signal my_CLK : STD_LOGIC;
  104. signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  105. signal STD_IN_Av : STD_LOGIC := '0';
  106. signal STD_IN_Request : STD_LOGIC := '0';
  107. signal intern_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  108. signal intern_STD_OUT_Av : STD_LOGIC := '0';
  109. signal intern_STD_OUT_Int : STD_LOGIC := '0';
  110. signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  111. signal pipeline_STD_OUT_Av : STD_LOGIC := '0';
  112. signal pipeline_STD_OUT_Int : STD_LOGIC := '0';
  113. signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  114. signal clavier_STD_OUT_Av : STD_LOGIC := '0';
  115. signal clavier_STD_OUT_Int : STD_LOGIC := '0';
  116. constant SECURISED : boolean := true;
  117. begin
  118. -- Diviseur de clock
  119. clk_div : Clock_Divider
  120. port map (CLK_IN => CLK,
  121. CLK_OUT => my_CLK);
  122. -- Generation du processeur en fonction de la condition sécurisé ou non
  123. instance: if (SECURISED) generate
  124. instance_securisee : entity work.Pipeline
  125. generic map (Nb_bits => 16,
  126. Instruction_En_Memoire_Size => 53,
  127. Addr_Memoire_Instruction_Size => 9,
  128. Memoire_Instruction_Size => 512,
  129. Instruction_Bus_Size => 5,
  130. Nb_Instructions => 32,
  131. Nb_Registres => 16,
  132. Addr_registres_size => 4,
  133. Memoire_Size => 32,
  134. Adresse_mem_size => 5,
  135. Memoire_Adresses_Retour_Size => 4,
  136. Adresse_Memoire_Adresses_Retour_Size => 2)
  137. port map (CLK => my_CLK,
  138. RST => my_RST,
  139. STD_IN => STD_IN,
  140. STD_IN_Av => STD_IN_Av,
  141. STD_IN_Request => STD_IN_Request,
  142. STD_OUT => pipeline_STD_OUT,
  143. STD_OUT_Av => pipeline_STD_OUT_Av,
  144. STD_OUT_Int => pipeline_STD_OUT_Int);
  145. else generate
  146. instance_non_securisee : entity work.Pipeline_NS
  147. generic map (Addr_Memoire_Instruction_Size => 9,
  148. Memoire_Instruction_Size => 512)
  149. port map (CLK => my_CLK,
  150. RST => my_RST,
  151. STD_IN => STD_IN,
  152. STD_OUT => pipeline_STD_OUT);
  153. end generate;
  154. instance_perif_ecran : PeripheriqueEcran
  155. generic map ( Nb_Bits => 16)
  156. port map ( CLK => my_CLK,
  157. CLK_VGA => CLK,
  158. RST => my_RST,
  159. vgaRed => vgaRed,
  160. vgaBlue => vgaBlue,
  161. vgaGreen => vgaGreen,
  162. Hsync => Hsync,
  163. Vsync => Vsync,
  164. STD_OUT => intern_STD_OUT,
  165. STD_OUT_Av => intern_STD_OUT_Av,
  166. STD_OUT_Int => intern_STD_OUT_Int);
  167. instance_perif_clavier : PeripheriqueClavier
  168. generic map (Nb_Bits => 16)
  169. port map ( CLK => my_CLK,
  170. RST => my_RST,
  171. PS2Clk => PS2Clk,
  172. PS2Data => PS2Data,
  173. STD_IN => STD_IN,
  174. STD_IN_Av => STD_IN_Av,
  175. STD_IN_Request => STD_IN_Request,
  176. STD_OUT => clavier_STD_OUT,
  177. STD_OUT_Av => clavier_STD_OUT_Av);
  178. -- Gestion du RST (inversion d'état)
  179. my_RST <= '1' when btnC = '0' else
  180. '0';
  181. intern_STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
  182. intern_STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
  183. intern_STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
  184. end Structural;