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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 09.07.2021 15:25:56
- -- Design Name:
- -- Module Name: PeripheriqueEcran - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- use work.ScreenProperties.all;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity PeripheriqueEcran is
- Generic ( Nb_Bits : Natural);
- Port ( CLK : in STD_LOGIC;
- CLK_VGA : in STD_LOGIC;
- RST : in STD_LOGIC;
-
- vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
- vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
- vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
- Hsync : out STD_LOGIC;
- Vsync : out STD_LOGIC;
-
- STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
- STD_OUT_Av : in STD_LOGIC;
- STD_OUT_Int : in STD_LOGIC);
- end PeripheriqueEcran;
-
- architecture Behavioral of PeripheriqueEcran is
-
- component VGAControler is
- Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
- VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
- VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
- VGA_HS : out STD_LOGIC;
- VGA_VS : out STD_LOGIC;
-
- X : out X_T;
- Y : out Y_T;
- PIXEL_ON : in STD_LOGIC;
-
- CLK : in STD_LOGIC;
- RST : in STD_LOGIC);
- end component;
-
- component clk_wiz_0
- port
- (-- Clock in ports
- clk_in1 : in std_logic;
- -- Clock out ports
- clk_out1 : out std_logic
- );
- end component;
-
- component Ecran is
- Port ( CLK : in STD_LOGIC;
- RST : in STD_LOGIC;
- Data_Av : in STD_LOGIC;
- Data_IN : in STD_LOGIC_VECTOR (0 to 6);
- X : in X_T;
- Y : in Y_T;
- OUT_ON : out STD_LOGIC);
- end component;
-
- component ScreenDriver
- Generic ( Nb_bits : Natural
- );
- Port ( CLK : in STD_LOGIC;
- Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
- ValueAv : in STD_LOGIC;
- IsInt : in STD_LOGIC;
- OutData : out STD_LOGIC_VECTOR (0 to 6);
- OutDataAv : out STD_LOGIC);
- end component;
-
- signal my_X : X_T := 0;
- signal my_Y : Y_T := 0;
- signal my_PIXEL_ON : STD_LOGIC := '0';
- signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
- signal OutDataAv : STD_LOGIC := '0';
- signal my_CLK : STD_LOGIC := '0';
-
- begin
-
- instanceVGA : VGAControler
- port map( VGA_RED => vgaRed,
- VGA_BLUE => vgaBlue,
- VGA_GREEN => vgaGreen,
- VGA_HS => Hsync,
- VGA_VS => Vsync,
-
- X => my_X,
- Y => my_Y,
- PIXEL_ON => my_PIXEL_ON,
-
- CLK => my_CLK,
- RST => RST);
-
-
- clk_wiz_0_inst : clk_wiz_0
- port map (
- clk_in1 => CLK_VGA,
- clk_out1 => my_CLK
- );
-
-
- instance_Ecran : Ecran
- port map ( CLK => CLK,
- RST => RST,
- Data_Av => OutDataAv,
- Data_IN => OutData,
- X => my_X,
- Y => my_Y,
- OUT_ON => my_PIXEL_ON);
-
- instance_ScreenDriver : ScreenDriver
- Generic map ( Nb_bits => Nb_Bits
- )
- Port map ( CLK => CLK,
- Value => STD_OUT,
- ValueAv => STD_OUT_Av,
- IsInt => STD_OUT_Int,
- OutData => OutData,
- OutDataAv => OutDataAv);
-
- end Behavioral;
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