No Description
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

PeripheriqueClavier.vhd 3.1KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 13.07.2021 09:30:08
  6. -- Design Name:
  7. -- Module Name: PeripheriqueClavier - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity PeripheriqueClavier is
  30. Generic (Nb_Bits : Natural);
  31. Port ( CLK : in STD_LOGIC;
  32. RST : in STD_LOGIC;
  33. PS2Clk : in STD_LOGIC;
  34. PS2Data : in STD_LOGIC;
  35. STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  36. STD_IN_Av : out STD_LOGIC;
  37. STD_IN_Request : in STD_LOGIC;
  38. STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  39. STD_OUT_Av : out STD_LOGIC);
  40. end PeripheriqueClavier;
  41. architecture Behavioral of PeripheriqueClavier is
  42. component KeyboardDriver
  43. Generic (Nb_Bits : Natural);
  44. Port (CLK : in STD_LOGIC;
  45. Data_read : out STD_LOGIC;
  46. Data_av : in STD_LOGIC;
  47. Data : in STD_LOGIC_VECTOR (0 to 6);
  48. STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  49. STD_IN_Av : out STD_LOGIC;
  50. STD_IN_Request : in STD_LOGIC;
  51. STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  52. STD_OUT_Av : out STD_LOGIC);
  53. end component;
  54. component Keyboard
  55. Port (CLK : in STD_LOGIC;
  56. PS2Clk : in STD_LOGIC;
  57. PS2Data : in STD_LOGIC;
  58. Data_read : in STD_LOGIC;
  59. Data_av : out STD_LOGIC;
  60. Data : out STD_LOGIC_VECTOR (0 to 6);
  61. alert : out STD_LOGIC);
  62. end component;
  63. signal Data_read : STD_LOGIC := '0';
  64. signal Data_av : STD_LOGIC := '0';
  65. signal Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
  66. signal nothing : STD_LOGIC := '0';
  67. begin
  68. instance_Keyboard : Keyboard
  69. port map (CLK => CLK,
  70. PS2Clk => PS2Clk,
  71. PS2Data => PS2Data,
  72. Data_read => Data_read,
  73. Data_av => Data_av,
  74. Data => Data,
  75. alert => nothing);
  76. instance_KeyboardDriver : KeyboardDriver
  77. generic map (Nb_Bits => Nb_Bits)
  78. port map (CLK => CLK,
  79. Data_read => Data_read,
  80. Data_av => Data_av,
  81. Data => Data,
  82. STD_IN => STD_IN,
  83. STD_IN_Av => STD_IN_Av,
  84. STD_IN_Request => STD_IN_Request,
  85. STD_OUT => STD_OUT,
  86. STD_OUT_Av => STD_OUT_Av);
  87. end Behavioral;