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KeyboardDriver.vhd 2.5KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 13.07.2021 09:30:08
  6. -- Design Name:
  7. -- Module Name: KeyboardDriver - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23. use IEEE.NUMERIC_STD.ALL;
  24. -- Uncomment the following library declaration if using
  25. -- arithmetic functions with Signed or Unsigned values
  26. --use IEEE.NUMERIC_STD.ALL;
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx leaf cells in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31. entity KeyboardDriver is
  32. Generic (Nb_Bits : Natural);
  33. Port (CLK : in STD_LOGIC;
  34. Data_read : out STD_LOGIC;
  35. Data_av : in STD_LOGIC;
  36. Data : in STD_LOGIC_VECTOR (0 to 6);
  37. STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  38. STD_IN_Av : out STD_LOGIC;
  39. STD_IN_Request : in STD_LOGIC;
  40. STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
  41. STD_OUT_Av : out STD_LOGIC);
  42. end KeyboardDriver;
  43. architecture Behavioral of KeyboardDriver is
  44. signal intern_value : Natural := 0;
  45. signal work_in_progress : BOOLEAN := false;
  46. signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0');
  47. begin
  48. process
  49. begin
  50. wait until CLK'event and CLK = '1';
  51. STD_IN_Av <= '0';
  52. STD_OUT_Av <= '0';
  53. if not(work_in_progress) then
  54. intern_value <= 0;
  55. end if;
  56. if STD_IN_Request = '1' then
  57. work_in_progress <= true;
  58. if Data_av = '1' then
  59. STD_OUT <= Zeros & Data;
  60. STD_OUT_Av <= '1';
  61. if (Data = "1111111") then
  62. intern_value <= intern_value / 10;
  63. elsif (Data = "0001101") then
  64. STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits));
  65. STD_IN_Av <= '1';
  66. work_in_progress <= false;
  67. elsif (Data >= "0110000" and Data <= "0111001") then
  68. intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6)));
  69. end if;
  70. end if;
  71. end if;
  72. end process;
  73. Data_read <= '0' when STD_IN_Request = '0' else Data_av;
  74. end Behavioral;